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> > It does not direct relate to the NV aspect, but Paul was talking about > > the SRAM contained in an FPGA. So I throwed in my larger SRAM wish. > > This Code-Ram should also be able to be Wide path and split, so > that multiple cores can be supported, with wide opcodes if desired. > Now you are opening the the wish list to this SRAM block. Perhaps that's one problem for such a feature. If A & X would integrate such a block they have to satisfy too many diverse requests. However, you can implement different interfaces to this block (split, multi port) by your own logic with multi-cycle access. > Given the relatively high Static Icc now of FPGAs, it would also > make sense to look at Self-refresh DRAM - DRAM is much more die > efficent. This would make the usage of the RAM more complicated. You have to account for the busy cycles introduced by DRAM refreshing. And AFAIK DRAM is a little different process that 'standard' cmos. > Serial 'Data Storage' Flash is getting better all the time, and could > serve as code memory in some instances. 'Jumps outside the Cache' would > be relatively costly, but the streaming speeds are getting quite good. I would generally copy the code into the RAM befor execution. With an on-chip RAM you could perhaps abandon the instruction and code cache. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 74101
Hi. I am using ISE 6.2 for xc2vp30,-6 that compiles for 100 MHz. Now I am trying to stretch the design to 133 MHz. Can anyone compare the performance improvement of ISE 6.3 vs. ISE 6.2 (if any) ? THANKXArticle: 74102
> What are these, and how essential they are > if I (eventually/immediately) want to do my own designs? > Not very essential. You can do a lot with the free versions of ISE and Quartus. All work I've done so far also compiles on the free Quartus version (I have little experience on the ISE). E.g. You don't need CoreGen to use the BRAM in the devices. It makes it simpler, but you can instantiate these blocks with straight VHDL. See as an example JOP that compiles from the plain VHDL sources on the free versions of Xilinxs ISE and Alteras Quartus. Martin ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/Article: 74103
Hello, according Xilinx Homepage http://www.xilinx.com/products/tables/fpga.htm#v2 my FPGA (XC2V1000) should have 720 kbit Block-RAM. But if I look into it, using the FPGA Editor a Blockram has two units each 2048*9 bits e.g. furthermore the whole FPGA has 4x10 RAM blocks. This results in 2048*9 * 2 * 4 * 10 = 1440 kbit, of course twice of Xilinx' specification. Since 4 columns and 10 rows are surely right, the presumption of 2 units per block has to be wrong. Please point me out where I'm wrong! Bye Tom.Article: 74104
"valentin tihomirov" <spam@abelectron.com> wrote in message news:<2sadlpF1iu5e1U1@uni-berlin.de>... > Occasionally, I've discovered that the result of synthesis (default effort) > depends on the instances order. I can bring a complete example but in short > the illustration is following: > > -- 24 LUTs > architecture RTL is > begin > U1: entity .. > U2: entity .. > > > -- 27 LUTs > architecture RTL is > begin > U2: entity .. > U1: entity .. > > This fact complicates comparition of different design configurations. Is it > normal? I've checked Synplify -- it always gives the same results > irrespecively to the units order. I've seen Synplify give different results after just changing the name of a net (and all references to it)! Cheers, JonArticle: 74105
"Jon Beniston" <jon@beniston.com> wrote in message news:e87b9ce8.0410031527.6e5b295e@posting.google.com... > "David Brown" <david@no.westcontrol.spam.com> wrote in message news:<cjm4ke$p5$1@news.netpower.no>... > > "Antti Lukats" <antti@case2000.com> wrote in message > > news:cjjtgn$mp6$03$1@news.t-online.com... > > > "Jon Beniston" <jon@beniston.com> wrote in message > > > news:e87b9ce8.0410010514.6fa501a@posting.google.com... > > > > > # Xilinx benefit if MicroBlaze is in the news > > > > > > > > > > # Such efforts expand usage of, and research in, MicroBlaze > > > > > > > > > > # It can be a usefull second opinion / benchmark > > > > > > > > > > # Xilinx will have trademark rights to MicroBlaze, so they can > > > > > restrict use of the name. Other examples of this are 6805 uC and i2c > > > > > instances. > > > > > > > > > > # The open source core is only a tiny portion of system development: > > > > > you also have compilers/SWdebuggers/HWDebuggers/Libraries, and all of > > > > > those will have Xilinx license restrictions for Xilinx FPGAs. > > > > > > > > Actully, the compiler & I believe the debugger are open source. This > > > > means that people are very close to having everything for free. > > > > > > 1) The compiler and binutils are GPL GNU stuff - that is Xilinx *must* > > > provide the source of the those GNU tools in source code form at no > > charge, > > > what they are doing, the gnu source of the tools is freely available from > > > Xilinx. And due to the GPL licensing they can not limit the access to that > > > source code. > > > > Xilinx don't have to provide the source free of charge. What they have to > > do is provide an offer to those who have access to the binaries, offering > > them the source code for no more than a reasonable distribution fee. They > > have no obligation to make the source code available to anyone else, nor do > > they have to make it free (as in beer), only free (as in speach). However, > > if someone buys a MicroBlaze development kit including the compiler, etc., > > then Xilinx must provide the source code to that someone, and they can then > > pass it on freely if they want. What this boils down to is that Xilinx has > > no obligations to make the tools easily available, but if someone posts the > > tools on opencores then Xilinx cannot complain (except perhaps regarding > > trademarks on the name). > > They do actually provide the source code for free. There is a link on > their web site. > So I've heard - I haven't looked (being a Nios user myself). I was merely correcting a misconception as to Xilinx's obligations under the GPL. It looks like they are happy to go beyond the letter of the law and are supporting the spirit of the GPL by making the source code easily available.Article: 74106
Hi > I am working on the Xilinx ML300 prototying board. I have a Linux image > that needs to be uploaded to the DDR memroy. > > I tried for a few days and was unable to figure out how this can be done. > Can any one kindly give me some hints? > > Even if you may not have the board, can you share your experience on how > usually this is done? First, I must insist that I have no experience with ML300 so no guarantee that what I propose is "the way to go (tm)". But can't you use some BRAM as a ROM, then put the bootloader in it (since it's small), then make your processor boot that rom. Then the bootloader, inits what need to be initialized for linux to run (like the DDR memory controller), then download the image from the outside world (or from some other BRAM blocks ... ) That's how it works in usual embedded systems I worked with that don't use FPGA. Here, the BRAM is just used for the purpose of what flash is used on other systems ... SylvainArticle: 74107
>>Occasionally, I've discovered that the result of synthesis (default effort) >>depends on the instances order. I can bring a complete example but in short >>the illustration is following: >> >>-- 24 LUTs >>architecture RTL is >>begin >> U1: entity .. >> U2: entity .. >> >> >>-- 27 LUTs >>architecture RTL is >>begin >> U2: entity .. >> U1: entity .. >> >>This fact complicates comparition of different design configurations. Is it >>normal? I've checked Synplify -- it always gives the same results >>irrespecively to the units order. > > > I've seen Synplify give different results after just changing the name > of a net (and all references to it)! I guess that synthesis tools uses heuristics to find how to do the synthesis. They try to find the "best" solution but just can't try every possibilities. So the results depends on "how good" are theses heuristics. Since the input is different, the result can be different as well ... SylvainArticle: 74108
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:41602609.1F9E7D64@yahoo.com... > Martin Schoeberl wrote: > > > > > > that's really nice (and funny) how much used this single board gets > > ;-) > > > > And a MB on an Altera FPGA, that's the end of the world. > > > > BTW: I have some more ACEX boards. I could donate them (or a small > > fee..) > > > > for projects that can convince me... > > > > > > I am looking at prototyping boards for a CPU in an ACEX 1K50. Do you > > > have anything with that chip? How much would you want for it? > > > > > Yes, the boards are with the ACEX 1K50. Is EUR 75,- ok? > > The price sounds good. Where can I get some info on these boards? > http://www.jopdesign.com/board.jsp MartinArticle: 74109
Nahum Barnea wrote:
> Hi.
>
> I am using ISE 6.2 for xc2vp30,-6 that compiles for 100 MHz.
> Now I am trying to stretch the design to 133 MHz.
>
> Can anyone compare the performance improvement of ISE 6.3 vs. ISE 6.2 (if any) ?
Howdy Nahum,
I recently switched from 6.2.3i to 6.3.1i and did not notice any
performance increase. In fact, performance actually went down slightly
until I tweaked some project settings.
Having said that, there are timing related bug fixes in 6.3.1i,
including one I was running into previously: falling edge to falling
edge wasn't timed properly. Who knows what else was fixed, so it might
be worthwhile to upgrade. We always keep previous versions installed
anyway, so switching back and forth shouldn't be a problem.
My design is a 2VP40-5 in which a total of 82% of all LUTs are used,
over half of which run at 155 MHz and the remainder run at 125 MHz.
Assuming the design you are working with is pipelined, 133 MHz should
not be too difficult to meet in a -6 part unless it is really full.
Good luck,
Marc
Article: 74110Hello, is there a possibility to use the Chipscope to inspect the content of BlockRam? Bye TomArticle: 74111
hi, what is the definition of the term "Field-programmble" inside "FPGA"? It could be: 1. programable in the field (on application sites) or 2."electrically programable" in contrast to "mask programmble" any literature to the the definition of the term "field-programmble" is welcome. Thank you. Chong chongws_at_gmail.comArticle: 74112
On Mon, 04 Oct 2004 11:29:26 +0200, Sylvain Munaut wrote: > >>>Occasionally, I've discovered that the result of synthesis (default effort) >>>depends on the instances order. I can bring a complete example but in short >>>the illustration is following: >>> >>>-- 24 LUTs >>>architecture RTL is >>>begin >>> U1: entity .. >>> U2: entity .. >>> >>> >>>-- 27 LUTs >>>architecture RTL is >>>begin >>> U2: entity .. >>> U1: entity .. >>> >>>This fact complicates comparition of different design configurations. Is it >>>normal? I've checked Synplify -- it always gives the same results >>>irrespecively to the units order. >> >> >> I've seen Synplify give different results after just changing the name >> of a net (and all references to it)! > > I guess that synthesis tools uses heuristics to find how to do the synthesis. > They try to find the "best" solution but just can't try every possibilities. > So the results depends on "how good" are theses heuristics. Since the input > is different, the result can be different as well ... > > > Sylvain It's not necessarily the synthesis tool that's giving different results, it's more likely map and par. The slightest change in the netlist or the constraints file causes map and par to give very different results. I've seen a 5% difference in the slice count if map and par find an easy solution or not.Article: 74113
"Antti Lukats" <antti@case2000.com> wrote in message news:<cjp9u0$dpl$03$1@news.t-online.com>... > "iceman" <static123ph@yahoo.com> wrote in message > news:62011d8f.0410030504.40932424@posting.google.com... > > ei anyone can help me with the algorithm on how to control a > > servomotor... cause we are gonna use it on our thesis... by the it's > > called "FPGA based intravenous infusion monitoring and control system" > > > > can anyone help us out on how to control a servomotor...will be using > > the servomotor to clamp the tube of an I.V.(intravenous) tube... the > > flow of the algorithm will bw this... first a personnel will input how > > many dosage a patient gets and then the servomotor will clamp the I.V. > > tube so that the desired dosage is achive... by the way will be using > > optical sensors to monitor the drops of the I.V. fluid i will be > > placed at the outside of the drip chamber... > > > > but we have a problem what if the drip of the fluid change how will > > the servomotor adjust it so that the dosage will be maintained...will > > use a feedback but how are we gonna implement it on FPGA.. > > > > got any suggestion on the algorithm... or any sites that can help us > > solve this problem > > you did not specify what type of servo you need to control, if that R/C > servo then that can be easily connected to FPGA there are some free ip cores > for that. > > BUT controlling R/C servo and doing some algorithm is way simpler faster and > cheaper when implemented using some small microcontroller not an FPGA - so > unless there are other reasons to use FPGA then microcontroller based design > would be better choice > > antti =============================================================================== were going to use R/C type of servomotor... any suggestions on the servomotor that we are going to use...Article: 74114
On 4 Oct 2004 05:13:22 -0700, chongws@gmail.com (Wei-sheng Chong) wrote: >hi, > > what is the definition of the term "Field-programmble" inside >"FPGA"? It could be: >1. programable in the field (on application sites) or >2."electrically programable" in contrast to "mask programmble" > > any literature to the the definition of the term >"field-programmble" is welcome. > >Thank you. > >Chong >chongws_at_gmail.com Either - it just means programmable after manufacture, as opposed to masked.Article: 74115
"Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message news:10lnrtjlg7sff75@news.supernews.com... > > "Markus Meng" <meng.engineering@bluewin.ch> wrote in message > news:aaaee51b.0409290819.a6020e5@posting.google.com... > > Hi all [SOPC users], > > > > is there a way a can configure the read burst length of the > > standard SDRAM controller within SOPC 4.1? > > > > Best Regards > > Markus > > Hi Markus, > > You might try asking this over on the Nios Forum (www.niosforum.com). I'd > like to know the answer as well. I looked through the controller's > class.ptf file and even the verilog source and don't see anything. > > On writes however, I'm getting bursts of at least 480 long words at one > clock per word. (my system is running at 75MHz) > Did you have to do anything special to achieve that? I have a custom peripheral that is writing as fast as it can to the sdram, but I'm getting one 32-bit write every 3 clocks. With the prototype system I have at the moment, that's good enough, but I'd like to improve on it when we start making the real thing. When reading, I'm getting one read every 2 clocks - again, it's not ideal but it works. I'd expect one read/write per clock for most of the burst, with some waits while changing banks or refreshing. Also, my reader and writer peripherals are independant, so sometimes they coincide. The Avalone bus arbitration apparently cannot take bursting into account, and swaps between the two accesses. Is there any way this can be improved upon, or do I have to implement my own mini-arbitrator to control the two peripherals?Article: 74116
Hello everyone, I have a very basic master state machine that is clocked at 200Mhz in a virtexII-pro. It has an asynchronous reset input that comes from a push-button on the board. Code looks like this: always @ (posedge mclk or negedge resetb) begin if (~resetb) begin state <= rst; end else begin case(state) rst : begin state <= rstInputStage; etc... When I perform a post-place and route simulation, I get some timing errors depending on when I de-assert 'resetb' in the testbench. If it is too close to a rising clock edge, everything becomes red in the waveform. I understand there are some setup/hold conditions, but I wonder what will happens in real life since at 200Mhz, it looks like I get timing errors most of the times...actually, I need to de-assert resetb very close to the falling edge of the clock. Anywhere else gives errors. Are there any solutions to this? Thanks, DavidArticle: 74117
jon@beniston.com (Jon Beniston) writes: > > 2) It is not of big news yet, but the new EDK software ide is based on > > Open-Source Eclipse Platform as well, but Eclipse licensing is different so > > using Xilinx Eclipse tools is possible not free, but as Eclipse itself is > > free and Open-Source there are no limitations for 3rd parties to develop > > Eclipse based IDE for the Open-Source M*Blaze > > No doubt their version of eclipse will be based on the standard C/C++ > plugin with a few extras. It's already pretty easy to set eclipse up > to target MicroBlaze / NIOS / any other GNU toolchain based processor. What do you need eclipse for anyway? I'm happy with a makefile and emacs... Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 74118
Each BRAM has two ports into the same memory array; The two 2kx9 ports
address the same 18K bits, but permit simultaneous independent access.
Thomas Reinemann wrote:
> Hello,
>
> according Xilinx Homepage
> http://www.xilinx.com/products/tables/fpga.htm#v2 my FPGA (XC2V1000)
> should have 720 kbit Block-RAM. But if I look into it, using the FPGA
> Editor a Blockram has two units each 2048*9 bits e.g. furthermore the
> whole FPGA has 4x10 RAM blocks. This results in
> 2048*9 * 2 * 4 * 10 = 1440 kbit, of course twice of Xilinx'
> specification. Since 4 columns and 10 rows are surely right, the
> presumption of 2 units per block has to be wrong.
>
> Please point me out where I'm wrong!
>
> Bye Tom.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 74119
Hello Everybody.
First of all thanks antti for your FSL File, now I understand the Read in
Process.
http://xilinx.openchip.org
But for me also very important is to write the data out after the
calculation is finished. Here is my actual
VHDL Code, so the readin should be okay, and then I only assign the output
value the input value after this
valid. Then I want to read it out, but unfortunately I always get Output =
0, althought I write different values from 1 up to 5 at the data input port!
So can perhaps someone give me a hint what is wrong here? Antti do you have
a solution for this perhaps?
begin -- architecture IMP
FSL0_S_Read <= FSL_S_Read_i;
FSL_S_Read_i <= FSL0_S_Exists;
FSL0_M_DATA <= FSL0_S_Data; -- Output = Input
FSL0_M_Write <= '1'; -- Indicates Data is
available for reading
end architecture IMP;
Test Code
int data_to_local_link[] = { 1,2,3,4,5 };
int data_back_local_link[5];
for (k=0;k<5;k++){
microblaze_nbwrite_datafsl(data_to_local_link[k],0);
microblaze_nbread_datafsl(data_back_local_link[k],0);
xil_printf("Testvalue :%x\n\r",data_back_local_link[k]);
Output:
Testvalue :0
Testvalue :0
Testvalue :0
Testvalue :0
Testvalue :0
Cheers
Roger
Article: 74120David wrote: > Hello everyone, > I have a very basic master state machine that is clocked at 200Mhz in > a virtexII-pro. It has an asynchronous reset input that comes from a > push-button on the board. Code looks like this: > > always @ (posedge mclk or negedge resetb) > begin > if (~resetb) begin > state <= rst; > end > else begin > case(state) > rst : > begin > state <= rstInputStage; > etc... > > When I perform a post-place and route simulation, I get some timing > errors depending on when I de-assert 'resetb' in the testbench. If it > is too close to a rising clock edge, everything becomes red in the > waveform. I understand there are some setup/hold conditions, but I > wonder what will happens in real life since at 200Mhz, it looks like I > get timing errors most of the times...actually, I need to de-assert > resetb very close to the falling edge of the clock. Anywhere else > gives errors. Are there any solutions to this? > Thanks, > David One solution would be to synchronize your asynchronous reset by one flip-flop with his D input connected to the VCC and his RST input connected to your actual asynchronous reset, and the Q output is your new pseudo-asynchronous reset of your actual design. Larry www.amontec.comArticle: 74121
Hi,
The problem is that the Write signal is not a ready signal for
MicroBlaze but it's a write signal into a FIFO.
So what you have done is to write new values EVERY clock cycle into the
FIFO which will get full very fast.
If you only want to write back the value that you read, then you should
do this instead.
FSL0_M_Write <= FSL_S_Read_i;
This will ensure that you only write when you have valid input data.
Göran
Roger Planger wrote:
>Hello Everybody.
>
>First of all thanks antti for your FSL File, now I understand the Read in
>Process.
>
>http://xilinx.openchip.org
>
>But for me also very important is to write the data out after the
>calculation is finished. Here is my actual
>VHDL Code, so the readin should be okay, and then I only assign the output
>value the input value after this
>valid. Then I want to read it out, but unfortunately I always get Output =
>0, althought I write different values from 1 up to 5 at the data input port!
>So can perhaps someone give me a hint what is wrong here? Antti do you have
>a solution for this perhaps?
>
>begin -- architecture IMP
> FSL0_S_Read <= FSL_S_Read_i;
> FSL_S_Read_i <= FSL0_S_Exists;
> FSL0_M_DATA <= FSL0_S_Data; -- Output = Input
> FSL0_M_Write <= '1'; -- Indicates Data is
>available for reading
>end architecture IMP;
>
>Test Code
>
>int data_to_local_link[] = { 1,2,3,4,5 };
>int data_back_local_link[5];
>
>for (k=0;k<5;k++){
> microblaze_nbwrite_datafsl(data_to_local_link[k],0);
> microblaze_nbread_datafsl(data_back_local_link[k],0);
> xil_printf("Testvalue :%x\n\r",data_back_local_link[k]);
>
>Output:
>
>Testvalue :0
>Testvalue :0
>Testvalue :0
>Testvalue :0
>Testvalue :0
>
>Cheers
>Roger
>
>
>
>
>
Article: 74122Thanks Ray, that helps a lot. "Ray Andraka" <ray@andraka.com> wrote in message news:415DB39C.5E625004@andraka.com... > Generally speaking (I'll talk about the exceptions in a second), the generic > gets the init value passed to the simulator but not to the hardware, and the > init attribute passes it to the hardware. So assuming that is the case, you need > the init attribute on the primitive in order to pass the initialization to the > edif netlist (and thus on to the bit file). The attributes are ignored by > simulation, so you need to set the primitive up with a generic in order to > initialize the simulation so that it matches the hardware. > > About a year ago, some synthesis tools started parsing certain generics like the > init generic to automatically pass the generic value to the hardware > (essentially by automatically adding an init=attribute), so if you have one of > those synthesis tools, you technically do not need to include an init > attribute. However, if you want your code portable between tools that do this > and tools that don't, then you need to make so the tool ignores the generic when > it synthesizes the design. The translate_on/off pragmas are a switch that cause > the synthesis to skip over those lines (it you don't then you end up with two > inits in the edif which causes problems in the translate in the xilinx tool > chain). > > The code you have here has the generic, but it is ignored in synthesis so it > never gets passed to the bitstream regardless of whether the tool can do it or > not. You are missing the matching INIT attribute, which I see you have in one > of the follow up posts. > > Another thing, you should consider using ieee.numeric_std instead of > std_logic_arith and std_logic_unsigned. It is an ieee standard and contains > definitions for both signed and unsigned types. STD_LOGIC_UNSIGNED, > STD_LOGIC_SIGNED, and STD_LOGIC_ARITH are not standard meaning you can get > different behavior out of different vendors libraries. Also the signed and > unsigned libraries have conflicting definitions which presents problems if you > have a design that uses both. > > Brad Smallridge wrote: > > > OK. What is wrong with this code? I am expecting to initiate the SRL16 with > > some sort of pattern, then loop it around continuously in a 10 bit pattern, > > put it to a pad where I can see it with a scope. I get a one little blip > > but not much. > > > > library IEEE; > > use IEEE.STD_LOGIC_1164.ALL; > > use IEEE.STD_LOGIC_ARITH.ALL; > > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > > > library UNISIM; > > use UNISIM.VComponents.all; > > > > entity srltest is > > port( > > clk : in std_ulogic; > > q : out std_ulogic ); > > end srltest; > > > > architecture Behavioral of srltest is > > > > component SRL16 > > -- synthesis translate_off > > generic ( > > INIT: bit_value:= X"1001"); > > -- synthesis translate_on > > port (Q : out STD_ULOGIC; > > > > A0 : in STD_ULOGIC; > > A1 : in STD_ULOGIC; > > A2 : in STD_ULOGIC; > > A3 : in STD_ULOGIC; > > CLK : in STD_ULOGIC; > > D : in STD_ULOGIC); > > end component; > > -- Component Attribute specification for SRL16 > > -- should be placed after architecture declaration but > > -- before the begin keyword > > -- Enter attributes in this section > > -- Component Instantiation for SRL16 should be placed > > -- in architecture after the begin keyword > > > > signal feedback : std_ulogic; > > > > begin > > > > SRL16_INSTANCE_NAME : SRL16 > > -- synthesis translate_off > > generic map( > > INIT => X"7878" ) > > -- synthesis translate_on > > port map (Q => feedback , > > A0 => '0', > > A1 => '1', > > A2 => '0', > > A3 => '1', > > CLK => clk, > > D => feedback ); > > > > q <= feedback; > > > > end Behavioral; > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 74123
Is it possible to take the FPGA.hex file, for example and given that you know the device, reverse-engineer it into either it's CLB map or back to it's high-level HDL code?Article: 74124
Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com> wrote in message news:<416118b5$0$22083$ba620e4c@news.skynet.be>... > >>Occasionally, I've discovered that the result of synthesis (default effort) > >>depends on the instances order. I can bring a complete example but in short > >>the illustration is following: > >> > >>-- 24 LUTs > >>architecture RTL is > >>begin > >> U1: entity .. > >> U2: entity .. > >> > >> > >>-- 27 LUTs > >>architecture RTL is > >>begin > >> U2: entity .. > >> U1: entity .. > >> > >>This fact complicates comparition of different design configurations. Is it > >>normal? I've checked Synplify -- it always gives the same results > >>irrespecively to the units order. most of the synthesizers re-synthesize the entire design whenever there is a change in the code (even a slightest one). therefore when you change your code the synthesizer can produce a different result. however a situation as you descired usually occurs when the code is not writen in a way that is easy for the synthesizer to understand (therefore a code revising may be needed), but this is not always the case sometimes the error can be caused by the synthesizer itself. You also mentioned that in Synplify it works well (i.e. - no change due to the swap between the entity positions), that's also very resonable because each synthesizer / simulator synthesize the entire design by itself and acording to its own predifined algorithms. > > > > > > I've seen Synplify give different results after just changing the name > > of a net (and all references to it)! > > I guess that synthesis tools uses heuristics to find how to do the synthesis. > They try to find the "best" solution but just can't try every possibilities. > So the results depends on "how good" are theses heuristics. Since the input > is different, the result can be different as well ... > > > Sylvain
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