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Hi When I am trying to load the verilog design to xst, I am receiving the followin errors: ERROR:HDLParsers:340 Entity <test> does not exist in library <work> ERROR:Xst:1876 - Entity <test> not found, Recompile it. I am using the newest Xilinx ISE 6.3i I have tried to fin out more about this errors on Xilinx web page, but I was unsuccessful. Do you have any ideas how to get rid of this errors?? thank you in advance Dominik GawlowskiArticle: 73851
"Markus Meng" <meng.engineering@bluewin.ch> wrote in message news:aaaee51b.0409290819.a6020e5@posting.google.com... > Hi all [SOPC users], > > is there a way a can configure the read burst length of the > standard SDRAM controller within SOPC 4.1? > > Best Regards > Markus Hi Markus, You might try asking this over on the Nios Forum (www.niosforum.com). I'd like to know the answer as well. I looked through the controller's class.ptf file and even the verilog source and don't see anything. On writes however, I'm getting bursts of at least 480 long words at one clock per word. (my system is running at 75MHz) KenArticle: 73852
On Wed, 29 Sep 2004 20:57:30 -0600, hamilton <hamilton@deminsional.com> wrote: >> Forth is very good for small embedded design. > >Forth is the perfect hacker language. >Write it once and no one else will able to read it again. I've read far too much driver code in C to believe this. It is possible (and far too frequent) to write unreadable code in any language. Professionally, I write Forth compilers and do applications consulting, mostly in Forth. I also have to read and write C code. One of the Forth applications I have to support is used all over the world and consists of 850,000+ lines of source code. MPE also supports a wide range of embedded applications, both large and small. After using a wide range of programming languages for a very long time I have come to the conclusion that readability of source code has very little to do with the programming language. It has a lot to do with the attitude of the programmer and particularly of the management. Here at MPE we use tools that extract documentation from source code. Similar tools exist for other languages, but are rarely used. This is a shame, as using good tools can dramatically affect coding style. Stephen -- Stephen Pelc, stephenXXX@INVALID.mpeltd.demon.co.uk MicroProcessor Engineering Ltd - More Real, Less Time 133 Hill Lane, Southampton SO15 5AF, England tel: +44 (0)23 8063 1441, fax: +44 (0)23 8033 9691 web: http://www.mpeltd.demon.co.uk - free VFX Forth downloadsArticle: 73853
"Symon" <symon_brewer@hotmail.com> wrote in message news:<2s0n6qF1f8t1eU1@uni-berlin.de>... > In case people start targeting MicroBlaze and its tools at vendor A's parts? That and the fact that it is actually a product they sell. Cheers, JonArticle: 73854
Hi I have the Cyclone 1C20 board from Altera. But when I finish downloading the program with JTAG mode,the board does not excecute my program,but exceute the program stored in the rom. What can I do to made the board excecute my program? thanksArticle: 73855
Hello Would somebody be so kind and email me please the files for the following tutorial? http://www.xilinx.co.jp/products/software/sysgen/app_docs/user_guide_Chapter_7_Section_11.htm The should be located in the directory: $SYSGEN\examples\EDK\rgb2gray of your EDK6.3 Thanks a lot for your help CheersArticle: 73856
Hello, I am looking for the internal organization of the Virtex-II , for instance the Major and Minor Addresses, how the column are divided and how many frames they have ... /Cyrille LambertArticle: 73857
The only thing I see is that you should get an 11-clock loop because the delay through the SRL is one more than the number on the A inputs (all A's zero gives one clock delay). Are you saying it won't simulate, or that you built it and it doesn't do what the simulation did? If you're going to synthesize this you'd need to add the INIT function to your ucf file or source code. The synthesizer is turned off when the generics are processed. "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10lmu0t8b47l75a@corp.supernews.com>... > OK. What is wrong with this code? I am expecting to initiate the SRL16 with > some sort of pattern, then loop it around continuously in a 10 bit pattern, > put it to a pad where I can see it with a scope. I get a one little blip > but not much. > > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > library UNISIM; > use UNISIM.VComponents.all; > > entity srltest is > port( > clk : in std_ulogic; > q : out std_ulogic ); > end srltest; > > architecture Behavioral of srltest is > > component SRL16 > -- synthesis translate_off > generic ( > INIT: bit_value:= X"1001"); > -- synthesis translate_on > port (Q : out STD_ULOGIC; > > A0 : in STD_ULOGIC; > A1 : in STD_ULOGIC; > A2 : in STD_ULOGIC; > A3 : in STD_ULOGIC; > CLK : in STD_ULOGIC; > D : in STD_ULOGIC); > end component; > -- Component Attribute specification for SRL16 > -- should be placed after architecture declaration but > -- before the begin keyword > -- Enter attributes in this section > -- Component Instantiation for SRL16 should be placed > -- in architecture after the begin keyword > > signal feedback : std_ulogic; > > begin > > SRL16_INSTANCE_NAME : SRL16 > -- synthesis translate_off > generic map( > INIT => X"7878" ) > -- synthesis translate_on > port map (Q => feedback , > A0 => '0', > A1 => '1', > A2 => '0', > A3 => '1', > CLK => clk, > D => feedback ); > > q <= feedback; > > end Behavioral;Article: 73858
Has anybody come across a company called Clearspeed Technology?
http://www.clearspeed.com/
Apparently they are about to do a press release next week announcing a
50Gflop/s massively parallel co-processor, you can program it in
standard C. Its being delivered on a 100Gflop/sec PCI-X boardset that
dissipates less than 25watts, which is extraordinary when you consider
that your typical x86 is in the 100watt region for the processor alone.
Worth checking out if anybody is seriously considering using an FPGA to
accelerate their floating point application. Just imagine what you
could do with this, fill up a 6 slot PC with these cards and you have a
do it yourself supercomputer, a few of these could probably take you
into the Top500 supercomputer list.
A.
Article: 73859In article <BGN6d.4506$nj.4491@newssvr13.news.prodigy.com>, Guy <guys@altera.com> wrote: >Nicholas- >Thanks for the response. Unfortunately because of my current employeement, >I can not post as myself like I have done in the past. I recognize that >value and promise in due time, I will do it again. (After this thread I >will change to a different anonymous moniker). > >You raise good points, but it appears that you are making assumptions about >NV memory detection when you mention probing - doesn't that assume that >there is actually a charge (a la flash) stored? What if there was some >other storage mechanism, almost like an un readable ROM bit? No, I am just assuming that because there is something static there, it is easier to probe because you don't need to worry about fubaring the power supply and a bunch of other things in the process. I don't care if its antifuse, FLASH, or MysticPixieGates: the NV ram must have a property where you can repeatedly attempt to distinguish a cell's contents by measuring its behavior without worrying about disturbing the power supply while getting to that point where you can probe the bit. >Would you agree that if the difficulty/cost of extracting a KEY from this NV >memory exceed that of the battery/SRAM storage, then it could very well be >considered a superior mechanism? This is what I would like to explore. I SEROUSLY doubt the cost of extracting a key from any NV storage you could imagine would be easier than extracting it from sram cells, see above and lots of exercises by attackers on the subject. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 73860
Hi KingKang,
This is from an earlier post. It was for the Strtaix Board, but should
be applicable here.
http://groups.google.com/groups?q=subroto&start=10&hl=en&lr=&ie=UTF-8&group=comp.arch.fpga&selm=95776079.0405190931.66acf11b%40posting.google.com&rnum=13
Hope it helps.
- Subroto Datta
Altera Corp.
"kingkang" <305liuzg@163.net> wrote in message
news:cjh02b$2rof$1@mail.cn99.com...
> Hi
> I have the Cyclone 1C20 board from Altera.
> But when I finish downloading the program with JTAG mode,the board does
> not
> excecute my program,but exceute the program stored in the rom.
> What can I do to made the board excecute my program?
> thanks
>
>
>
Article: 73861Yes you are right about the 11 cycles. I don't get any output at all. Zero zolts.Article: 73862
Hal, They claim it never goes away. (Until they go out of business....) I'll post both, but I have received back that the long ones are useless to most folks as they can't cut and paste them back together sometimes for their browser of choice. Austin Hal Murray wrote: >>(by the way, http://tinyurl.com is a cool way to minimize the pain of >>long URLs) > > > Yes, but please include the full URL too. You never know when some > nice service might vanish. > > > >>http://tinyurl.com/7xemy > > > In this case, it's: > http://support.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=alpa_rosetta > >Article: 73863
Hal, The colder is gets, the less charge leaks off, and the more likely the bits are retained. A count to ten at room temp seems to be effective (without power), so I imagine it might stick around for hours at -40C, and perhaps days at 77K (liquid nitrogen). Still, working on it under liquid nitrogen is probably going to be a bit tough. And stripping off those metal layers to get to it, that is another problem while keeping power on it. Basically, all we have to do is offer a secure enough solution that the attacker moves on to a less secure objective (like the box with the poly fuses which the IEEE published photomicrograph and techniques for to see which ones are programmed or not). Austin Hal Murray wrote: >>I have even been told that reading out the state of our battery backed >>key memory can be done today. > > >>The reason why I do not believe the latter, is that they have to do it, >>while keeping the battery backed memory power ON. > > > Just because we don't know how to do it yet doesn't mean > that somebody else doesn't know how to do it. Or that it > can't be solved with enough money. > > On the other hand, if it's cheaper to use social engineering > or a rubber hose, then it's good enough. > > How long do your bits last if I just disconnect the battery? > (leakage vs capacitance) What if the chip is cold? > > > >>Don't bother to argue with me. It is the NSA, CIA, etc. you would have >>to convince. > > > Only if that's his market. Maybe what he is thinking about is good > enough for some high volume commercial applications. >Article: 73864
Guy, <ignore> Austin Guy wrote: > I thought I was being clear when I said not to assume I was affiliated with > Altera. So to be clear about it, I am not employed by Altera nor do I have > the ability to know whether they are considering or Analyzing NV memory for > use in their FPGAs. Unfortunately, when creating my original post, I did > not realize nor intend for the Altera email address to have been posted I > simply thought it was a log-in procedure, a GOOGLE NEWS GROUP limitation I > did not remember since it has been a long time since using Google to post > (rather than other more anonymous methods). This lead to my reason for > disclosure. > > > > As an FPGA industry veteran, I am however very interested in continued > market research and discussions, which I hope you will agree, can be > beneficial to all FPGA users to create and provide vendors feedback. > > > > AUSTIN- > > You have made assumptions in your postings/responses with respect to > security. I never mentioned the word government or any of their standards. > You have assumed once again. Shame on you again? - Just kidding. Anyway, > the link you provided to the xilinx website was informative > (http://tinyurl.com/496n2). > > > > A couple of comments: > > In one of my earlier posts, I did not include other options when mentioning > NV memories in SRAM fpgas, I should have included battery backed SRAM, Fuse > based methods for Key storage, distributed polygon approaches and likely > others. > > > > One of the most important points the Xilinx link makes which Austin > neglected in his assumption that Security is no less than 100%, is the > tradeoff of security with cost. While I did say that it was undetectable, I > did not say it was suitable for government applications (another > assumption). So, the implication in the original posting is that there > would be a very low cost NV solution that would be super costly to reverse > engineer (order(s) of magnitude more difficult that Flash or even Antifuse) > providing a significantly lower cost solution for those non-government > applications needing high security than the solutions that Altera or Xilinx > currently offer. > > > > A decent article talking about security from a practical perspective: > http://www.algotronix.com/content/security%20FPL%202001.pdf > > > > Also, now coming back to government, although I am not familiar with the > specific published requirements (I add that due diligence to my to-do list), > I do believe security has been moving target with rising requirements even > for government./? So, just as Austin says that there might be ways to > detect and capture the Volatile SRAM stored KEY thus enabling the cracking > of governement data stream there is a level of probability and cost function > involved that is the current governement requirement. I'll bet that this > requirement and cost function will continue rise in time. > > > > Austin - Why is it impossible to believe that a new NV memory technology can > actually exceed this probability / cost function of detecting the stored > volatile key? > > > > > > As for Paul's comparison to Max II - I really do not see very many parallels > to the bulk of the discusson in this thread regarding applications for the > NV on chip memory. Max II does have NV memory and can potentially integrate > an external solution. I am trying to emphasize that much of this thread is > beyond that - especially with respect to larger data storage and other NV > needs (like that of secure processor code). > > > > > > More discussion? > > Thanks. > > > > > > > > > > "Paul Leventis (at home)" <paulleventis-news@yahoo.ca> wrote in message > news:0LqdnVRXQ4PYyMbcRVn-vA@rogers.com... > >>>That's a disclosure ? >>>Q: Do you work for Altera, or are affiliated with Altera ? >> >>My guess is no, this Guy guy does not work for Altera. If he does, it's > > the > >>first I've heard of him and he is violating Altera posting protocol by not >>clearly stating his affiliation in each posting. His email address is > > also > >>not in the format of an altera address for someone with the name Guy, and >>besides it bounces. >> >> >>>Q: Are Altera considering/analysing NV memory in FPGA ? >> >>We have Non-Volitile memory in our MAX II CPLD family. A Flash block is >>used to store the device configuration program. We also expose 8 Kb of >>Flash memory for use by the user -- for example, to absorb functions >>normally stored in off-chip serial eproms, such as a device serial number. >> >>I cannot comment on whether or not we are considering it for future FPGA >>families, except to say I doubt we would conduct market research in a > > public > >>forum such as this. We typically talk to all of our big customers to get >>feedback on family plans, and this is done under NDA. >> >>Regards, >> >>Paul Leventis >>Altera Corp. >> >> > > > >Article: 73865
"Brannon King" <bking@starbridgesystems.com> writes: > That's a beautiful solution. I'm glad there are people in the world who can > see the obvious. > You're too kind :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 73866
ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0409300139.97e7e1d@posting.google.com>... > Hi, > > I have a PLL in my design. This PLL generates two clocks which are > used in my design. > Now I want to cut these clocks from the design and generate my own > clocks for simulation. > The testclocks 'l_sdram_clk' and 'l_sdram_clk_90' are going to run > when the PLL is locked so that I use the 'l_pll_locked' signal to > enable the generation of the clocks. > I try that by using GENERATE. But the simulation shows that > 'l_sdram_clk' and 'l_sdram_clk_90' remain undefined. > > How can I solve that problem ? > > I would appreciate your help. > > Rgds > André > > > Here's the code: > > architecture xy of zx is > > ... > signal l_pll_locked : std_logic; > -- This signal comes out of the PLL, it gets '1' in the simulation > > test_1: if (l_pll_locked='1') generate > process > begin > l_sdram_clk <= '1'; wait for 3.75 ns; > l_sdram_clk <= '0'; wait for 3.75 ns; > end process; > end generate; > im not sure why are you doing this this way, but what do you expect to happen when l_pll_locked equals 0 during simulation? (think about it, so that you can understand why it's failing even when it gets 1 assigned) do you expect the process to just "dissapear"?? because in that case you want a process to "appear" when l_pll_locked equals 1. im pretty sure that's not possible. try to RTFM before (or ask to your coworkers, it's a lot FASTER than usenet!) so that you learn and understand why and how, before doing hit-and-miss coding techniques if you dont want to read the LRM (which is somehow hard to read), get a nice book, P. Ashenden, etc. but hey! im no hardware hotshot either! hint: try to use gated clocks, im guessing while the pll is not locked it's clock output is 0... l_sdram_clk <= not l_sdram_clk when l_pll_locked = '1' else '0' or something like that, bye! > test_2: if (l_pll_locked='1') generate > process > begin > l_sdram_clk_90 <= '1'; wait for 1.875 ns; > l_sdram_clk_90 <= '0'; wait for 3.75 ns; > l_sdram_clk_90 <= '1'; wait for 1.875 ns; > end process; > end generate; > > ... > end architecture xy;Article: 73867
David Smith <Dsnew@yahoo.com> wrote: >Has anybody come across a company called Clearspeed Technology? X-Original-Trace: 30 Sep 2004 14:52:36 GMT, koo.clearspeed.com Apparently you have. Has anyone come across a stupid f**k trying to advertise his product by spamming fake questions on usenet? Apparently I have.Article: 73868
Thanks for the answer guys. Is there any other way (tool) to accomplish the readback? I've been trying using JTAG tools (a openwice project) which is nice and neat, but it does lack of documentation and is taking me too much time to program the subrutines for xilinx devices (JTAG tools doesn't support Virtex at the moment). Austin,I read the article, very nice. Actually I need this readback stuff because I'm trying to implement something similar, kind of an artificial SEU generator, a SEU simulator if you wish. Any suggestion would be great! Alonzo.Article: 73869
Just to make sure that I wasn't doing a silly mistake with the pin assignments, I ran this code below, which removes the feedback loop, and just feeds through a d input that is connected to a pushbutton. Works fine. There must be something wrong in the original code with either the syntax of the init statement or the initialization and start up after configuration of the Xilinx Spartan 3. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library UNISIM; use UNISIM.VComponents.all; entity srltest is port( clk : in std_ulogic; d : in std_logic; q : out std_ulogic ); end srltest; architecture Behavioral of srltest is component SRL16 -- synthesis translate_off generic ( INIT: bit_value:= X"1001"); -- synthesis translate_on port (Q : out STD_ULOGIC; A0 : in STD_ULOGIC; A1 : in STD_ULOGIC; A2 : in STD_ULOGIC; A3 : in STD_ULOGIC; CLK : in STD_ULOGIC; D : in STD_ULOGIC); end component; -- Component Attribute specification for SRL16 -- should be placed after architecture declaration but -- before the begin keyword -- Enter attributes in this section -- Component Instantiation for SRL16 should be placed -- in architecture after the begin keyword -- signal feedback : std_ulogic; begin SRL16_INSTANCE_NAME : SRL16 -- synthesis translate_off generic map( INIT => X"7878" ) -- synthesis translate_on port map (Q => q , A0 => '0', A1 => '1', A2 => '0', A3 => '1', CLK => clk, D => d ); -- q <= feedback; end Behavioral;Article: 73870
On Thu, 30 Sep 2004 07:40:55 -0700, Austin Lesea <austin@xilinx.com> wrote: >Hal, > >They claim it never goes away. (Until they go out of business....) > >I'll post both, but I have received back that the long ones are useless >to most folks as they can't cut and paste them back together sometimes >for their browser of choice. it maybe tedious but it is always possible to cut&paste into a text editor to fix it up and then paste the whole thing to the browser. i can't believe there are browser which prevent a whole url to be pasted to the link box.Article: 73871
>The synthesizer is turned off when the generics are processed. I'm just following the example in the library. I don't get why it says to turn synthesize off. When I take these -- statements out I get errors.Article: 73872
mk, It may be possible, but not all folks have the skill.....(believe it or not). Austin mk wrote: > On Thu, 30 Sep 2004 07:40:55 -0700, Austin Lesea <austin@xilinx.com> > wrote: > > >>Hal, >> >>They claim it never goes away. (Until they go out of business....) >> >>I'll post both, but I have received back that the long ones are useless >>to most folks as they can't cut and paste them back together sometimes >>for their browser of choice. > > > it maybe tedious but it is always possible to cut&paste into a text > editor to fix it up and then paste the whole thing to the browser. i > can't believe there are browser which prevent a whole url to be pasted > to the link box. >Article: 73873
Hi Austin Lesea wrote: > Just ramp on slower than that indicated in the data sheet, and > everything is fine. May sound like a stupid question to experts but I'm more a sw/fw guy : How do you make it ramp slower ? Is there any obvious trick ? Looking at my regulator datasheet, doesn't even specify ramp rate ... SylvainArticle: 73874
Hi, Yes, you can do this. You would need some thing that turns on quick, like a small CPLD? You'd be looking at the RST# line, for certain. If it's a 64-bit design, you need REQ64#. If it's a PCI-X design, you need several other signals, detailed in the PCI-X addendum. I will note that you'll then have two loads on a number of signals, which is a compliance violation. Eric Hal Murray wrote: > > >* PCI 32-bit design -- about 2^25 bus clock cycles > >* PCI 64-bit design -- about 100 ms > >* Any PCI-X design -- about 100 ms > > > >The reason a 32-bit PCI design has so much more > >time is that it does not need to be ready to see > >the busmode/buswidth broadcast which takes place > >at the rising edge of reset. > > Could I grab the mode/width info with a small amount of > external logic? (and pass it to the FPGA when its ready) > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.
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