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I/Q demodulation - a complex mixer using the sine and cosine to deliver the baseband without image - provides the single-sideband demodulation Jerry mentions. Decimation is a simple way of getting "processing gain" by taking a high digital frequency IF with a lower number of bits per sample and - through decimation - increasing the effective number of bits by filtering out the system and quantization noise from the original A/D that is mixed to outside the baseband. If you don't need the processing gain, subsampling can be used but realize that this effectively aliases the IF into several "folds" such that any spurious signals or thermal or quantization noise gets added to the desired IF. Your description of the image comes off a little peculiar in my perception suggesting you might not be getting your desired point across. If the IF is analog-filtered then subsampled, this aliased pseudo-IF can be I/Q mixed to provide the baseband; it can even *be* the baseband depending on the sampling rate. If the IF is analog-filtered then sampled by at least twice the IF, I/Q demodulation is still required to isolate the baseband from the *mixed* image of Fif+Fmix. The topology you're thinking about isn't clear. Are your questions answered by the interpretation I took? "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:HfYgc.173403$JO3.100798@attbi_s04... > When digitally mixing an IF down to baseband, one is left with a spectrum > that consists of the baseband (Fif - Fmix = 0Hz) and an image (Fif + Fmix). > If the IF is greater than the Nyquist freq, the image will wrap back into > the first Nyquist zone (0 to Fn). > > Normally the next step in demodulation is decimation, which consists of > lowpass filtering out the image (often with CICs) and then dropping some of > the resultant samples to get a lower sample rate. > > Is there a method by which an image-reject mixer could mix the IF down to > baseband while simultaneously cancelling the image? If so, it seems like > there would be no filtering required for decimation, which would consist > entirely of throwing samples out. Then it also seems that the mixer itself > could run at the slower decimated rate. > > Or is that all just another way of saying "undersampling"? > -Kevin > >Article: 68826
I'd forgotten about the decimation processing gain--that's a good reason to stay with a high sample rate and conventional decimation process. -Kevin "John_H" <johnhandwork@mail.com> wrote in message news:iaZgc.4$913.203@news-west.eli.net... > I/Q demodulation - a complex mixer using the sine and cosine to deliver the > baseband without image - provides the single-sideband demodulation Jerry > mentions. > > Decimation is a simple way of getting "processing gain" by taking a high > digital frequency IF with a lower number of bits per sample and - through > decimation - increasing the effective number of bits by filtering out the > system and quantization noise from the original A/D that is mixed to outside > the baseband. If you don't need the processing gain, subsampling can be > used but realize that this effectively aliases the IF into several "folds" > such that any spurious signals or thermal or quantization noise gets added > to the desired IF. > > Your description of the image comes off a little peculiar in my perception > suggesting you might not be getting your desired point across. If the IF is > analog-filtered then subsampled, this aliased pseudo-IF can be I/Q mixed to > provide the baseband; it can even *be* the baseband depending on the > sampling rate. If the IF is analog-filtered then sampled by at least twice > the IF, I/Q demodulation is still required to isolate the baseband from the > *mixed* image of Fif+Fmix. The topology you're thinking about isn't clear. > > Are your questions answered by the interpretation I took? > > > "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message > news:HfYgc.173403$JO3.100798@attbi_s04... > > When digitally mixing an IF down to baseband, one is left with a spectrum > > that consists of the baseband (Fif - Fmix = 0Hz) and an image (Fif + > Fmix). > > If the IF is greater than the Nyquist freq, the image will wrap back into > > the first Nyquist zone (0 to Fn). > > > > Normally the next step in demodulation is decimation, which consists of > > lowpass filtering out the image (often with CICs) and then dropping some > of > > the resultant samples to get a lower sample rate. > > > > Is there a method by which an image-reject mixer could mix the IF down to > > baseband while simultaneously cancelling the image? If so, it seems like > > > there would be no filtering required for decimation, which would consist > > entirely of throwing samples out. Then it also seems that the mixer > itself > > could run at the slower decimated rate. > > > > Or is that all just another way of saying "undersampling"? > > -Kevin > > > > > >Article: 68827
You need a filter in there (unless you are not downsampling and there is no
out-of-band signal), however you can play some optimization tricks with the
math to roll the mixer into the filter if the LO is a multiple of your input
sample rate. What you end up with is a polyphase filter that has the mixer
convolved with it so that you get both mixing and filtering. If you want to
run the mixer slower, that can be done by bandlimiting the signal before the
mix and subsampling.
Kevin Neilson wrote:
> When digitally mixing an IF down to baseband, one is left with a spectrum
> that consists of the baseband (Fif - Fmix = 0Hz) and an image (Fif + Fmix).
> If the IF is greater than the Nyquist freq, the image will wrap back into
> the first Nyquist zone (0 to Fn).
>
> Normally the next step in demodulation is decimation, which consists of
> lowpass filtering out the image (often with CICs) and then dropping some of
> the resultant samples to get a lower sample rate.
>
> Is there a method by which an image-reject mixer could mix the IF down to
> baseband while simultaneously cancelling the image? If so, it seems like
> there would be no filtering required for decimation, which would consist
> entirely of throwing samples out. Then it also seems that the mixer itself
> could run at the slower decimated rate.
>
> Or is that all just another way of saying "undersampling"?
> -Kevin
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68828"Peter Alfke" <peter@xilinx.com> wrote in message news:BCA9A92A.5F50%peter@xilinx.com... > Clock Enables vs multiple clocks is a trade-off. > If you are not concerned about power, then a single low0skew global clock > and a "sloppier" network of CEs requires the least amount of thinking. > Multiple derived clocks mean that you have to think about clock transfer > from one clock domain to the next, you may have to use multiple > PLL/DLL/DCMs. > Indeed, your customer/boss/well-being is almost always far better served by the 1) reduced time to market 2) improved design accuracy and stability 3) design portability 4) simplicity of having a single clock with CEs for the slower stuff. It's hard to imagine a situation where a multiple clock system would be worth the hassle. (Maybe the use of legacy stuff would be one reason?) IMO, Syms.Article: 68829
Probably, your hieararchy path in the BMM doesn't correctly reflect your submodule path. In submodule flow, platgen generates a system_stub.bmm instead of the system.bmm. The system_stub.bmm contains hierarchy path of the submodule in your system. In xps, selecting "Project Options" -> "Hierarchy & Flow", you can submodule flow plus add the instance name of the instantiate submodule in your schematic toplevel. This written to system_stub.bmm It's bitgen in the iSE flow, that writes out system_stub_bd.bm that contains the placement info of the blockrams. The system_stub_bd.bm by data2mem to initialize your bitstream. Morris Ho wrote: > Tools used: EDK and ISE 6.2 on Win2000. I compiled the Memec HelloWorld > project and successfully ran it on their Spartan IIELC reference design > board. > > With this working project, I changed its properties to a sub-module and > exported it to Project Navigator project that had a schematic top level > file. I created the library symbol for the sub-module, placed the > sub-module and an counter on the schematic and I ran it all the way to > Generate Programming File. When I downloaded the bit file, the counter > worked, but the Microblaze did not. Even going back to Platform Studio and > using the import function did not create a working bit file. > > I found by extensive poking around that the Project Navigator does NOT > automatically update the BMM file with the newly placed locations of BRAM > that holds the Microblaze program. (The export from XPS did add a > system.BMM, but that file did not have any placement info--the file just had > the names of the BRAM instances and the memory bit positions.) Data2Mem > needs the placement information to create a new download file. I found that > I could use the FPGA editor in Project Navigator to find out where the last > PAR operation put the BRAMs. I created a new BMM file from the system.BMM > and included the placement info. Specifying this BMM file with the .ELF > allowed Data2Mem to create a WORKING Microblaze sub-module bit file. You > can manually run Data2Mem in the Project Navigator or use the dialog in XPS > (which calls Data2Mem in the script) as long as you supply the correct BMM > file. > > A valid line in a BMM text file for Data2Mem is: > bram_1mb/bram_1mb/ramb4_s2_s2_0 [31:30] PLACED = R3C0; > > The BMM files exported to Project Navigator by XPS did not have the field > starting with "PLACED.." After going from PAR to bit file creation, the BMM > file still did not change, even though the subsequent Data2Mem procedure to > combine the ELF data requires placement info in the BMM. It is quite > reasonable not to supply any placement before PAR, because PAR is allowed to > move things around, but the final placement info should be extracted and > updated into the BMM file. In this example, I manually added the placement > information. > > I have seen a few posts regarding this problem. Is there a button or > procedure in Project Navigator to automatically extract new BRAM locations > and update the BMM file? Of course I already have a work-around, like > forgetting about sub-modules and keeping the project exclusively in XPS ! > > -- / 7\'7 Paulo Dutra (paulo.dutra@xilinx.com) \ \ ` Xilinx hotline@xilinx.com / / 2100 Logic Drive http://www.xilinx.com \_\/.\ San Jose, California 95124-3450 USAArticle: 68830
>4) simplicity >of having a single clock with CEs for the slower stuff. It's hard to imagine >a situation where a multiple clock system would be worth the hassle. (Maybe >the use of legacy stuff would be one reason?) How about battery operation where power consumption is critical? (It turns into battery life.) On the high speed/performance end, it might save a bit of heat. Going from X watts to X-2 might be critical. (Look at the games modern CPUs are doing to balance heat and performance.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68831
"Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message news:kc9780d765fn0lor7msd06dhnk033aqp7p@4ax.com... > You can make a simple > distributed PWM by using a first order delta-sigma modulator; > it's essentially the same trick as Bresenham's algorithm > for drawing angled lines on a raster display. Conceptually > the algorithm is: > * maintain a signed accumulator register A > * establish a PWM cycle length, N clock cycles > * have a "desired output" value V > * on each clock cycle, accumulate A = A + V, and then... > - if A is negative, supply 0 as the output > - if A is positive, supply 1 as the output and modify > the accumulator by forming A = A - N > Very interesting! I've a question. What's the algorithm for a second order delta-sigma modulator? N-order? Cheers, Syms.Article: 68832
On Mon, 19 Apr 2004 02:10:38 -0700, Hal Murray wrote: > Pulse width modulation is the classic way to do low speed D/A from > digital logic. For this purpose, I think I can do better by spreading > the on bits over the whole time slot rather than clumping them all at > the beginning. (Better low frequency noise.) For example, if I wanted > slightly lower than 1/3 of full scale, I would send 1 on pulse, and 2 or > 3 off pulses, adjusting the ratio of 2 and 3 off pulses to get the best > answer. What's the term for this approach? Is there a good writeup > someplace? One term is rate multiplier, another is interleaved PWM. Its easy to generate interleaved PWM by bit reversing the reference count before comparing it with the PWM value. You can even trade off transitions per cycle versus filter time constant by only bit reversing the desired number of bits of the reference count. The power on the FPGA tends to be noisy so I would add an external 74ACT04 or some such powered by a clean power supply for your actual PWM... Peter WallaceArticle: 68833
>The power on the FPGA tends to be noisy so I would add an external >74ACT04 or some such powered by a clean power supply for your actual >PWM... Thanks. That was on my list but I left it out because of clutter. The supply for that buffer also has to be well regulated. I suspect that's just the tip of the analog iceberg. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68834
>Is the limitation in the hardware or in the software? >Are you running out of PCI bus cycles or CPU cycles? > >Count the cycles on the PCI bus and do the arithmetic. >How many CPU cycles does it take to process each packet? There is another possibility I overlooked. There is probably a dedicated processor on the chip to process control blocks and such. You might run out of cycles in that CPU. The data sheet or marketing blurbs might have some info about how well the chip works, especially if it can keep up with full wire speed and small packets. You could also try to get a PCI card using that chip and plug it into a motherboard/system and see how fast you can make it go. This depends a lot on the driver and OS and your test programs. Of course, you need a place to stand while running the tests. It might be simplest to get two of the boards, setup two systems and send packets from one to the other. (This could be a big rathole.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 68835
javaguy11111@yahoo.com (db) wrote in message news:<903bda3b.0404181812.1b218f10@posting.google.com>... > Very cool. Why are you selling it? > Do you have any closeups of the Virtex. How did you route the pins > out? How is the BGA attached to board. Did you use reflow? > We need money, because we were "self-funded". The FGA chip was soldered with blue prototyping wires, that was attached to the FPGA pads directly. We didnt use reflow, as it would have been too expensive. Here is my website. Check it out for some of my projects, in particular, INES1M for the close back shots! JacquesArticle: 68836
Hi, Thanks for all the help. I wrote the constraints as you have described, but I am not able to meet the setup time requirement. The PCI design was done originaly for an ASIC and changing it will be a big project by itself. My setup time on some paths is 11-12ns. This is because of a lot of comb. logic in the data path between pin and register. Is it possible to add delays to the clock path only for the register which has the setup time violation? This would mean that I would be trading off freq. for setup time. Does Quartus do this for me through any optimization options? I did see a tsu-freq trade off but that is opposite of what I need. Thanks again for all the help. Regards Tushit vbetz@altera.com (Vaughn Betz) wrote in message news:<48761f7f.0404160830.662dc9d8@posting.google.com>... > Hi Tushit, > > As Subroto said, the best thing to do is to study Altera's PCI core to > get all the constraints right. > > Here's a quick summary of the constraints for 33 MHz PCI: > > - 7 ns Tsu constraint on all inputs > - 11 ns Tco constraint on the outputs > - 33 MHz constraint on the PCI clock > - 0 ns Th constraint on the inputs > > Don't forget the Th (hold-time) constraint, since the PCI spec needs > it. > > The Tsu and Tco constraints can instead be converted to clock path > constraints with the INPUT_MAX_DELAY constraint as David said, but it > would be easier to just set them as Tsu and Tco since then you don't > have to work on precisely what INPUT_MAX_DELAY you have to set. > > Vaughn > > tushitjain@yahoo.com (tushit) wrote in message news:<ec6aab0.0404130920.42fa2dfd@posting.google.com>... > > Hi, > > I am fairly new to FPGAs. I am trying to write the constraints for the > > PCI module on an Altera Stratix device. I am using QuartusII for all > > synthesis and P&R. > > The PCI spec says I need to ensure a setup time of 7ns for all pins. > > The PCI clock itself works at 33Mhz. I want to know the following: > > 1) Is it okay if I just constraint the PCI clk of my design to 50Mhz > > (30ns for the 33Mhz clock and another 10ns to ensures that the setup > > time is met)? I realise this will be an overkill on the internal logic > > but may save me some effort. > > 2) The other way I think to do this is to constraint the PCI clk to > > 33MHz and specify the external delay on all the PCI signals to 7 or > > 8ns. While setting PCI clk to 33Mhz I also ticked the option of > > including external delays in the frequency calculation. Is this the > > correct approach? OR do I need to setup the tco. > > Thanks in advance. > > Regards > > TushitArticle: 68837
Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<p68780ta5piddrjllu6s8mkscf04jqe49j@4ax.com>... > On 19 Apr 2004 02:19:04 -0700, kanglc@starhub.net.sg (owner) wrote: > > >Hi, > > > >This is somewhat OT, but I can't find a more suitable newsgroup. > > > >I am using a Gigabit Ethernet MAC chip from Marv***, which claims full > >line rate (compliance to IEEE 802.3ab). It has an integrated GMAC, > >PHY/Serdes, and PCI interface (64-bit, 66MHz). On the PCI bus side, we > >connect it to a Spartan IIe-300 with a Xilinx PCI Logicore. > > > >Everything works in the FPGA, PCI read/write transactions, but we > >cannot achieve full line rate for 64-byte frame length. We can only > >achieve 680Mbps because of the overhead in reading/writing > >descriptors. > > > >My questions are: Is this expected? Is this acceptable? I have no > >prior experience with Gigabit Ethernet MAC, and appreciates any > >feedback. > > I've seen Marv*** GbE PHYs work at 100% of line rate, in one of these: > http://advanced.comms.agilent.com/RouterTester/datasheets/e7918a.htm > Never used one of their MACs though. Thanks for your reply. Yes I am aware of the Marv*** PHY used in Agilent equipment. Our project is similar - a handheld test instrument. > Umm, > 64 bytes frame > + 8 bytes preamble and SFD > + 12 bytes minimum interframe gap > = 84 bytes on the line => 1.4881 Mpps, which corresponds to 761.9Mbps > of useful data transfer. > > You seem to be achieving about 89% of this. This wouldn't be > acceptable for test equipment, but may be ok for your application > (which you didn't specify). > > Regards, > Allan. On the PCI bus (64-bit, 66MHz), it shows that for every frame that was fetch by the MAC, it has to read one descriptor and then write one descritor, to release the ownership. From the datasheet, we cannot find ways to burst the frames, in order to decrease the overhead due to the handling of descriptors. Or is there? Regards, LCArticle: 68838
Hi, I am new to configurating multiple devices through JTAG. Does anyone know if it is possible to configure multiple devices (Xilinx Spartan FPGA and CPLD) in a daisy chain through JTAG. The problem I face is that the the devices concerned have different Vcc(s). The former is 5V and the latter is a 3.3V device. Is it only possible to configure them separately through JTAG. Thank you.Article: 68839
On 20 Apr 2004 00:21:17 -0700, kanglc@starhub.net.sg (owner) wrote: >Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<p68780ta5piddrjllu6s8mkscf04jqe49j@4ax.com>... >> On 19 Apr 2004 02:19:04 -0700, kanglc@starhub.net.sg (owner) wrote: [snip] A GbE MAC is reasonably simple. I expect that you could make your own in an FPGA, and this could be cheaper and smaller than a solution involving both an FPGA and an ASIC. This way you could control all aspects of the MAC, including where its descriptors are held (possibly in a very fast local memory). You would still need an ASIC for the PHY though. Regards, Allan.Article: 68840
oh, yah, it's true. i only want to learn but i don't want to pay for a book either but i want my own copy of either a book or a spec... i am sure there will be a softcopy somewhere in some professor's computer account from some university...only that somebody has yet to browse his directory...:P Happy searching for free stuff online... kelvin Petter Gustad <newsmailcomp5@gustad.com> wrote in message news:m3zn98o2bg.fsf@scimul.dolphinics.no... > "Kelvin" <kelvin8157@hotmail.com> writes: > > > well...i will search it again and again until i can find one...dun think > > i can afford that kind of price... > > If you just want to learn about PCI Express you can buy a book, .e.g. > the earlier mentioned mindspring book, or "The Complete PCI Express > Reference" from Intel Press. If you are about to implement PCI Express > you can not affort to not get the spec... > > Petter > > -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?Article: 68841
here is my website. http://www.ece.concordia.ca/~jl_athow/elec.htmArticle: 68842
Hi I synthesised my verilog code in synplify. And do the P&R in quartusII. When I did not config some of the pins FPGA ran correctly.But when I config these pins,it went wrong result! I can believe the pins did not affect the internal function! The board freq meet the timing report of quartusII. I don't know why. The fpga is Altera 20k200e Thanks and RegardsArticle: 68843
Hi,
I have a FF in my design whose reset and set are separate conditions:
process( rst, clk )
begin
if ( rst = '1' ) then
output <= '0';
elsif ( clk'event and clk = '1' ) then
if ( set = '1' ) then
output <= '1';
end if;
if ( reset = '1' ) then
output <= '0';
end if;
end if;
end process;
This works fine but now I want the reset condition to be a rising edge
detector signal, so:
process( rst, clk )
begin
if ( rst = '1' );
aux <= '0';
if ( clk'event and clk = '1' ) then
aux <= input;
end if;
end process;
reset <= not(aux) and input;
The "input" signal is synchronous to my design and periodical but its
period is about 16 times the clock period. When I execute the
functional simulationwith ModelSim SE 5.6f, the "reset" signal appears
as a glitch since the "input" and "aux" signals change their values in
the same clock edge.
Because of this, the "output" signal is never reseted.
I believe that the timing simulation may vary and the design could
work correctly because of the "clock to output" of the FFs, but I'n
not sure.
Any suggestions?
Thanks in advance,
Arkaitz.
---------------------------
Electronics Area
IKERLAN
Pš J. M. Arizmendiarrieta, 2
20500 Arrasate (Gipuzkoa)
---------------------------
Article: 68844A good help is on the xilinx site. xilinx.com --> Support --> Problem Solvers --> JTAG Problem Solvers From there, look for relevant info. johnong99@hotmail.com (john ong) wrote in message news:<a11135b4.0404192350.107f4a14@posting.google.com>... > Hi, > I am new to configurating multiple devices through JTAG. Does anyone > know if it is possible to configure multiple devices (Xilinx Spartan > FPGA and CPLD) in a daisy chain through JTAG. The problem I face is > that the the devices concerned have different Vcc(s). The former is 5V > and the latter is a 3.3V device. Is it only possible to configure them > separately through JTAG. Thank you.Article: 68845
Hi, there: I went for an interview with a R&D center of an american company. One week after the interview the interviewer sent me a letter asking me to sign a paper for background check..What does that mean? AFAIK this is not customery in my country...Under what circumstance do they ask for background check? How do I know whether they abuse my rights? What kind of information may they check and what not? Is it compulsory for an american co to perform this check? Best Regards, LeoArticle: 68846
Hi, what's better for a reliable and compact (fpga!)-design: - To compose the design structure in state machines as much as possible? or - To make strong use of small single components (e.g. FFs, counters, etc.), for which there can be implemented as library-elements or as behavioural parts. Any preferences? For my own part I admire a structural implemented design with some FSMs in some special situations (e.g. flow control or like that). But from another point of view, state machines have much of advantages because of their strong deterministic behaviour. What's your opinion concerning this case? Is there existing a application dependent guide of "good" design? Regards, Thomas.Article: 68847
I have a DSP development kit, Stratix Edition. I obtained a license for the development kit, using the link: https://mysupport.altera.com/lic/devKitNic.asp?product=stratix I received the license, installed it per the instructions. Quartus II seems to work OK but when I try to run the Filtering Reference Design Lab, exercise 3, and run the Signal Compiler 2.1.3, I get the error message "! Unable to check a valid DSP Builder License". I was under the impression from the Altera Licensing web link that the DSB Builder License was included as a feature of the licensing file. I've contacted Altera but so far no response. Does anyone have any experience with this problem? Thanks a million. JonArticle: 68848
Hello, I'm new for VHDL and I need help. I've got NuHorizons CoolRunnerII board and I'm using ISE version 6.2. Can you give documents If you have or Can you recommend any book (I hope I can find it)? I have dowloaded any documents from Xilinx web site, but something is not clear for me. thanks usrdr@yahoo.co.ukArticle: 68849
The simplest form of background check is to verify your education background ( did you get that PhD at xyt university in 1999?) and also your employment times (did you work there from x to y?). Deeper probing is unusual and might be illegal. There are strict rules in the US: The future employer may NOT ask about race, ethnicity, religion, sexual orientation, and not even for your age and gender (!). Now, if the job requires a government security clearance, that's a different matter... Peter Alfke =========================== > From: "Andrew Leo" <asdf@aef.com> > Organization: Singapore Telecommunications Ltd > Newsgroups: comp.arch.fpga > Date: Tue, 20 Apr 2004 21:08:54 +0800 > Subject: What does a "background check" mean? ... > > Hi, there: > > I went for an interview with a R&D center of an american company. > One week after the interview the interviewer sent me a letter asking me > to sign a paper for background check..What does that mean? AFAIK > this is not customery in my country...Under what circumstance do they > ask for background check? How do I know whether they abuse my > rights? What kind of information may they check and what not? Is it > compulsory for an american co to perform this check? > > Best Regards, > Leo > > >
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