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"Dwayne Surdu-Miller" <miller@SEDsystems.nospam.ca> wrote in message news:108iv4e3fah94df@corp.supernews.com... > I will slip in an 'oops' and a 'thanks' here. The input jitter > generality is clearly wrong and contentious. > > This issue brings up an application issue that has come up a number of > times for me. I've set up a number of clock dividers using various > techniques like clock-puncturing and > numerator-accumulation/denominator-thresholding, but of course the > output clock jitter varies directly with the input clock width. > > What kind of thing could accept an extremely jittery clock output like > that described above, and produce a nice clean clock with the same > average frequency and substantially reduced jitter? > > Best regards, > Dwayne Surdu-Miller > > I came across an interesting DLL that does just this. Rather than delay the input jittery clock, it uses its own oscillator which should be plesiochronous (close in frequency) to the input clock, and relatively free of jitter. Phases of this clean clock 60 degrees apart are generated, and control logic selects and interpolates different phases together to create an output clock that is of the same frequency, and synchronous with the input clock. I can dig up a link to the paper if your interested. Cheers, Michael.Article: 69026
While EZUSB itself isn't flash-based, you can add a serial EEPROM for about $0.50 which provides this capability. "RM" <mainr@_spamjam_bigfoot.com> wrote in message news:<P8-dnWASwLiTjBHdRVn-vA@edaptivity.com>... > - Program should be flash-based. EZUSB requires initial program load via USB > whenever the device is re-attached to the USB host. I wish to program device > functionality once, and this program should be retained when the device is > detached from USB. > > Thanks, > R. Main.Article: 69027
Josh Graham wrote:
> Hello all,
> I am trying to get XST (ISE 6.1) to infer a dynamic shift register
> implemented using Virtex II LUTS. I have used the VHDL model shown
> below.
> However XST does not use LUTS, instead flip-flops are used. When I
> change the line srout <= sr(n) where n is a static value XST manages
> to use LUTS for the shift register. Can anybody please tell me what I
> am doing wrong. This is the same code as given in XST Synthesis ans
> Verification guide.
Howdy Josh,
Does the guide say that it will use only LUTs for an addressable (or
dynamic) shift register? My understanding and experience is that it
will take all consecutive and more importantly, unused bits, and roll
them into a LUT based SRL (assuming it doesn't have a reset). I'm
pretty certain that it is configured during synthesis/map/P&R and can't
be addressable or dynamic.
Ray Andraka uses these a lot, so I'll bet he has an efficient way to do
what you want (although I would plan on it being larger than your
originally thought).
Good luck,
Marc
Article: 69028On Mon, 26 Apr 2004 10:51:41 +1000, "Michael Chan" <mchan@itee.uq.edu.au> wrote: > >"Dwayne Surdu-Miller" <miller@SEDsystems.nospam.ca> wrote in message >news:108iv4e3fah94df@corp.supernews.com... >> I will slip in an 'oops' and a 'thanks' here. The input jitter >> generality is clearly wrong and contentious. >> >> This issue brings up an application issue that has come up a number of >> times for me. I've set up a number of clock dividers using various >> techniques like clock-puncturing and >> numerator-accumulation/denominator-thresholding, but of course the >> output clock jitter varies directly with the input clock width. >> >> What kind of thing could accept an extremely jittery clock output like >> that described above, and produce a nice clean clock with the same >> average frequency and substantially reduced jitter? >> >> Best regards, >> Dwayne Surdu-Miller >> >> >I came across an interesting DLL that does just this. Rather than delay the >input jittery clock, it uses its own oscillator which should be >plesiochronous (close in frequency) to the input clock, and relatively free >of jitter. Phases of this clean clock 60 degrees apart are generated, and >control logic selects and interpolates different phases together to create >an output clock that is of the same frequency, and synchronous with the >input clock. I can dig up a link to the paper if your interested. I've seen CDR devices that do this, although I think the phases may have been less than 60 degrees apart. I could probably dig up part numbers if anyone is interested. Regards, Allan.Article: 69029
RM wrote: > > I'm looking a microcontroller with the following properties: > - Includes a USB port interface, which is used for programming all functions > (ideal case). Alternatively, initial function programming could be via JTAG, > but once programmed the device must support USB. > - Program should be flash-based. EZUSB requires initial program load via USB > whenever the device is re-attached to the USB host. I wish to program device > functionality once, and this program should be retained when the device is > detached from USB. > - CPLD (or FPGA with non-volatile program storage / autoload (autoload could > be performed by microcontroller)) to support reconfigurable hardware > functions. > > Anyone know of such a device? The only MCU I have seen that includes any sort of PLD is the new Analog devices ARM7 parts. I don't know if they have a USB version, but I belive they have some 8 or more pins that can be driven by a PLD. Other than that, you would be looking at one of the FPGA/MCU combined devices like the Atmel SLIC or the Tricend devices at a *MUCH* higher price point and I don't think either of them are USB capable. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 69030
RM wrote: > I'm looking a microcontroller with the following properties: > - Includes a USB port interface, which is used for programming all functions > (ideal case). Alternatively, initial function programming could be via JTAG, > but once programmed the device must support USB. > - Program should be flash-based. EZUSB requires initial program load via USB > whenever the device is re-attached to the USB host. I wish to program device > functionality once, and this program should be retained when the device is > detached from USB. > - CPLD (or FPGA with non-volatile program storage / autoload (autoload could > be performed by microcontroller)) to support reconfigurable hardware > functions. > > Anyone know of such a device? The uPSD devices from STm come close - they have CPLDs, currently 16 macrocells, and I think a 32 MC one is comming. The new ARM7s from ADI also have a simple Prog.logic fabric, but that is not a full CPLD but is interfaced via some IO mapping registers. I think their target use is very simple logic, like Quadrature and PWM deadband, and fast protection etc. Looks a good idea. -jgArticle: 69031
Hello,
i am using a FSM in my CPLD design (XC95108). It is written in ABL. It is
working fine so far, beside some curious behaviour. On some special
condition it seems, my FSM stops working. Something like the token gets lost
??? I have seen it when a lot of "traffic" is on a lot of lines, sometimes
already at start up (i still have the xilinx boot adapter connected all the
time, when i then do a verify of my written program it is running again,
verify succeeded of course). I have not used any global inputs (they are
N.C.), for the state machine i have a initial state inside my abel sources.
I jump everytime from one state to another, can't see any state which gets
lost.
Can you give me a tip for this how to solve it ? Can i use something like a
"default" case to come back even i such a case ? I read that one hot state
machines are not the best things for CPLD. When i convert it, will it solve
my problem ? Is there an easy way of converting it ?
Regards,
Martin
Article: 69032Need to reload my system to fix some corruption, and didn't archive the service packs ... and it appears Xilinx took them off the web/ftp sites. So if you have them archives somewhere ... HELP!!! Thanks in advance, JohnArticle: 69033
Hi, I was talking to an "expert" in synthesis and he mentioned that there is a lot of difference between a synthesizable RTL code for a FPGA and a synthesizable RTL code for an ASIC. Is this true? If so, could you please point the significant differences between the two and what causes these differences. Thanks, AnandArticle: 69034
John L. Bass schrieb: > Need to reload my system to fix some corruption, and didn't archive the > service packs ... and it appears Xilinx took them off the web/ftp sites. > > So if you have them archives somewhere ... HELP!!! > > Thanks in advance, > John > Look at: http://www.xilinx.com/webpack/classics/wpclassic/index.htm Register required.Article: 69035
Martin Maurer wrote: > Hello, > > i am using a FSM in my CPLD design (XC95108). It is written in ABL. It is > working fine so far, beside some curious behaviour. On some special > condition it seems, my FSM stops working. Something like the token gets lost > ??? I have seen it when a lot of "traffic" is on a lot of lines, sometimes > already at start up (i still have the xilinx boot adapter connected all the > time, when i then do a verify of my written program it is running again, > verify succeeded of course). I have not used any global inputs (they are > N.C.), for the state machine i have a initial state inside my abel sources. > I jump everytime from one state to another, can't see any state which gets > lost. > > Can you give me a tip for this how to solve it ? Can i use something like a > "default" case to come back even i such a case ? I read that one hot state > machines are not the best things for CPLD. When i convert it, will it solve > my problem ? Is there an easy way of converting it ? Look in the .RPT file, to see the state-nodes, and the conditions for a next-state. If a One-Hot ends up with zero, or >=two bits hi, it may or may not recover. If you have a spare pin, decode those options to it, and verify if that is your failure mode. Causes can be aperture effects, where an external signal is not stable on the clock edge. Look carefully at async signals that cause state changes. recovering from all Zero is simple enough, and could be already done in your code. -jgArticle: 69036
"Leon Heller" <leon_heller@hotmail.com> wrote in message news:408c2ecd$0$19422$cc9e4d1f@news-text.dial.pipex.com... > I just came across this schematic for the ByteBlaster II: > > http://www.mcu.cz/atm/index.php?direction=0&order=&directory=EDA > > Someone has probably worked out the circuit by tracing the connections on a > unit as Altera hasn't published it, AFAIK. You need to register to be able to download the above file. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 69037
In article , mchan wrote: > I came across an interesting DLL that does just this. Rather than delay the > input jittery clock, it uses its own oscillator which should be > plesiochronous (close in frequency) to the input clock, and relatively free > of jitter. Phases of this clean clock 60 degrees apart are generated, and > control logic selects and interpolates different phases together to create > an output clock that is of the same frequency, and synchronous with the > input clock. I can dig up a link to the paper if your interested. Hi! Yes, I'd be interested, could you dig that paper up? Jay.Article: 69038
I doubt, since the driver is specific to the part. This ByteblasterMV is done in an evening with selfetching. Rene Steve Casselman wrote: > If you are doing jtag can't you use the xilinx cable design. > > > Steve > > "Rene Tschaggelar" <none@none.net> wrote in message > news:408c21a8$0$708$5402220f@news.sunrise.ch... > >>Mike Treseler wrote: >> >> >>>Florian Student wrote >>> >>> >>>>www.altera.com/literature/ds/dsbyte.pdf only gives a file not found > > error. > >>> >>>see page 4 of >>>http://www.altera.com/literature/ds/dsbytemv.pdf >> >> >>The only change to the MV is the replaacement of the LS244 with a HC244 >>to make it work also at 3.3V.Article: 69039
Leon Heller wrote: > I just came across this schematic for the ByteBlaster II: > > http://www.mcu.cz/atm/index.php?direction=0&order=&directory=EDA > > Someone has probably worked out the circuit by tracing the connections on a > unit as Altera hasn't published it, AFAIK. And does it work ? Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 69040
Thanks for all the replys guys, I should have stipulated that the frequency has got to be adjustable on the fly. > LTC6900, LTC6903 from linear technology This looks like my best bet, apart from.... > > Can be sourced from distributor in a couple of days. I can get them from the LTC web site, does anyone have any experience of their delivery times? Thanks again for all suggestions, NialArticle: 69041
Hi, You are right, the trdy,irdy, cben, framen are the problem areas. I am using quartus to do the synthesis and P&R. I looked at the timing analysis report and the report for delay in data path looks like this: I have edited slightly to make it readable... ------------------------------------------------------------------ Info: 1: + IC(0.000 ns) + CELL(0.976 ns) = 0.976 ns; Loc. = Pin_AT6; PIN Node = 'cben[3]' Info: 2: + IC(2.595 ns) + CELL(0.213 ns) = 3.784 ns; Loc. = LC_X92_Y16_N1; COMB Node = ' Info: 3: + IC(0.364 ns) + CELL(0.213 ns) = 4.361 ns; Loc. = LC_X92_Y16_N3; COMB Node = ' Info: 4: + IC(0.139 ns) + CELL(0.087 ns) = 4.587 ns; Loc. = LC_X92_Y16_N4; COMB Node = ' Info: 5: + IC(0.351 ns) + CELL(0.087 ns) = 5.025 ns; Loc. = LC_X92_Y16_N9; COMB Node = ' Info: 6: + IC(1.121 ns) + CELL(0.332 ns) = 6.478 ns; Loc. = LC_X91_Y19_N8; COMB Node = ' Info: 7: + IC(0.139 ns) + CELL(0.087 ns) = 6.704 ns; Loc. = LC_X91_Y19_N9; COMB Node = ' Info: 8: + IC(0.352 ns) + CELL(0.087 ns) = 7.143 ns; Loc. = LC_X91_Y19_N3; COMB Node = ' Info: 9: + IC(2.143 ns) + CELL(0.213 ns) = 9.499 ns; Loc. = LC_X82_Y31_N6; COMB Node = ' Info: 10: + IC(0.340 ns) + CELL(0.087 ns) = 9.926 ns; Loc. = LC_X82_Y31_N9; COMB Node =' Info: 11: + IC(1.658 ns) + CELL(0.087 ns) = 11.671 ns; Loc. = LC_X88_Y27_N8; COMB Node = ' Info: 12: + IC(1.527 ns) + CELL(0.087 ns) = 13.285 ns; Loc. = LC_X82_Y31_N2; COMB Node = ' Info: 13: + IC(1.641 ns) + CELL(0.087 ns) = 15.013 ns; Loc. = LC_X81_Y26_N0; COMB Node = ' Info: 14: + IC(0.139 ns) + CELL(0.087 ns) = 15.239 ns; Loc. = LC_X81_Y26_N1; COMB Node = ' Info: 15: + IC(0.593 ns) + CELL(0.087 ns) = 15.919 ns; Loc. = LC_X82_Y26_N5; COMB Node = ' Info: 16: + IC(0.366 ns) + CELL(0.213 ns) = 16.498 ns; Loc. = LC_X82_Y26_N1; COMB Node = ' Info: 17: + IC(0.918 ns) + CELL(0.364 ns) = 17.780 ns; Loc. = LC_X85_Y26_N2; REG Node = ' Info: Total cell delay = 3.394 ns Info: Total interconnect delay = 14.386 ns --------------------------------------------------------------------------- The delay in clock path is about 4ns and this gives a tsu of 13 ns or so. It is going through a lot of combo nodes (I think 17!!). Will it help to do a manual fitting. To check if the routing delays could be reduced I cleaned up my device and did a syn and P&R only with the PCI module. I assume this will give a better P&R fit but I still got a similar slack for tsu. My device util. with the full design in 75% of a stratix EP1S80 C6 grade. With only PCI this goes down to ~20%. I also tried the physical synthesis of combo logic option but this didn't help. Someone suggested reducing the fanout of the signals by duplicating them, but I assume Quartus must be doing that for me. I know xilinx has a "max fanout" setting, though I couldn't find it in quartus. If I need to do this manually how will I do this? If all else fails I will have to look into redesigning the combo logic manually. Thanks and regards Tushit > > Hi Tushit, > > It sounds like you have too many levels of logic on your set-up path. > That is definitely the most difficult set of paths in PCI. > > Quartus does not have an option to automatically delay the clock to a > register. There are (tricky) ways to do it by hand, but I wouldn't > recommend going down that route. > > Which device and speed grade are you using? Which synthesis tool? > Knowing what you're using will help me give more focused answers. > > Altera's PCI cores have 2 or 3 levels of logic on the Tsu critical > paths. The most critical paths are those involving trdy and irdy in > most cases, since those high-fanout signals are harder to localize. > So the most important thing to meeting PCI timing is to get a small > number of levels of logic on those paths. If you are using Quartus > Integrated Synthesis and finding it is not doing a good job on that > path, you can put lcell buffers in your HDL to tell the mapper where > you want the lcell boundaries. In most circuits this isn't necessary, > but PCI is a case where synthesis can fall short. > > Another, simpler option, is to turn on physical synthesis and see if > it improves your results. Physical synthesis knows what the placement > is, so it can make better informed decisions about what should be a > logic cell than the front-end synthesis. > > The good news is that if you get the levels of logic down to a > reasonable level, the fitter should do the rest automatically for you, > so long as you're using Quartus II 4.0 or later. We meet 66 MHz, > 64-bit PCI with no place & route constraints in Stratix, so 33 MHz is > easy for the fitter. > > Hope this helps. Let me know how it turns out! > > Vaughn > AlteraArticle: 69042
rickman wrote: > user@domain.invalid wrote: > >>Steven wrote: >> >>>Hi, newgrouper, >>> >>>does anyone know what dqm does ? The specification of micron is >>>vague. What mask function does it mean ? >>> >>>Thanks >>> >>>Steven. >> >>Hi >> >>My interpretation is that the mask means that you can choose to not overwrite parts of existing data when you do a write to a certain address. >> >>A little example: >>If you have a data width of 64 bits and have 8 bits of dqm:s, and have a data architecture that use byte-variables. >>Then you can store 8 variables on one address and change one without destroy the others by using dqm as byte-enable. >> >>If I'm wrong I'm sure someone will correct me. > > > That is part of it. In essence the DQM is a byte enable. On write it > will allow or prevent the write on a byte by byte basis. On read, IIRC, > it will enable the data output or tristate the output on byte by byte > basis. > I checked a datasheet picked at random from Micron (MT16VDDT3264A) and there it says that DM (the name for dqm in the data sheet) only affects the write operation. I have not checked to many other datasheets, my feeling is that this is the standard way. It makes full sense to only use dqm at a write to not corrupt data at a address you do not want to alter. This is not a problem when you read, it is up to the receiver of the sdram-data to do the masking. I guess e.g commercial DSPs with SDRAM-interface have support for this but it is hidden by programmer with some abstraction levels. If you implement it in a FPGA you must take care of it yourself. As in my previous post, I have not much experience of constructing SDRAM-interfaces so please correct me if I'm wrong. /PfnaArticle: 69043
"Rene Tschaggelar" <none@none.net> wrote in message news:408cd362$0$703$5402220f@news.sunrise.ch... > Leon Heller wrote: > > > I just came across this schematic for the ByteBlaster II: > > > > http://www.mcu.cz/atm/index.php?direction=0&order=&directory=EDA > > > > Someone has probably worked out the circuit by tracing the connections on a > > unit as Altera hasn't published it, AFAIK. > > And does it work ? I mean to try it, when I get my Cyclone board finished. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 69044
"Leon Heller" <leon_heller@hotmail.com> wrote in message news:408cffe8$0$19420$cc9e4d1f@news-text.dial.pipex.com... > "Rene Tschaggelar" <none@none.net> wrote in message > news:408cd362$0$703$5402220f@news.sunrise.ch... > > Leon Heller wrote: > > > > > I just came across this schematic for the ByteBlaster II: > > > > > > http://www.mcu.cz/atm/index.php?direction=0&order=&directory=EDA > > > > > > Someone has probably worked out the circuit by tracing the connections > on a > > > unit as Altera hasn't published it, AFAIK. > > > > And does it work ? It looks about right if SOT-23's were used for all the diodes and transistors. NialArticle: 69045
> > My interpretation is that the mask means that you can choose to not overwrite parts of existing data when you do a write to a certain address. > > > > A little example: > > If you have a data width of 64 bits and have 8 bits of dqm:s, and have a data architecture that use byte-variables. > > Then you can store 8 variables on one address and change one without destroy the others by using dqm as byte-enable. > > > > If I'm wrong I'm sure someone will correct me. > > That is part of it. In essence the DQM is a byte enable. On write it > will allow or prevent the write on a byte by byte basis. On read, IIRC, > it will enable the data output or tristate the output on byte by byte > basis. > what does enable mean here ? In Write, DQM is high when it receives data? I have simulated testbench from micron, the DQM doesnot change. Thanks StevenArticle: 69046
I use instantiation inside a generate for the dynamic shift registers.
I've found that inference is too dependent on the particular synthesis
tool, and even the version of the tool. Much less hassle to jus tinfer the
structure you want, except of course if it is retargeted to a device family
that doesn't have SRL16's. I built mine as a separate component
parameterized for width, placement and a few other things so that I could
easily reuse it in other designs.
Marc Randolph wrote:
> Josh Graham wrote:
>
> > Hello all,
> > I am trying to get XST (ISE 6.1) to infer a dynamic shift register
> > implemented using Virtex II LUTS. I have used the VHDL model shown
> > below.
> > However XST does not use LUTS, instead flip-flops are used. When I
> > change the line srout <= sr(n) where n is a static value XST manages
> > to use LUTS for the shift register. Can anybody please tell me what I
> > am doing wrong. This is the same code as given in XST Synthesis ans
> > Verification guide.
>
> Howdy Josh,
>
> Does the guide say that it will use only LUTs for an addressable (or
> dynamic) shift register? My understanding and experience is that it
> will take all consecutive and more importantly, unused bits, and roll
> them into a LUT based SRL (assuming it doesn't have a reset). I'm
> pretty certain that it is configured during synthesis/map/P&R and can't
> be addressable or dynamic.
>
> Ray Andraka uses these a lot, so I'll bet he has an efficient way to do
> what you want (although I would plan on it being larger than your
> originally thought).
>
> Good luck,
>
> Marc
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 69047On Mon, 26 Apr 2004 11:34:31 +0530, Anand P Paralkar wrote: > Hi, > > I was talking to an "expert" in synthesis and he mentioned that there is > > a lot of difference between a synthesizable RTL code for a FPGA and a > synthesizable RTL code for an ASIC. > > Is this true? > > If so, could you please point the significant differences between the > two and what causes these differences. > > Thanks, > Anand The differences is in the choices you make. In FPGAs state is cheap and logic is expensive, in ASICs logic is cheap and state is expensive. To be more specific, FPGAs LUTs (the FPGAs logic element) are relatively slow and not very plentiful. FFs are very plentifull (relative to the available LUTs). RAM is very very plentiful, each LUT is typically worth 2-5 ASIC gates as logic but as a 16 bit RAM it's equivalent to 50-100 gates. There is also lots of RAM in the form of block RAMS. Shift registers are nearly free if you use the LUT RAM based shift register. Interconnect is very slow relative to an ASIC. ASICs Logic gates are almost free. They are very fast relative to an FPGA so you can do much more in a cycle (unless you are running at GHz clock rates). FFs are more expensive. Each FF is 6 gates (I might be wrong about the exact gate counts here, it's been a while since I've had to think in these terms, but the orders of magnitude are correct). RAM is much more expensive. A 16 bit RAM requires 16 latches and the associated decoding and multiplexing logic. Block RAM type structures layout efficiently but they still require a lot of area, in an FPGA they are already there so you might as well use them, in an ASIC you would think about how much RAM you absolutely need and you probably wouldn't waste in on things like look up tables unless that was absolutely the best way to do the function.Article: 69048
Steven wrote: >>>My interpretation is that the mask means that you can choose to not overwrite parts of existing data when you do a write to a certain address. >>> >>>A little example: >>>If you have a data width of 64 bits and have 8 bits of dqm:s, and have a data architecture that use byte-variables. >>>Then you can store 8 variables on one address and change one without destroy the others by using dqm as byte-enable. >>> >>>If I'm wrong I'm sure someone will correct me. >> >>That is part of it. In essence the DQM is a byte enable. On write it >>will allow or prevent the write on a byte by byte basis. On read, IIRC, >>it will enable the data output or tristate the output on byte by byte >>basis. >> > > > > what does enable mean here ? In Write, DQM is high when it receives data? > I have simulated testbench from micron, the DQM doesnot change. > > > Thanks > > Steven I am a bit confused what you are really asking about. Try to define the following and it might be easier for someone to help you: 1) Give a short introduction what you want to do. 2) What memory are you using, include link to data-sheet (maybe even give page in data-sheet). 3) Find out what you want to test. Probably the micron-provided testbench do not test the features of the dqm therefore the dqm-signal is constant. 4) You could state your level of "electronics knowledge" when posting a follow-up questions. If you don't grasp the basic terminology like e.g "enable" in the given context, doing a SDRAM-interface is quite a complex task. I do not want to discourage you from asking questions but point to that the more specific questions you ask the more likely that someone can give a good answer. /PfnaArticle: 69049
Does anyone know if it is OK to have 3rd party devices in one JTAG chain with Xilinx FPGAs and CPLDs? The Xilinx devices I am using are XC2VP4 and XC9572XL... Thanks, /Mikhail -- To reply directly: matusov at square peg ca (join the domain name in one word and add a dot before "ca")
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