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Hi, I am having problems starting up the Xilinx Platform Studio. I have installed EDK 3.2 with service pack 2. When I run it, I get a message saying "The procedure entry point ?GetProjectToolBarID@Dco_PlToolBarManager@@SAIXZ could not be located in the dynamic link library libDco_Plugin.dll" Im running Windows XP professional with SP1. Also have Xilinx ISE 5.1.3i installed. My env variables seem to be pointing to the correct location. I've tried reinstalling, but of no avail. Any help will be appreciated. VinodArticle: 69176
Dear All, After investigating the price of FPGA PCI boards for a project, it seems the cost of a board is typically 3 to 4 times the component cost for mid-range FPGA's like Xilinx 2V3000. Of course board manufacturers have overheads and need to make a profit - my point isn't to complain about their Gross Profit margin. Rather, at what point is it better to meet the initial capital expenditure of having your own board designed, thereafter only having to meet board manufacturing costs? For example, just how much design time and cost does it take to create a board with - Quicklogic or PLXTech PCI Bridge Single FPGA A PROM Single bank of DDR memory. Surely this type of requirement is common and would not require months of development time or am I being naive? :) Any comments appreciated... Thanks, Andy.Article: 69177
Hi, I am using EDK 3.2 with ISE 5.1.3 on a WinXp machine, and targeting the Virtex 2 pro board. Does Modelsim XE allow me to simulate code running on the PowerPC along with other external blocks written in VHDL as one whole unit? I do not have a board yet, and was also wondering whether such simulations would be prohibitively long. Links to informative websites would be appreciated Thanks VinodArticle: 69178
"Boki" <bokiteam@ms21.hinet.net> wrote in message news:<c6ov4e$pk1@netnews.hinet.net>... > Dear All, > > VHDL / Verilog circuits work in 1-V still correct? > > I want to combine 1-V analog circuits and VHDL circuits.. > > Thanks > > Boki. HDL will work with digital at any voltage its designed for. For mixed signal with VHDL I think there is AVHDL for analog VHDL mixed signal. Its been a while since I looked at that. Somebody in the VHDL group might know. regards johnjakson_usa_comArticle: 69179
Not, Seems extremely unlikely. It is true that without Vcco connected to anything, the ESD protection as well as the other protection circuits for large positive voltages is not well protected. Is this attached to a long cable? If so, you may blow out the IOBs even with the Vcco connected (inductive kickback can cause very large voltages). For long cable applciations, clamp diodes are almost required. Austin NotTooSmart wrote: > Quick question... I've been using a Virtex-E fpga on a development > board that provides jumpers to connect or disconnect Vcco for each I/O > bank. Some of my inputs are LVDS, and one of my signal sources has > LVDS output that swings up as high as ~2.4V at the highest. On one of > my last test runs I accidentally left the Vcco jumper uninstalled for > the IO bank that this device was connected to, meaning that Vcco for > that bank was left floating. To make a long story short, much current > was drawn, and now (probing the FPGA pins directly) Vcco for that I/O > bank appears to be shorted to ground inside the chip package(~1.5 ohms > from Vcco pin to Gnd pin). > > To anyone out there who's familiar with Xilinx hardware, would the > mistake I made above (no Vcco for a ~2.4V input LVDS signal) have > caused the IO bank to become damaged? I'd just like some confirmation > that this is the cause, before I power up the FPGA board and fry > another IO bank...Article: 69180
I am trying to understand some very specifics of the behaviour of the I/O pins of the Xilinx SpartanII family, that I went through in a not quite clean prototype setup. The situation was as follows: I/O pins defined as future outputs, I/O pins connected to a DSP control bus and an old FLUKE (Philips) state analyzer, probably presenting an impedance of a few tens of Kohms to ground per input, Configuration mode = all '1' (Serial Slave Mode, no pre-configuration pullups), 6 FPGA's in a row. By mistake, no pullups or pulldowns on the pins. Thus, a situation where, before programming, voltage on the pins is floating and probably dictated by leakage currents and the equivalent impedance of the state analyzer, Before programming : all I/O's are seen as "HIGH" (Vcc) by the State Analyzer (confirmed by scope reading), BUT : when programming in Slave Serial Mode, somewhere during programming, ALL I/O pins are pulled to "LOW", then return back to "HIGH" at the end of the programming. A reasonable explanation is that the DSP input leakage current, high enough to keep the pins at Vcc when not in programming mode, is not large enough during the programming and is "eaten" by some current pumped to ground by the FPGA. Adding a 10K pullup to 3V3 is enough to always keep the voltage on the pins at "HIGH" during the programming. Has anyone got an explanation for this behaviour ? A. BeaujeanArticle: 69181
arkaitz wrote: > Hi all, > > I am trying to make a post-place & route simulation of a very simple > design. > > In the "top.vhd "file there is declared an entity that contains some > generics and the architecture. > > entity top is > generic( > gen1 : real := 3.0; > gen2 : std_logic; > gen3 : std_logic > ); > port( > clk : in std_logic; > rst : in std_logic; > input : in std_logic; > output : out std_logic > ); > end top; > > When I ask ISE to simulate a PPR simulation with modelsim it generates > a file called "top_timesim.vhd". Then generates a "tb_top.tdo" where > there are some modelsim commands that compile the "top.vhd" and > "tb_top.vhd" files. > > Modelsim generates a "not default binding for component top" error. I > have seen the top_timesim.vhd file and the generics of my top are > deleted! > > Why can be this? Is there any way to avoid this? Unfortunately, there is no way for the software to retain the original generics you defined in the code (at least not yet) and thus when netgen (the Xilinx ISE netlister) creates the entity for your top module, it can not recreate those generics in the declaration. Fortunately though, there is an easy way around this without having to edit the file or the test bench. If you run netgen with the -a switch (In the ISE GUI it is the advanced simulation model property, Generate Architecture Only) the netlist produced will not contain an entity declaration and only contain the architecture. What this allows you to do is retain the original entity declaration with the defined generics from your RTL code and bind the structural timing architecture to that. If you have already run a functional simulation using that RTL code for that project, then all you would need to do is flip this switch and that should fix the problem for you. As long as all of your ports are defined as std_logic/std_logic_vector, you should not have any problems with this. This is also an easy way to get around any top-level ports declared as a buffer rather than an out although I still highly suggest not to declare any port as a buffer in VHDL. Good luck, -- Brian > > Thanks in advance, > > Arkaitz. > > Note: I have rewriten the generics in "top_timesim.vhd" file and now > it works well.Article: 69182
It seems digilentinc actually makes the kit I refrenced earlier. Let me rephrase my question are there any starter kits to be had in the $20-$30 range or is 49.99 the min i am going to find Josiah "Yves Deweerdt" <yves@news.be> wrote in message news:c6qps4$r7t$1@reader13.wxs.nl... > cpex wrote: > > Hello, > > > > I am a computer engineering student and I am looking to do a project which > > will require a FPGA or CPLD. I will need something with > 70 general IO > > pins. I am looking for a development board that will give me an expansion > > port to plug it into my project. I want something less than $100 perferably > > less than $50. I am currently considering the CPLD design kit from XILINX > > which has XC2C256-7TQ144 CoolRunner-II CPLD and XC9572XL-10VQ44 CPLD on it > > as it seems to be a good starter package. Are there other quick dirty > > solutions that will allow me to easily program a device and integrate it > > with my project? I do not need something that has tons of LEDS and > > pushbuttons and tons of extra proto space. > > > > Thank You > > Josiah Vivona > > > > > > Have a look at http://www.digilentinc.com > They have some nice FPGA and CPLD boards. Most of the boards contain > only the necessary with nearly every IO of the FPGA or CPLD going to a > connector. If needed you can add some of their IO-boards which contain > the leds, push buttons, lcds, ... > > Kind regards, > > Yves >Article: 69183
"arkaitz" <arkagaz@yahoo.com> escribió en el mensaje news:c1408b8c.0404290218.5106d484@posting.google.com... > Hi all, > > I am trying to make a post-place & route simulation of a very simple > design. > > In the "top.vhd "file there is declared an entity that contains some > generics and the architecture. > > entity top is > generic( > gen1 : real := 3.0; > gen2 : std_logic; > gen3 : std_logic > ); > port( > clk : in std_logic; > rst : in std_logic; > input : in std_logic; > output : out std_logic > ); > end top; > > When I ask ISE to simulate a PPR simulation with modelsim it generates > a file called "top_timesim.vhd". Then generates a "tb_top.tdo" where > there are some modelsim commands that compile the "top.vhd" and > "tb_top.vhd" files. > > Modelsim generates a "not default binding for component top" error. I > have seen the top_timesim.vhd file and the generics of my top are > deleted! > > Why can be this? Is there any way to avoid this? > > Thanks in advance, > > Arkaitz. > > Note: I have rewriten the generics in "top_timesim.vhd" file and now > it works well. i dont think you should use "generics" in a "top" entity that you want to synthesize (correct me if im wrong). I've heard that some tools accept them and use the default value if specified. what i do is to "wrap" the generic component, and instantiate it into a "wrapper" that doesnt contain any generics and where all generics have been fixed to constants defined in some package. It also eases simulation before and after synthesis, as you only have to switch wrappers (or architectures) in the testbench.Article: 69184
johnjakson@yahoo.com (john jakson) wrote in message news:<adb3971c.0404290626.3d334519@posting.google.com>... > "Boki" <bokiteam@ms21.hinet.net> wrote in message news:<c6ov4e$pk1@netnews.hinet.net>... > > Dear All, > > > > VHDL / Verilog circuits work in 1-V still correct? > > > > I want to combine 1-V analog circuits and VHDL circuits.. > > > > Thanks > > > > Boki. > > HDL will work with digital at any voltage its designed for. > > For mixed signal with VHDL I think there is AVHDL for analog VHDL > mixed signal. Its been a while since I looked at that. Somebody in the > VHDL group might know. > > regards > > johnjakson_usa_com Thank you for information. Best regards, Boki.Article: 69185
IIRC, ModelSIM XE doesn't support the SWIFT models needed to simulate the PowerPCs. Perhaps IBM will give you the VHDL? Perhaps not! ;-) Cheers, Syms. "Vinod" <vananth@gmail.com> wrote in message news:6cd79f5.0404290531.ffccd75@posting.google.com... > Hi, > I am using EDK 3.2 with ISE 5.1.3 on a WinXp machine, and targeting > the Virtex 2 pro board. Does Modelsim XE allow me to simulate code > running on the PowerPC along with other external blocks written in > VHDL as one whole unit? > I do not have a board yet, and was also wondering whether such > simulations would be prohibitively long. > > Links to informative websites would be appreciated > > Thanks > VinodArticle: 69186
Hi, I am involved in a project dealing with fpgas and the pcb may only be used on one side for component placement (actives an passives). Therefore I am considering using a QFP package instead of a BGA package for decoupling purposes mainly. My application runs at 40 MHz and the IO need is small (about 100 IOs). I am considering either a 208 QFP or a 256 FBGA for a Xilinx part like spartan IIE. The other issue is about obsolescence. I noticed the QFP package is still available for Spartan III. Is it a good indicator for the life of this package for Spartan IIE or is this idea irrelevant ? Finally, the temperature of the environment will border 85°C so I believe the regular industrial grade parts we use may be out of our specs. What is the rule for Xilinx parts like spartan IIE or else ? Since the junction temperature is 100°C what happens if the part is in an ambient temperature above 85°C ? Will it keep working or will performance be degraded ? Does it depend on the process of the FPGA for a same grade ? Is there a derating one can apply if the FPGA is out of specs but not about to be destoyed because junction temperature was not reached ? Any idea is welcome !!! JFArticle: 69187
First $50 is a quite good price on a board. It probably represents an educational discount on the parts. Before you go buy the $50 board, I would do an accessment to see if the part meets your needs or do you need to spend a little more ($75/$85), and get a part with more capabilities. Since you are a student, perhaps it might help to put it in perspective of other things you spend money on. How many waters do you have to drink instead of beer or soda to be able to afford the more expensive board or how many bags of chips does the cost of the board represent. It is not as an absurd analysis as you think - chips and soda are much more expensive than you think. Cheers, Jim P.S. When I was in college, I had an active hobby in kayaking. I always thought of expenditures in terms of how many kayak paddles it would buy. Did not eat many bags of chips. I can still count the number of sodas I drink in a year on one hand and the ones I drink are usually free. I can alternately recommend that you pop your own popcorn instead of chip. cpex wrote: > It seems digilentinc actually makes the kit I refrenced earlier. > > Let me rephrase my question are there any starter kits to be had in the > $20-$30 range or is 49.99 the min i am going to find > > Josiah > > "Yves Deweerdt" <yves@news.be> wrote in message > news:c6qps4$r7t$1@reader13.wxs.nl... > >>cpex wrote: >> >>>Hello, >>> >>>I am a computer engineering student and I am looking to do a project > > which > >>>will require a FPGA or CPLD. I will need something with > 70 general IO >>>pins. I am looking for a development board that will give me an > > expansion > >>>port to plug it into my project. I want something less than $100 > > perferably > >>>less than $50. I am currently considering the CPLD design kit from > > XILINX > >>>which has XC2C256-7TQ144 CoolRunner-II CPLD and XC9572XL-10VQ44 CPLD on > > it > >>>as it seems to be a good starter package. Are there other quick dirty >>>solutions that will allow me to easily program a device and integrate it >>>with my project? I do not need something that has tons of LEDS and >>>pushbuttons and tons of extra proto space. >>> >>>Thank You >>>Josiah Vivona >>> >>> >> >>Have a look at http://www.digilentinc.com >>They have some nice FPGA and CPLD boards. Most of the boards contain >>only the necessary with nearly every IO of the FPGA or CPLD going to a >>connector. If needed you can add some of their IO-boards which contain >>the leds, push buttons, lcds, ... >> >>Kind regards, >> >>Yves >> > > > -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~Article: 69188
JF, Wow. Not enough questions? See below, I will try to do my best. Austin jean-francois hasson wrote: > Hi, > > I am involved in a project dealing with fpgas and the pcb may only be used > on one side for component placement (actives an passives). Therefore I am > considering using a QFP package instead of a BGA package for decoupling > purposes mainly. A QFP package has significantly more inductance, and is harder to get a good decoupling design done right. A fgXXX package (fg256) is a much lower inductance value package, and with all components on top, is not impossible at all to do a power distribution decoupling scheme well. You may need two more layers in the pcb stackup to do it right (in either case). If you are having problems with your layout, you may send it into the Hotline, and someone will look at it for you, and advise you. My Lab gets invovled in many pcb cases. I would prefer you learn how to do it right and succeed the first time! My application runs at 40 MHz and the IO need is small > (about 100 IOs). I am considering either a 208 QFP or a 256 FBGA for a > Xilinx part like spartan IIE. The other issue is about obsolescence. I > noticed the QFP package is still available for Spartan III. Is it a good > indicator for the life of this package for Spartan IIE or is this idea > irrelevant ? The QFP will be around for quite awhile. It is too popular, and too high a seller. For extreme SI applications, it is not used, however. Finally, the temperature of the environment will border 85°C so > I believe the regular industrial grade parts we use may be out of our specs. 85C to 100C is 15C junction to ambient. In a QFP package, that might limit you to about 1 watt of power dissipation in the part! This will be tough. > What is the rule for Xilinx parts like spartan IIE or else ? The 'rule' is that above 85C for commercial, and above 100C for Industrial, the device is not expected to meet specifications (but it will still function up to 125C). Since the > junction temperature is 100°C what happens if the part is in an ambient > temperature above 85°C ? Specifications may not be met. Will it keep working or will performance be > degraded ? Functionality will continue to ~125C junction, and beyond that we make no statements or assurances. Does it depend on the process of the FPGA for a same grade ? No. Is > there a derating one can apply if the FPGA is out of specs but not about to > be destoyed because junction temperature was not reached ? In the old days, when everything was simple, simple derating formulas could be applied to the CLB, routing, etc. With DCMs, BRAMs, etc. this no longer works at all. Perhaps you need the automotive version of the parts which is characterized (has a speeds file) for 125C abs max? Contact your disti or Xilinx FAE. > Any idea is welcome !!! Contact your disti or Xilinx FAE. They can be more helpful than I. > > JF > >Article: 69189
"Jim Lewis" <Jim@SynthWorks.com> wrote in message news:1092goikgfsf93@corp.supernews.com... <snip> > Since you are a student, perhaps it might help to put > it in perspective of other things you spend money on. > How many waters do you have to drink instead of beer > or soda to be able to afford the more expensive board <snip> > P.S. > When I was in college, I had an active hobby in kayaking. > I always thought of expenditures in terms of how many > kayak paddles it would buy. Did not eat many bags of > chips. I can still count the number of sodas I drink in > a year on one hand and the ones I drink are usually free. Jim, I notice you didn't economise on beer! Good choice! cheers, Syms.Article: 69190
Hi all, My boss has authorized me to purchase a new machine(dell) to be used for synthesis, translate, map and P&R. I'm looking for some suggestions on which processor P3 vs P4 vs AMD how much memory 1gig or more bus speed which brand server vs end user machine Thanks for your help. I need to order the machine ASAP. Thanks MattArticle: 69191
I will be using a V2pro XC2VP50 On Thu, 29 Apr 2004, Matthew E Rosenthal wrote: > Hi all, > My boss has authorized me to purchase a new machine(dell) to be used for > synthesis, translate, map and P&R. I'm looking for some suggestions on > which processor P3 vs P4 vs AMD > how much memory 1gig or more > bus speed > which brand > server vs end user machine > > Thanks for your help. I need to order the machine ASAP. > > Thanks > > Matt >Article: 69192
Goran, Yeah- I tried that too. But I did find my problem. I was performing the sims on the testbench file expecting it to read the configuration. I ran the one that worked and I realized I was running "vsim system_conf"- and it occured to me- you have to execute the configuration file- not the testbench. Oh well- there is a day I will never get back. I made a system_stub_conf that pointed to system_conf and a testbench_conf that pointed to that. Modelsim did seem to like too much heirarchy in its statements- although I have seen example where the heirarchy goes way down. Thanks for your help, Mike Goran Bilski <goran@xilinx.com> wrote in message news:<c6qfho$24m2@cliff.xsj.xilinx.com>... > Hi, > > If you compile the system_init file into "work", you can use the > configuration specified in the file directly. > A configuration can use another configuration. > > ex. > I have created a testbench "system_tb" for the system generated from XPS: > > In my configuration statement I have this: > > configuration tb_cfg of system_tb is > for VHDL_TEST > for all : system use configuration work.system_conf; > end for; > end for; > end tb_cfg; > > You should be able to do this for your system: > > configuration conf_name of testbenchname is > for testbench_arch > for all : system_stub use configuration work.system_conf > end for; > end for; > end conf_name; > > > MS wrote: > > >I am using the Xilinx EDK to perform simulations of the embedded > >PowerPC on a V2Pro. I have had success using simply the EDK with > >Modelsim but when I change the flow to the ISE as an embedded project- > >I am having trouble getting the boot ROM to be read in as a > >configuration in Modelsim. > > > >The trouble has to do with assigning the blockRAM configurations to > >the blockmemories once I wrapped the system_stub in a testbench. I > >was able to get this all to work with ISE when I did not embed the > >processor, but once it is embedded- the blockRAM moves a level down in > >the heirarchy and then the configuration statement does not compile. > >My understanding in VHDL is it is like this.... (I am improvising from > >memory here) > > > >configuration name of testbenchname is > > for behavior -- arch name > > for uut: system_stub -- unit under test > > for STRUCUTRE -- arch of system_stub > > for system_i: system -- declared system > > for structure > > for all: blockram_types: use work.blockram_conf; > >bunch of end fors and end of configuration > > > >I stole this from the system_init file and added my new levels of > >heirarchy. > > > >It complains to me that system is not a valid component- but in the > >work directory I see it there clear as day. Is there a limit to how > >far down in the heirarchy you can assign configurations? I do not > >believe so. I tried making multiple level configurations and have had > >no luck either. > > > >If I blow this away- the PowerPC fetches from FFFFFFC and gets zero > >back. When done properly, it fetches the first opcode and I am off an > >running. > > > >Thanks, > >MS > > > >Article: 69193
In article <Pine.LNX.4.58-035.0404291458250.11736@unix48.andrew.cmu.edu>, Matthew E Rosenthal <mer2@andrew.cmu.edu> wrote: >Hi all, >My boss has authorized me to purchase a new machine(dell) to be used for >synthesis, translate, map and P&R. I'm looking for some suggestions on >which processor P3 vs P4 vs AMD P4, hyperthreaded turned on. Allows you to do some low-intensity work while the tools are grinding away, without paying the extra cost for a multiprocessor system. >how much memory 1gig or more. As Much As Possible (tm). ECC definatly preferred (Soft Errors Happen (tm)). >bus speed HT P4s are all the 400 MHz DDR bus, which is what you want. >which brand >server vs end user machine High end workstation. Disk is less important, you want reasonably fast but reliability counts for more. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 69194
Click on the disk icon in the second column "ted" <edaudio2000@yahoo.co.uk> wrote in message news:c54bf83f.0404280333.3f03ac24@posting.google.com... > Leon > > I have tried the website, I even registered, but somehow, I cannot > click on the "byteblaster.pdf" link to download. How do you get to > download the file?? > > Thanks > Ted > > > > I just came across this schematic for the ByteBlaster II: > > > > http://www.mcu.cz/atm/index.php?direction=0&order=&directory=EDA > > > > Someone has probably worked out the circuit by tracing the connections on a > > unit as Altera hasn't published it, AFAIK. > > > > LeonArticle: 69195
fpgadev@yahoo.com (AndyAtHome) wrote in message news:<29ab33c4.0404290413.2b5a2be5@posting.google.com>... > Dear All, > > After investigating the price of FPGA PCI boards for a project, it > seems the cost of a board is typically 3 to 4 times the component cost > for mid-range FPGA's like Xilinx 2V3000. > > Of course board manufacturers have overheads and need to make a profit > - my point isn't to complain about their Gross Profit margin. > > Rather, at what point is it better to meet the initial capital > expenditure of having your own board designed, thereafter only having > to meet board manufacturing costs? > > For example, just how much design time and cost does it take to create > a board with - > > Quicklogic or PLXTech PCI Bridge > Single FPGA > A PROM > Single bank of DDR memory. > > Surely this type of requirement is common and would not require months > of development time or am I being naive? :) > > Any comments appreciated... Well, it really depends on how many boards you need, and whether the hardware design on the off-the-shelf board meets your requirements. Regarding the former, it's simply the classic make/buy decision. If you need a handful boards, buying them makes sense because you can concentrate your development efforts into the FPGA and you know (or at least hope!) that the board design itself is stable. If you need a lot of boards, then it may very well make sense to spin your own. Rolling your own board requires a different skill set from designing an FPGA, and if you don't have those skills (and the software tools), then you have to hire them and that cost may bust your budget. You also have to learn about (or have in place) the entire manufacturing process, including purchasing, board fab, stuffing, everything, which will distract you from your FPGA design :) Of course, if no off-the-shelf board meets your needs, then your choice is clear. Besides, a product that costs only three times the bill-of-materials is kinda cheap :) -aArticle: 69196
I've found some boards with 32 LVDS channels. The problem is that all the 32 channels have a common clock. I would like to connect a different sub unit to each pin of the 32 channels. How can I distribute the clock to all sub units? þþ"Hal Murray" <hmurray@suespammers.org> ëúá áäåãòä news:9tSdnVZp843-mRLdRVn-sA@megapath.net... > >We are planning a data acquisition system with 4-12 sub units. Each sub unit > >produce data of 25MBit/sec. The distance between the boxes and computer is > >about 2 meters. > >I'm willing to transfer and analyze the data in real-time. I'm willing to > >close a control loop in 1-5msec (I. wish 100usec ......). > >What is the recommended serial protocol? > >The sub units will be in-house made the host computer for data analysis and > >storage will be a PC (probably with raid HD). > >What communication HW/protocol should I use in my sub units? > >What communication HW/protocol should I use in the PC? > > One straw man would be 100 megabit ethernet. That lets you use > off-the-shelf gear on the PC end. For 12 sub units, you probably > need a gigabit ethernet card on the PC and a 12 port switch > with a gigabit uplink. (It also gives you lots of flexibility > on the length which might be handy some day.) > > If you want to build your own PCI card, look at LVDS. 25 megabits > should be easy at 2 meters. Manchester encoding costs a factor > of 2 in link bandwidth (which you have lots of) but it's real > simple to decode. > > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 69197
Nicholas C. Weaver wrote: > HT P4s are all the 400 MHz DDR bus, which is what you want. Is that 200MHz?Article: 69198
Leon Heller wrote: > "Leon Heller" <leon_heller@hotmail.com> wrote in message > news:408cffe8$0$19420$cc9e4d1f@news-text.dial.pipex.com... > >>"Rene Tschaggelar" <none@none.net> wrote in message >>news:408cd362$0$703$5402220f@news.sunrise.ch... >> >>>Leon Heller wrote: >>> >>> >>>> I just came across this schematic for the ByteBlaster II: >>>> >>>>http://www.mcu.cz/atm/index.php?direction=0&order=&directory=EDA >>>> >>>>Someone has probably worked out the circuit by tracing the connections >> >>on a >> >>>>unit as Altera hasn't published it, AFAIK. >>> >>>And does it work ? >> >>I mean to try it, when I get my Cyclone board finished. > > > A problem with this is that the BF550 and BF570 transistors used are > unavailable - 20 weeks delivery according to Arrow. 8-( > > I'll see if I can find equivalent devices. Since this is not a precision analog device, I guess any bipolar does the job. Basically two inverters to boost the voltage plus an emitter follower to lower the output impedance. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 69199
Hello everyone, I was wondering what the standard design practice is for turning off the clock for some parts of an FPGA design while keeping other parts running. I would assume simply gating the clock (followed by a global clock buffer) introduces unacceptable amounts of clock skew. Perhaps this method could be combined with use of a delay-locked loop as present in the Xilinx FPGAs to keep the gated clock synchronous to the rest of the system? Of course the gating circuit would also have to take care of switching the gated clock glitchless, for which perhaps a circuit could be used such as the one on http://www.eedesign.com/features/exclusive/OEG20030626S0035 (referred to by FAQ answer "Switching clocks without glitches"). Or am I overlooking a simpler solution? A similar problem exists when instead of turning the clock off it is switched to a divided version (produced by counter) of itself, while other parts keep running at the full speed or a different division factor. I would prefer to keep the whole system synchronous (e.g. all switched or divided versions of the same clock with minimal skew) because else the different parts would need anti-metastability sychronizers such as 2 or 3 flipflops in series on all their communication lines... greetings, Tom
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