Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 69100

Article: 69100
Subject: Design PAR in Stratix
From: petersommerfeld@hotmail.com (Peter Sommerfeld)
Date: 27 Apr 2004 03:09:35 -0700
Links: << >>  << T >>  << A >>
Hi folks,

I have a very simple design that uses 3 LEs in Stratix when compiled
with either Quartus II 4.0 or Synplify. There must be something I
don't realize about the LE/routing architecture because I think it
should/could use only 1 LE (see design below). I would think the
design should connect the four terms to the 4 inputs of the LUT, feed
this LUT's output to the D-input of the register of the same LE, and
also connect the enable and reset of the register with the respective
inputs.

Here's what it does instead: Routes the 4 terms to its own LUT, then
ANDs the LUT's output with the enable input in a 2nd LE and fianlly
uses this result as the enable of the register in a 3rd LE. The
D-input of this register is tied to VCC. Seems very odd to me.

In Quartus, I turned on Optimize Area, Auto Packed Regs=Minimize, and
played with a few other options, to no avail. Setting the fmax
sufficiently high packed the design into 2 LEs but did it in a wierd
way. I'm curious why the design doesn't ever route into 1 LE?

-- Pete

library ieee;
use ieee.std_logic_1164.all;

entity test_4input is
       port (
         clk           : in std_logic;
         -- should go to LE's reset:
         rst_n         : in std_logic;
         ena           : in std_logic;
         -- four terms:
         a, b, c, d    : in std_logic;
         result        : out std_logic     );
end;

architecture rtl of test_4input is
       signal sig : std_logic;
begin

       process( clk, rst_n ) 
       begin
              if rst_n='0' then
                 sig    <= '0';
              elsif clk'event and clk='1' then
                 if ena='1' then
                       if (a xor b xor c xor d)='1' then
                             sig <= '1';
                       end if;
                 end if;
              end if;
       end process;

       result <= sig;
end;

Article: 69101
Subject: Re: Design PAR in Stratix
From: Marc Randolph <mrand@my-deja.com>
Date: Tue, 27 Apr 2004 07:22:45 -0500
Links: << >>  << T >>  << A >>
Peter Sommerfeld wrote:
> Hi folks,
> 
> I have a very simple design that uses 3 LEs in Stratix when compiled
> with either Quartus II 4.0 or Synplify. There must be something I
> don't realize about the LE/routing architecture because I think it
> should/could use only 1 LE (see design below). I would think the
> design should connect the four terms to the 4 inputs of the LUT, feed
> this LUT's output to the D-input of the register of the same LE, and
> also connect the enable and reset of the register with the respective
> inputs.
> 
> Here's what it does instead: Routes the 4 terms to its own LUT, then
> ANDs the LUT's output with the enable input in a 2nd LE and fianlly
> uses this result as the enable of the register in a 3rd LE. The
> D-input of this register is tied to VCC. Seems very odd to me.

Howdy Peter,

It doesn't seem so odd to me since that is basically what the code is 
telling it to do.  The code fragment creates a latch that, once set, 
never clears until the reset happens.  This means that it can't use the 
D-input of the FF, and it also means that the control for the enable 
input has 5 inputs (requiring two LUTs).

So the only question in my mind is if the Stratix can't control the 
enable input of the FF from a LUT within the same LE, or the tools don't 
know how.

If you didn't mean to have a latch, you might put a "sig <= '0';" in 
there somewhere.  Or get rid of the inner-most if statement altogether.

Have fun,

    Marc

> In Quartus, I turned on Optimize Area, Auto Packed Regs=Minimize, and
> played with a few other options, to no avail. Setting the fmax
> sufficiently high packed the design into 2 LEs but did it in a wierd
> way. I'm curious why the design doesn't ever route into 1 LE?
> 
> -- Pete
> 
> library ieee;
> use ieee.std_logic_1164.all;
> 
> entity test_4input is
>        port (
>          clk           : in std_logic;
>          -- should go to LE's reset:
>          rst_n         : in std_logic;
>          ena           : in std_logic;
>          -- four terms:
>          a, b, c, d    : in std_logic;
>          result        : out std_logic     );
> end;
> 
> architecture rtl of test_4input is
>        signal sig : std_logic;
> begin
> 
>        process( clk, rst_n ) 
>        begin
>               if rst_n='0' then
>                  sig    <= '0';
>               elsif clk'event and clk='1' then
>                  if ena='1' then
>                        if (a xor b xor c xor d)='1' then
>                              sig <= '1';
>                        end if;
>                  end if;
>               end if;
>        end process;
> 
>        result <= sig;
> end;

Article: 69102
Subject: JTAG, Master Serial Mode
From: c.chen@gmx.de (Chao)
Date: 27 Apr 2004 06:56:09 -0700
Links: << >>  << T >>  << A >>
Hello, 

I have one general question concerning the FPGA supported
configuration mode. I am using Xilinx ISE iMpact to program Spartan-3.
I use the JTAG Cable-IV to download the bitstream to the Spartan-3.
Meanwhile I set up the configuration jumper on board to JTAG mode
(i.e. M0,M1,M2=0,1,0). That works fine. But if I set up the jumper to
MASTER-SERIAL (i.e. M0,M1,M2=1,1,1) mode, I can still download the
bitstream to the Spartan-3 via JTAG cable. I expected that I can
download the bitstream via JTAG cable only under JTAG mode jumper set
on board.  Does the jumper on board have nothing to do with the iMpact
"software" based configuration mode set?

Thanks in advance for your explanation.

Chao.

Article: 69103
Subject: Re: Design PAR in Stratix
From: petersommerfeld@hotmail.com (Peter Sommerfeld)
Date: 27 Apr 2004 06:59:39 -0700
Links: << >>  << T >>  << A >>
Oops, never mind. I realized my mistake right after I posted.

-- Pete

petersommerfeld@hotmail.com (Peter Sommerfeld) wrote in message news:<5c4d983.0404270209.7a5a45a0@posting.google.com>...
> Hi folks,
> 
> I have a very simple design that uses 3 LEs in Stratix when compiled
> with either Quartus II 4.0 or Synplify. There must be something I
> don't realize about the LE/routing architecture because I think it
> should/could use only 1 LE (see design below). I would think the
> design should connect the four terms to the 4 inputs of the LUT, feed
> this LUT's output to the D-input of the register of the same LE, and
> also connect the enable and reset of the register with the respective
> inputs.
> 
> Here's what it does instead: Routes the 4 terms to its own LUT, then
> ANDs the LUT's output with the enable input in a 2nd LE and fianlly
> uses this result as the enable of the register in a 3rd LE. The
> D-input of this register is tied to VCC. Seems very odd to me.
> 
> In Quartus, I turned on Optimize Area, Auto Packed Regs=Minimize, and
> played with a few other options, to no avail. Setting the fmax
> sufficiently high packed the design into 2 LEs but did it in a wierd
> way. I'm curious why the design doesn't ever route into 1 LE?
> 
> -- Pete
> 
> library ieee;
> use ieee.std_logic_1164.all;
> 
> entity test_4input is
>        port (
>          clk           : in std_logic;
>          -- should go to LE's reset:
>          rst_n         : in std_logic;
>          ena           : in std_logic;
>          -- four terms:
>          a, b, c, d    : in std_logic;
>          result        : out std_logic     );
> end;
> 
> architecture rtl of test_4input is
>        signal sig : std_logic;
> begin
> 
>        process( clk, rst_n ) 
>        begin
>               if rst_n='0' then
>                  sig    <= '0';
>               elsif clk'event and clk='1' then
>                  if ena='1' then
>                        if (a xor b xor c xor d)='1' then
>                              sig <= '1';
>                        end if;
>                  end if;
>               end if;
>        end process;
> 
>        result <= sig;
> end;

Article: 69104
Subject: Re: Design PAR in Stratix
From: Marius Vollmer <marius.vollmer@uni-dortmund.de>
Date: Tue, 27 Apr 2004 16:07:54 +0200
Links: << >>  << T >>  << A >>
petersommerfeld@hotmail.com (Peter Sommerfeld) writes:

I have only rudimentary synthesis experience, but let me try anyway...

> I'm curious why the design doesn't ever route into 1 LE?
>
> [...]
>               if rst_n='0' then
>                  sig    <= '0';
>               elsif clk'event and clk='1' then
>                  if ena='1' then
>                        if (a xor b xor c xor d)='1' then
>                              sig <= '1';
>                        end if;
>                  end if;
>               end if;
> [...]

'sig' is never set to '0', except when resetting.  Should it simply be

                  if ena='1' then
                    sig <= (a xor b xor c xor d);
                  end if;

Article: 69105
Subject: Re: Simulating two clock domains
From: "fe" <notvalid@nowhere.com>
Date: Tue, 27 Apr 2004 10:47:16 -0400
Links: << >>  << T >>  << A >>
You want out to be low for 3 clk_60 cycles (1 clk_20) when input rise.

To avoid problem of passing from one clk domain to the other (because both
clks must be balanced at both aux and out registers), you can do this if
input high time and low time are both at least 3 clk_60 cycles width all the
time and it's synchronous with clk_60.

     signal aux : std_logic_vector(2 downto 0);

     process( rst, clk_60 )
     begin
       if ( rst = '1' ) then
         aux <= (others => '0');
       elsif ( clk_60 = '1' and clk_60'event ) then
         aux <= aux(1 downto 0) & input;
       end if;
     end process;

     re_edge <= not(aux(2)) and input; -- 3 clk cycles pulse width

If you use Xilinx, the shift register is free but I don't know if you can
reset it.

regards
fe




Article: 69106
Subject: Re: Design PAR in Stratix
From: incorrigible@comcast.net (Bill)
Date: 27 Apr 2004 07:59:15 -0700
Links: << >>  << T >>  << A >>
Pete,

The way you've coded this, once the enable is active while the xor
equation is true, the flop will be set to "1" and ALWAYS remain "1",
unless the async reset goes active.  The flop retains a "1" regardless
of the state of the enable or the 4-input function.  Even if you
forced the tool to use the enable, it would still require a 5-input
function (two LEs) This function would be the 4-input equation or'd
with flop's current value.

When f = a xor b xor c xor d the following truth table represents your
function:

ena | f  | current | next
-------------------------
 0  | 0  |  0      | 0
 0  | 1  |  0      | 0
 1  | 0  |  0      | 0
 1  | 1  |  0      | 1
 X  | X  |  1      | 1
 

The functions are implemented in separate LEs, as Synplify has chosen
to use the flop's enable and in Stratix the enable cannot be driven
directly by the result of the associated LUT.

I don't think you've coded your intended functionallity.  If it's
coded as follows, it implements in a single LE using the clock enable
and the 4-input LUT.  In this case, the flop loads the result of the
xor equation when the enable is active and retains its current value
when the enable is inactive.

process( clk, rst_n ) 
  begin
    if rst_n='0' then
      sig    <= '0';
    elsif clk'event and clk='1' then
      if ena='1' then
        if (a xor b xor c xor d)='1' then
          sig <= '1';
        else
          sig <= '0';
        end if;
      end if;
    end if;
end process;

An alternative coding would be:

process( clk, rst_n ) 
  begin
    if rst_n='0' then
      sig    <= '0';
    elsif clk'event and clk='1' then
      if ena='1' then
        sig <= a xor b xor c xor d;
      end if;
    end if;
end process;

Bill

Article: 69107
Subject: Re: transport applications
From: johnjakson@yahoo.com (john jakson)
Date: 27 Apr 2004 08:06:31 -0700
Links: << >>  << T >>  << A >>
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<c6l7o4$mru$1@news.tu-darmstadt.de>...
> Hal Murray <hmurray@suespammers.org> wrote:
> : > It provides high speed on an old-fashioned rail bed.
>  
> : Why do I want tilting trains?  Why not bank the tracks more?
> 
> Because then, when an emergency braking has to be exercised, the train would
> fall over...

Thanks Symon, things have changed so much that Virgin seems to run
everything:-/


I believe the newer French track laid down for their highspeed is
gently banked and with large turning space, well I've only seen tv
snips in the countryside. I guess in UK (I left 20yrs ago) most of the
track is in densely populated areas, too late to do anything about it.
Perhaps the only place to put any new service would be near/over the
motorway.

regards

johnjakson_usa_com

Article: 69108
Subject: Re: Inferring Dynamic shift registers in XST
From: johnjakson@yahoo.com (john jakson)
Date: 27 Apr 2004 08:13:16 -0700
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> wrote in message news:<408DD446.5727B22@andraka.com>...
> The OP stated that he was trying to infer a DYNAMIC shift register, which implies an SRL16.

whoops, missed the DYNAMIC part,
> Otherwise, he needs a register file with a mux, which is both bulky and slow.  The synthesis tools
> are notoriously inconsistent and picky about the style needed for this structure to be inferred as

indeed
> an SRL16, and I've seen different tools wind up with different results, even when going between

I'll be adding FFed srls later on when the dust has settled. perhaps I
should look at dynamic too for queues, although ram based will
probably give me about same cost/perf/area

regards

johnjakson_usa_com

Article: 69109
Subject: Re: SDRAM's dqm
From: dxslyz@lycos.de (Steven)
Date: 27 Apr 2004 08:18:48 -0700
Links: << >>  << T >>  << A >>
excuse me, Fredrik, I have thought the interface of sdram is almost
same from different manufacturers, it seems not so true.

I am now doing a sdram controller design for a special processor
architecture
The Ram I targets is Micron's sdram MT48LC16M16A2TG, which has 256mb
capacity.

Here is the address of it. 
http://www.micron.com/products/dram/sdram/part.aspx?part=MT48LC16M16A2TG-6A

The signal dqm causes me much wonder. The datasheets says: 

--- quote ---
Input/Output Mask: DQM is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when
DQM is sampled HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (two-clock latency) when DQM is sampled
HIGH during a READ cycle. On the x16, DQML corresponds to DQ0-DQ7 and
DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered
same state when referenced as DQM.

-- quote end -----

DQM is input signal, which I falsely thought is output in the first
message. Is mask means that I can overwrite just part of address, say
1 byte from 2 bytes cell? This is what was suggested by the above
msgs. But what is dqm function in read, what means "an output enable
signal for read accesses."

Thanks 

Steven

Article: 69110
Subject: Re: transport applications
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 27 Apr 2004 08:27:36 -0700
Links: << >>  << T >>  << A >>
The Swedish S2000 tilting train is not pulled by a locomotive. It has
electric motors driving every single car.
The main reason for tilting is passenger comfort. The problem is that there
must be enough room between the rail pairs for two trains to meet.

The French and Japanese laid new tracks for their TGV and Shinkansen trains,
and the Germans did it in some places (Cologne-Frankfurt), but Sweden is a
large country with relatively few people, so the economics are different
Peter Alfke (likes to ride European trains...).
==============

> From: hmurray@suespammers.org (Hal Murray)
> Newsgroups: comp.arch.fpga
> Date: Mon, 26 Apr 2004 19:44:04 -0500
> Subject: Re: transport applications
> 
>> It provides high speed on an old-fashioned rail bed.
> 
> Why do I want tilting trains?  Why not bank the tracks more?
> 
> Is the problem something like a tight radius of curvature
> such that a long train would get pulled off the track as
> it went around the curve?  (Maybe a long slow freight runs on
> the same tracks.)
> 
> -- 
> The suespammers.org mail server is located in California.  So are all my
> other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's.  I hate spam.
> 


Article: 69111
Subject: Re: transport applications
From: Jonathan Bromley <jonathan.bromley@doulos.com>
Date: Tue, 27 Apr 2004 16:35:44 +0100
Links: << >>  << T >>  << A >>
On 27 Apr 2004 08:06:31 -0700, johnjakson@yahoo.com 
(john jakson) wrote:

>I believe the newer French track laid down for their highspeed is
>gently banked and with large turning space, well I've only seen tv
>snips in the countryside.

TGVs run at full speed only on specially-laid, dedicated tracks
with solid concrete track-bed.  Not cheap.  The usual UK legacy
track (wooden sleepers, a few tons of dirty stone chippings for
ballast) wouldn't be a lot of use.

A few years ago I read a French newspaper article suggesting 
that the TGVs have lots of power available from the overhead 
rail, and therefore slopes are much less of a problem than
they were for traditional trains.  But curves would dramatically
limit the speed - you can't bank a railway curve very much,
because you have to cope with the possibility of a stationary
train on the banked section :-)  Presumably the same thing
applies to VERTICAL curves - you don't want the train, or
its passengers, experiencing large local variations in 'g'.

> I guess in UK (I left 20yrs ago) most of the
>track is in densely populated areas, too late
> to do anything about it.

Too late, too little will, land prices too high, railways
badly out of fashion and suffering a serious image problem.

>Perhaps the only place to put any new service would be 
>near/over the motorway.

And spoil the motoring lobby's God-given right to extend the
carriageway to 5 or 6 lanes each way?  No hope.
(Seriously - UK motorways often have curves that would be
far too severe for TGV-class trains.)
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223          mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                Web: http://www.doulos.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Article: 69112
Subject: Re: Byteblaster Download cable schematics not available from altera site
From: kensmith@violet.rahul.net (Ken Smith)
Date: Tue, 27 Apr 2004 16:04:29 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <c6gf4e$2nu$1@inf2.informatik.uni-stuttgart.de>,
Florian Student  <studenfn@trick.informatik.uni-stuttgart.de> wrote:
>Hello everybody,
>
>I was planning to get into fpgas/cplds but don't really want do buy an 
>expensive starterkit. As an older post indicated altera has published 
>the schematics of their byteblaster download cable. However it was not 
>listed on the site and a google link 
>www.altera.com/literature/ds/dsbyte.pdf only gives a file not found error.
>
>Does anybody of you have the file (dsbyte.pdf) and could send it to me, 
>or point me to an alternative download location.

You can make a cable that works with just wire, connectors and 100 ohm 
resistors.  To use it, you have to use the version of Altera's JAM-ISP 
program I have here on my PC.  If no-one else gives you a good solution, 
I'll see if I can send you what you need.

-- 
--
kensmith@rahul.net   forging knowledge


Article: 69113
Subject: Re: JTAG, Master Serial Mode
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 27 Apr 2004 09:13:38 -0700
Links: << >>  << T >>  << A >>
Xilinx went to great efforts to write it, so read the bloody datasheet!
Quote:-
"Configuration through the boundary-scan port is always available,
independent of the mode selection. Selecting the Boundary-Scan mode simply
turns off the other modes."
Syms.

"Chao" <c.chen@gmx.de> wrote in message
news:8228a344.0404270556.23004f45@posting.google.com...
> Hello,
>
> I have one general question concerning the FPGA supported
> configuration mode. I am using Xilinx ISE iMpact to program Spartan-3.
> I use the JTAG Cable-IV to download the bitstream to the Spartan-3.
> Meanwhile I set up the configuration jumper on board to JTAG mode
> (i.e. M0,M1,M2=0,1,0). That works fine. But if I set up the jumper to
> MASTER-SERIAL (i.e. M0,M1,M2=1,1,1) mode, I can still download the
> bitstream to the Spartan-3 via JTAG cable. I expected that I can
> download the bitstream via JTAG cable only under JTAG mode jumper set
> on board.  Does the jumper on board have nothing to do with the iMpact
> "software" based configuration mode set?
>
> Thanks in advance for your explanation.
>
> Chao.



Article: 69114
Subject: Re: Xilinx Block RAM Init
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Tue, 27 Apr 2004 09:18:58 -0700
Links: << >>  << T >>  << A >>

Hi,

Go to http://www.engr.sjsu.edu/crabill and download lab
assignment #5, including the zip of the project files.
The main point of this lab is to learn how to use BlockRAM 
primitives to build a large ROM in a Spartan-IIE device.
It's done in Verilog.

Eric

Arlen wrote:
> 
> I have a Xilinx Spartan IIE device and it has built in block
> rams that I would like to use for effectively a ROM design.

Article: 69115
Subject: Re: SDRAM's dqm
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 27 Apr 2004 12:19:00 -0400
Links: << >>  << T >>  << A >>
Steven wrote:
> 
> excuse me, Fredrik, I have thought the interface of sdram is almost
> same from different manufacturers, it seems not so true.
> 
> I am now doing a sdram controller design for a special processor
> architecture
> The Ram I targets is Micron's sdram MT48LC16M16A2TG, which has 256mb
> capacity.
> 
> Here is the address of it.
> http://www.micron.com/products/dram/sdram/part.aspx?part=MT48LC16M16A2TG-6A
> 
> The signal dqm causes me much wonder. The datasheets says:
> 
> --- quote ---
> Input/Output Mask: DQM is an input mask signal for write accesses and
> an output enable signal for read accesses. Input data is masked when
> DQM is sampled HIGH during a WRITE cycle. The output buffers are
> placed in a High-Z state (two-clock latency) when DQM is sampled
> HIGH during a READ cycle. On the x16, DQML corresponds to DQ0-DQ7 and
> DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered
> same state when referenced as DQM.
> 
> -- quote end -----
> 
> DQM is input signal, which I falsely thought is output in the first
> message. Is mask means that I can overwrite just part of address, say
> 1 byte from 2 bytes cell? This is what was suggested by the above
> msgs. But what is dqm function in read, what means "an output enable
> signal for read accesses."

The above quote is what I remembered about DQM.  It is a mask or a byte
enable for writing and an output enable for reading.  There will be a
separate DQM input signal for each byte in the SDRAM.  

In read the output of a byte that is not enabled is held tri-state
(Hi-Z).  Bytes that are enabled will output data onto the data bus.  

If you don't need independant byte access, you can just tie all DQM
signals low and the chip will always read or write the full word of
data.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 69116
Subject: Xpower Static Current
From: rajarsheeb@yahoo.com (raj)
Date: 27 Apr 2004 10:33:55 -0700
Links: << >>  << T >>  << A >>
Hi,
I have a quick qustion regarding Xpower.

Does it report the static(leakage) power/current consumed by the
current design.
The Quiescent Current Definition says "Current Flow into the 
Device with no signal switching".But I am not sure whether Quiescent
Current includes the Static Current.Even if in the  design I add/delete new
components  the Quiescent current remain same.Please advise.

regards
--raj

Article: 69117
Subject: Strange message from Xilinx 6.2.01i
From: "Geoffrey Mortimer" <me@privacy.net>
Date: Tue, 27 Apr 2004 19:49:15 +0200
Links: << >>  << T >>  << A >>
Hi

Anyone ever seen this and or know what it means?

Mapping a total of 117 equations into 16 function
blocks.................................................................
java.lang.ClassCastException: org.apache.xalan.res.XSLTErrorResources_it
 at org.apache.xalan.xslt.Process.main(Unknown Source)
Exception in thread "main"
Design a3010_cpld has been optimized and fit into device XC95288XL-7-FG256.
Completed process "Fit".

TIA

Geoff



Article: 69118
Subject: Re: transport applications
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 27 Apr 2004 10:54:46 -0700
Links: << >>  << T >>  << A >>
>
> I believe the newer French track laid down for their highspeed is
> gently banked and with large turning space, well I've only seen tv
> snips in the countryside. I guess in UK (I left 20yrs ago) most of the
> track is in densely populated areas, too late to do anything about it.
> Perhaps the only place to put any new service would be near/over the
> motorway.
>
> regards
>
> johnjakson_usa_com
Hi John,
I heard that the French have a much more 'robust' compulsary purchase scheme
than other countries, i.e. Draw a straight line on the map between Paris to
Lyons and that's where the railway's gonna go! Interesting idea about the
Motorways, here in San Jose I go along Hwy 85 to work, (right past the
Xilinx campus, as it happens, so I'm still on topic ;-)) which is a fairly
new road. There's a light rail system along the central reservation (=Median
for US readers!) for a fair part of the journey. No-one uses it, of course.
No point in owning a Hummer and leaving it at home....
Jonathan's right about economics of new track in the UK. In order to do
anything, you have to tunnel. Check out
http://news.bbc.co.uk/1/hi/england/2223468.stm The good thing about this is
that French passengers will now arrive at St.Pancras. If you're French, I
guess that's much better than terminating at Waterloo!
cheers, Syms.



Article: 69119
Subject: Re: Xpower Static Current
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 27 Apr 2004 14:04:51 -0400
Links: << >>  << T >>  << A >>
raj wrote:
> 
> Hi,
> I have a quick qustion regarding Xpower.
> 
> Does it report the static(leakage) power/current consumed by the
> current design.
> The Quiescent Current Definition says "Current Flow into the
> Device with no signal switching".But I am not sure whether Quiescent
> Current includes the Static Current.Even if in the  design I add/delete new
> components  the Quiescent current remain same.Please advise.

If you think about the nature of static current you will realize that
"adding" components to your design will have no effect on it. 
Regardless if your design uses the components on the chip, the logic is
still there and will draw static power.  When you use a component, you
then need to include it in your dynamic power calculations since it will
be switching.  

The chip will draw the same static power even if your design has no
components.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 69120
Subject: Re: CPLD input
From: Hans Maier <Hans@Maier.com>
Date: Tue, 27 Apr 2004 20:11:25 +0200
Links: << >>  << T >>  << A >>
>  You could clarify if your 50mA meant 50 microamps, or
>50 milliamps. Many times I've seen the greek 'u' in uA
>morph into mA on the internet as it jumps fonts....
>  50uA could be a normal pin pullup, 50mA sounds like
>the PFET is on.

it is 0.050 A or 50 milliamps


>  A simple test is to try moving the function to another pin,
> or simply swap the pin allocates (two same-class pins).

Thanks I will do that.

>  If the problem stays with the pin, it's likely to be
>chip related, if it moves with the function, suspect something
>in your code...

code is very simple:

VCC_SENSE: in    std_logic;                       -- sense power    



Article: 69121
Subject: Re: transport applications
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 27 Apr 2004 11:14:23 -0700
Links: << >>  << T >>  << A >>
Here's a better link about the tunneling under London.
http://news.bbc.co.uk/1/hi/uk/2225861.stm



Article: 69122
Subject: Re: transport applications
From: krw <krw@att.biz>
Date: Tue, 27 Apr 2004 15:06:22 -0400
Links: << >>  << T >>  << A >>
In article <c6m7ud$dm6n5$1@ID-212844.news.uni-berlin.de>, 
symon_brewer@hotmail.com says...
> Here's a better link about the tunneling under London.
> http://news.bbc.co.uk/1/hi/uk/2225861.stm
> 
Guy Fawkes?

-- 
  Keith

Article: 69123
Subject: Re: CPLD input
From: "John_H" <johnhandwork@mail.com>
Date: Tue, 27 Apr 2004 20:13:16 GMT
Links: << >>  << T >>  << A >>
Here's a weird thought...  Try VOLT_SENSE: in
              -- sense power


"Hans Maier" <Hans@Maier.com> wrote in message
news:1f8t80lcr6kj8ghv4dao4qb6spbfhvrct1@4ax.com...
> >  You could clarify if your 50mA meant 50 microamps, or
> >50 milliamps. Many times I've seen the greek 'u' in uA
> >morph into mA on the internet as it jumps fonts....
> >  50uA could be a normal pin pullup, 50mA sounds like
> >the PFET is on.
>
> it is 0.050 A or 50 milliamps
>
>
> >  A simple test is to try moving the function to another pin,
> > or simply swap the pin allocates (two same-class pins).
>
> Thanks I will do that.
>
> >  If the problem stays with the pin, it's likely to be
> >chip related, if it moves with the function, suspect something
> >in your code...
>
> code is very simple:
>
> VCC_SENSE: in    std_logic;                       -- sense power
>
>



Article: 69124
Subject: Re: Strange message from Xilinx 6.2.01i
From: Jim Granville <no.spam@designtools.co.nz>
Date: Wed, 28 Apr 2004 09:11:04 +1200
Links: << >>  << T >>  << A >>
Geoffrey Mortimer wrote:
> Hi
> 
> Anyone ever seen this and or know what it means?

  That Xilinx are using too much Java in their tools .... ? :)

  Given design lifetimes, version control issues, and stability, using 
Java does look a strange decision.

  On my V6.2, I've seen various Java stumbles, and thus I avoid
the java pathways - so far as I can tell, it's restricted to the 
reporting parts of the tools, not the real 'engine room' stuff.

  Your report suggests the FIT actually worked, so the java exception
shown was (hopefully) not mission critical....

-jg

> Mapping a total of 117 equations into 16 function
> blocks.................................................................
> java.lang.ClassCastException: org.apache.xalan.res.XSLTErrorResources_it
>  at org.apache.xalan.xslt.Process.main(Unknown Source)
> Exception in thread "main"
> Design a3010_cpld has been optimized and fit into device XC95288XL-7-FG256.
> Completed process "Fit".
> 
> TIA
> 
> Geoff
> 
> 




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search