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Stefan Philipp wrote:
> Hi Folks,
>
> I am using the rocket IOs of the Xilinx Virtex II pro chips, with are
> working fine, but:
>
> While testing different frequencies in simulation, it seems, that if clock
> correction IDLEs
> are inserted in data between the SOP/EOP of a CRC checked data package,
> this results in an CRC error if clock corrections are needed during readout
> of
> the receiver elastic buffer, which is not documented in the rocket io user
> guide.
>
> This means, that there is no possibility to do any clock correction during
> the
> receive of crc-checked data and IDLEs could only be transmitted outside the
> SOP/EOP.
>
> Does anyone know, if this is generally true ?
Howdy Stefan,
"Idle mode [...] occurs during normal operation between frames"
(paraphrased from IEEE). I'm not sure why you'd insert idles in the
middle of a packet (between SOP or EOP), but if you are, don't do that :-)
Also, do you have CLK_COR_KEEP_IDLE set to true? If so, I could see how
that might confuse your CRC checker on the rx side.
Have fun,
Marc
Article: 68801Hello, does anybody has an idea, what kind of error pattern causes the plb_ddr controller to not correctly complete a read access to the ddr-sdram but instead indicating with the asserted PLB_SMErr that the access has failed? Many thanks for your replies. ChristianArticle: 68802
Dear Sir or Madam, I have some problems with implementing an SRAM controller. At http://mitglied.lycos.de/vazquez78 (link SRAM Controller) there are shown some plots. My question: As you can see the control sequence is WRITE READ NOP WRITE READ NOP ... (clock period : 11.11ns) When I go from WRITE to READ OE_n becomes active whereas WE_n becomes inactive at the same time. (Note: In simulation assertion / deassertion of control signals etc. is delayed by one clock cycle with regard to the state name ! ) The simulation shows that the read data are not correct. What does go wrong? Is the control sequence not right that is asserting OE_n and deasserting WE_n at the same time is not allowed? Thank you very much for your help. Kind regardsArticle: 68803
Dear All, Does OPB bus(V2.0) included in Xilinx EDK6.2 support burst transfer mode (fixed burst or variable burst)? If yes, how many data can it transfer(read/write) at one operation? HiroArticle: 68804
Ben, Not all FPGAs have a startup current: specifically we fixed that problem on Virtex II, Virtex II Pro, Virtex II Pro - X, and Spartan III. Now "A" stands for "amperes." We reviewed all of the TI material. Austin Ben Popoola wrote: > Hi, > SRAM FPGAs have a start-up current spike greater than 1A. > TI have a FPGA power supply document on their web site, that provides > various power supply circuits for FPGAs. > > Questions: > > (1) What is the minimum input current needed - from an off-the-shelf > power supply - for use with the TI circuits ? > > > > Cheers >Article: 68805
Joseph, The Coolrunner is a CPLD, and the 4000 was a FPGA: totally different architectures. Both are programmable logic devices, however. In general, the largest CPLD is still much smaller than the smallest FPGA in the capacity to do something (gates, flops, etc). CPLDs like Coolrunner have extremely low quiescent current and get used in handheld, or portabke devices often (like cellphones), whereas the FPGA has a larger quiescent current and is not usually found in a battery operated device, but rather its large number of gates are used in places like cellular base-stations. Austin Joseph Goldburg wrote: > What's the difference between say the Xilinx Coolrunner CPLD > and the Xilinx 4000 FPGA series. > > I noticed the coolrunner dev kit for $50 USD > > Please reply to this new group and wizard1@netspace.net.au > > Thanks in advance > > Joseph > >Article: 68806
Hi Maciej, Have you tried SignalTapping it? I've had similar problems, and found them pretty quickly by SignalTapping the Nios instruction and data pointer (IIRC, ic_address and dc_address) along with the Avalon signals going to/from external RAM. I think some of my problems ended up being stack corruption, I/O drive strength, and corruption with simultaneous multi-mastering. -- Pete Maciej Witaszek <nospam_mwitasze@elka.pw.edu.pl> wrote in message news:<c5s292$rvd$1@mamut.aster.pl>... > Hi, > I have the NIOS developer board with APEX FPGA.It has a SODIMM socket for > SDRAM module. I use a Micron MT8LSDT864HG-10ECS. > I make a Quartus project based on verilog/standard_32. I use nios_32 CPU. > I create a new memory configuration based on Micron datasheet and I put > it into class.ptf from altera_avalon_new_sdram_controller. > I write a simple program that can read and write memory maped in sdram. > This configuration has Location Vector, Program and Data memory set to > ext_ram which is SRAM. > But next I change Progam and Data memory to sdram. Program is compiled > correctly and srecord looks ok. I load it to board using nios-run. > When program starts it prints only "Return address is 0x00000000" and > returns to GERMS. The same situation is which all demo programs from > cpu_sdk and my own programs. > I will be very thankful for any help. > Best regards, > Maciej WitaszekArticle: 68807
I don't know of any specific examples, however it is simply a matter of
scheduling or arbiting access. The simplest set up is to provide access to
your external RAM at twice the required access frequency of either port. On
odd clocks, you allow access from one port, on even clocks access by the other
port (SDRAM requires something more complex of course). Each port will need
its own address logic and data registers to hold the outputs to memory and
later the inputs from memory so that every thing is presented when it is
needed.
khiltrop@gesytec.de wrote:
> Hi,
>
> ist there any vhdl example published for use of an external SRAM as a dual
> ported RAM?
>
> I imagine a state machine writing a data flow into the RAM,
> and a short FIFO for the read path out of the RAM,
> and some logic feeding the FIFO and handling the arbitration to the RAM.
> Maybe a write FIFO is also necessary.
>
> The RAM has 512k x 8.
>
> Thanks for any hint.
>
> Klaus Hiltrop
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68808Hi, I use 2 Altera FPGA : 1 Cyclone C12 (first in chain TDI/TDO) and 1 Cyclone C4 (second in chain TDI/TDO). So, in multi-device configuration the first device's nCE (C12) need to be tied low while its nCE0 pin is connected to nCE of the next device (C4) in the chain. In my scheme, there is an inversion !. There is the nCE pin of C4 tied low, while the nCE0 of C4 is connected to the nCE of the C12. So, I just can program the C4 FPGA, but I can't program the C12. Is someone could help me ?. Thanks. Bernard.Article: 68809
Slight correction. _Some_ SRAM FPGAs have a start-up current requirement, sometimes called Power-On Surge (POS) current. Check the data sheet for specific requirements. Spartan-3 FPGAs, as an example, have no POS current. You just need to supply at least the quiescent current. --------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/II/IIE FPGAs http://www.xilinx.com/spartan3 --------------------------------- Spartan-3: Make it Your ASIC "Ben Popoola" <b.popoola@ntlworld.com> wrote in message news:c5qsbp$4orlv$2@ID-207836.news.uni-berlin.de... > Hi, > SRAM FPGAs have a start-up current spike greater than 1A. > TI have a FPGA power supply document on their web site, that provides > various power supply circuits for FPGAs. > > Questions: > > (1) What is the minimum input current needed - from an off-the-shelf > power supply - for use with the TI circuits ? > > > > Cheers >Article: 68810
On Mon, 19 Apr 2004 09:10:38 -0000, hmurray@suespammers.org (Hal Murray) wrote:
>I'm interested in getting some analog signals out of and into a FPGA.
>The context is fine tuning the frequency of a crystal and measuring
>temperature and supply voltages.
> ....
>Pulse width modulation is the classic way to do low speed D/A from
>digital logic. For this purpose, I think I can do better by spreading
>the on bits over the whole time slot rather than clumping them all at
>the beginning. (Better low frequency noise.) For example, if I wanted
>slightly lower than 1/3 of full scale, I would send 1 on pulse, and 2
>or 3 off pulses, adjusting the ratio of 2 and 3 off pulses to get the
>best answer. What's the term for this approach? Is there a good
>writeup someplace?
This is called a Bit Rate Multiplier. First popularized in the
Fairchild 7497 which is a 6 bit implementation. TI also makes it:
http://focus.ti.com/docs/prod/folders/print/sn7497.html
As you can see on page 5 of the data sheet, it is trivially
cascadeable, and page 3 shows you all you need to do an FPGA
implementation.
Philip
Philip Freidin
Fliptronics
Article: 68811On Mon, 19 Apr 2004 14:36:06 +0200, Rene Tschaggelar <none@none.net> wrote: >>>I'm interested in getting some analog signals out of and into a FPGA. >>>The context is fine tuning the frequency of a crystal and measuring >>>temperature and supply voltages. >>>I don't need high speed. A 1 Hz response is overkill. I'm thinking of >>>16-20 bits of resolution. >> >> That's only a few microvolts... > >Yes. >A discrete solution with PWM or a DAC requires a comparator >being able to sense these microvolts. Considering that >the usual offset voltage is in the 2 digit microvolt region, >that won't be easy. Further a comparator needs overdrive. Dual-slope techniques do a pretty good job of turning all these effects (bias, overdrive...) into a near-constant offset that can easily be calibrated away. >It might be simpler to use a standard 20 or 24bit ADC, >eg LT2404, LT2424, LT2440 plus a few more. Also Analog Devices >has a few. They cost in the order of 7$US. True, but they do most grievously spoil the fun of the thought-experiment. >Getting them to produce between 16 and 20 bits is tricky enough. Indeed. It's very easy to get a rather small current to develop tens of microvolts along a rather short piece of PCB trace. And assembled PCBs are a rich source of thermoelectric voltages, so any temperature gradient across your PCB is likely to kill your accuracy. A nice big power-hungry FPGA in a nice small package, close to a whole lot of nice low-power analogue electronics... I suspect Hal Murray is somewhat aware of these issues. If not, he soon will be ;O) -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 68812
On Mon, 19 Apr 2004 16:40:04 GMT, Philip Freidin <philip@fliptronics.com> wrote: [re. distributing the pulses over a PWM cycle...] >This is called a Bit Rate Multiplier. I believe the BRM arrangement gives significantly worse low-frequency spuriae than the Bresenham (or delta-sigma, or pulse distributor, or gradient interpolator, or whatever you want to call it) arrangement that I described in an earlier response. However, I don't have a formal proof of that, so it's possible I'm totally wrong. Refutations welcome! -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 68813
Hi all, I had a question about Xilinx Virtex II FPGA's. In general is there an easy way to estimate the power increase by using clock enables vs. generating multiple internal clocks. Has anyone had any experience with coding a design both ways and looking at the power increase? I assume that there must be some power increase because the clock is now driving the input stage of all the Flops but internally it is gated by the enable. Thanks JonArticle: 68814
I think there is more to PLLs, DLLs and Digital Clock Managers (DCMs in Virtex/Spartan3) Fist the obvious: They can multiply the incoming frequency, so you do not need such a fast xtal. They can also divide the frequency.They canthus generate several internal frequencies from one xtal input. Now the more exciting: They can completely eliminate the on-chip clock delay, which is important on large chips. (They cannot eliminate clock skew. that is left to the chip dsigner to minimize) PLLs and also the Spartan3 DCM can reduce incoming jitter. Virtex2/Spartan3 DCMs can simultaneously multiply and divide the clock frequency by any integer up to 32, thus generating any one of a very large number of derived frequencies. DCMs can generate a phase-offset of n/256 of the clock period, where n can be any number up to 255. This allows phase manipulation down to 50 picosecond incrments. The applications of fixed or adaptive phase control are endless... Peter Alfke, Xilinx Applications > From: Rene Tschaggelar <none@none.net> > Newsgroups: comp.arch.fpga > Date: Sat, 17 Apr 2004 16:18:26 +0200 > Subject: Re: PLL and DLL > > Muthu wrote: > >> Hi, >> >> What is the need for PLL / DLL ? >> >> what kind of system requires this? When it is required? > > The newer families of FPGAs run on frequencies where > 1) it is hard to get oscillators > 2) you wouldn't want these oscillators on your board for EMC reasons > 3) the chips are too large to run on a single clock net > > PLLs allow to step the frequency up from a usual clock. > > Rene > -- > Ing.Buero R.Tschaggelar - http://www.ibrtses.com > & commercial newsgroups - http://www.talkto.netArticle: 68815
Austin Lesea wrote:
>
> Dave,
>
> If I have offended anyone, I apologize.
>
> However, I do not appreciate the mis-quote of this newsgroup in your
> slides at the presentation. Odd how my comment was distorted and then
> made it into the presentation. Makes me wonder.
>
> But, all of that aside, you will be happy to know that I no longer will
> comment on software, or software performance in this forum. We have
> someone who is now tasked with that subject. I am not an expert in that
> field (as I so amply demonstrated by opening my mouth and letting
> everyone know): all I can do is repeat what I hear from our customers,
> and our own engineers. They can do a much better job.
>
> The questions I posed are legit, however. As well as comparing 90nm to
> 90nm ('Our latest announced yet to be shipped chip is better than your 2
> year 130nm technology chip...')
>
> I will continue to monitor the group for the questions that I can shed
> some light on: signal integrity, IO modeling, IC Design, etc.
>
> Now you have a (mis) quote from me in your slides on a subject that I
> have publicly stated I am not an expert in.
I am coming late to the party as usual. I would like to say that I
perfer not to see marketing espoused here, pure or otherwise. Marketing
is of little value and is counter productive when it gets in the way of
seeing what the real issues and facts are. It also tends to create a
lot of spurious responses that clutter up the group. That aside, I am
pleased at Xilinx's approach to this newsgroup and the assignment of
specific representatives to deal with specific areas of expertise.
It seems that many companies have historically considered the newsgroups
a place to either market, or nothing but trouble and have stayed away
from posting any "official" comments. I am pleased to see both Xilinx
and Altera taking this forum seriously and addressing it at a business
level rather than just unofficially.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 68816SD, 1. To respond to your concerns, our benchmarking team ran a second set of experiments to compare Stratix to Virtex-II Pro in which the circuits are given I/O constraints in addition to Fmax contraints. The results showed a decrease in the absolute Fmax produced for both families of between 5% to 6%, but a negligible change (less than 0.5%) in the relative comparison. So, our results as presented in the Net Seminar remain valid both with a without I/O constraints. 2. Design age varies greatly though in general the larger designs tend to be newer than the smaller designs. Most of the large designs (>40K LEs) are less than 1 year old. Most of the small & mid density designs are 1-3 years old. To the extent that we look for data points that are "out-lying" and fix them (as they are often representive of broader issues), there is some tuning of our software around these designs. I think this likely contributes to the discrepancy in results, though I would speculate that it contributes much less than the methodology differences. Dave Greenfield Altera Product Marketing nofpgaspam@yahoo.com (SD) wrote in message news:<27eca41.0404131035.7a9a355f@posting.google.com>... > Dave, > > Thanks for your response. If I may address some of these points one > last time... > > 1. I understand that you don't have constraints for all these designs, > but for the designs you ran the benchmarks on, wouldn't it be more > thorough to include the I/O timing for the critical path as well? > Since you already have the data, it shouldn't be much more effort. > Would it be possible to at least show an average Tsu/Tco change on the > critical paths for the benchmark designs? I'm not disputing your > claims of a 5% difference, but without that data, I'm only getting > numbers for the middle slice of the path. > > 2. Could you provide the approximate average age of these designs? > Also could you comment on whether you think some of the discrepancy in > the benchmarking results is due to tool/architecture tuning to these > designs? If the designs were used during Altera's tool/architecture > development, then they should (and hopefully would) favor an Altera > implementation. > > 3. Sounds reasonable enough :) > > SD > >Article: 68817
Hi Jon, You could try using the Xilinx Power Estimator tool. I'm not sure that you're right that several separate clocks are better than a clock enabled design. Here's my reasoning. A major part of the power consumption is the energy used when a flip-flop changes state, so this is the same for both designs. So, the only difference between the two methods is the difference in power to charge and discharge the global clock networks for the former case, and the power to charge and discharge the clock enable signals in the latter case. I doubt that there's much difference. Why not try the power estimator and report back? cheers, Syms. "Jon" <jon8spam@yahoo.com> wrote in message news:d68b01eb.0404191107.7fd1adf4@posting.google.com... > Hi all, > I had a question about Xilinx Virtex II FPGA's. In general is there > an easy way to estimate the power increase by using clock enables vs. > generating multiple internal clocks. Has anyone had any experience > with coding a design both ways and looking at the power increase? I > assume that there must be some power increase because the clock is now > driving the input stage of all the Flops but internally it is gated by > the enable. > > Thanks > > JonArticle: 68818
Symon wrote:
>
> Hi Jon,
> You could try using the Xilinx Power Estimator tool. I'm not sure that
> you're right that several separate clocks are better than a clock enabled
> design. Here's my reasoning.
> A major part of the power consumption is the energy used when a flip-flop
> changes state, so this is the same for both designs. So, the only difference
> between the two methods is the difference in power to charge and discharge
> the global clock networks for the former case, and the power to charge and
> discharge the clock enable signals in the latter case. I doubt that there's
> much difference.
> Why not try the power estimator and report back?
> cheers, Syms.
Actually, it may be the other way around. Driving the global nets is
likely to take more power than driving the inputs of the FFs. By having
multiple clocks, multiple sets of clock lines will require more power
vs. the extra power of driving the FF inputs. I guess it may depend on
the relative speeds of the clocks.
Which will take more power, a x N x F1 or (b + a x N) x F2 where a is
the power coefficient for a FF input only, N is the number of FFs
enabled at the lower speed and F1 is the high speed clock frequency; b
is the power coefficient for driving a clock line and F2 is the low
speed clock? Another way to express this is
A F2
- * N <?> -------
B F1 - F2
Or the breakeven point would be
B * F2
N = --------------
A * (F1 - F2)
If N is greater than this, the enabled FFs will use more power. If N is
less than this, the enabled FFs will use less power.
Obviously it is not a simple choice, but depends on several aspects of
your design and the FPGA. The design will even affect A and B somewhat
since FFs in more columns will require more column lines to be driven.
I am not sure the calculator will consider all these effects. But the
timing analyzer will. Too bad they can't combine the timing analysis
with power estimation. I think their is a lot more design info
available in the timing analyzer that could be used to calculate power
consumption.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 68819On Sat, 17 Apr 2004 21:58:26 +0200, Maciej Witaszek <nospam_mwitasze@elka.pw.edu.pl> napisal: >But next I change Progam and Data memory to sdram. Program is compiled >correctly and srecord looks ok. I load it to board using nios-run. >When program starts it prints only "Return address is 0x00000000" and >returns to GERMS. The same situation is which all demo programs from I got SODIMM from laptop and compiled some simple design (only with UART & lcd). Worked from the first time. Board was the one with Apex20KE, Have you tried "minimal_sdram_32" from examples directory? PS: To juz taki czas, ze rodacy szukaja pomocy za granica? :-) -- JerryArticle: 68820
When digitally mixing an IF down to baseband, one is left with a spectrum that consists of the baseband (Fif - Fmix = 0Hz) and an image (Fif + Fmix). If the IF is greater than the Nyquist freq, the image will wrap back into the first Nyquist zone (0 to Fn). Normally the next step in demodulation is decimation, which consists of lowpass filtering out the image (often with CICs) and then dropping some of the resultant samples to get a lower sample rate. Is there a method by which an image-reject mixer could mix the IF down to baseband while simultaneously cancelling the image? If so, it seems like there would be no filtering required for decimation, which would consist entirely of throwing samples out. Then it also seems that the mixer itself could run at the slower decimated rate. Or is that all just another way of saying "undersampling"? -KevinArticle: 68821
"Peter Seng" <NOSPAM@seng.de> wrote in message news:c5vttk$4df$1@online.de... > Standard base adresses are 3BCh, 378h, 278h (named LPT1-LPT3, in this > order), but 3BCh is the only not able to be set to EPP or ECP mode. Ranges > see above. EPP and ECP may use a secondary adress range at baseadress + > 400h. Hi Peter, apparantely I can not use 03BC at all. It is used for Pentium II to AGP Bridge controller. I can not modified its IO range at all and if I disable it, my computer run at 640x480. > The hardware does not look as it is Xilinx compatible, different drivers and > missing capacitors.... On our systems we also use different drivers and no > capacitors at all - but we do it inside an FPGA - and we also had problems > first - so we included digital filtering (instead of capacitors) and it > worked afterwards. > -> Try to built or lend a Xilinx download cable (Parallel cable III, > schematic on the net, see Xilinx). If it works use this. > or > -> try to connect a 1nF capacitor between TCK and GND of Your board. Not > shure if it works.... > and/or > -> ask digilent what to do, describe your problems I will try the capacitor trick and just email digilent. Let's see how it works and I will report back. Thanks for your time! HendraArticle: 68822
Kevin Neilson wrote: > When digitally mixing an IF down to baseband, one is left with a spectrum > that consists of the baseband (Fif - Fmix = 0Hz) and an image (Fif + Fmix). > If the IF is greater than the Nyquist freq, the image will wrap back into > the first Nyquist zone (0 to Fn). > > Normally the next step in demodulation is decimation, which consists of > lowpass filtering out the image (often with CICs) and then dropping some of > the resultant samples to get a lower sample rate. > > Is there a method by which an image-reject mixer could mix the IF down to > baseband while simultaneously cancelling the image? If so, it seems like > there would be no filtering required for decimation, which would consist > entirely of throwing samples out. Then it also seems that the mixer itself > could run at the slower decimated rate. > > Or is that all just another way of saying "undersampling"? > -Kevin Look at sinrle-sidebamd receiver design. It's all there for you. Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 68823
rickman wrote: > Symon wrote: > >>Hi Jon, >>You could try using the Xilinx Power Estimator tool. I'm not sure that >>you're right that several separate clocks are better than a clock enabled >>design. Here's my reasoning. >>A major part of the power consumption is the energy used when a flip-flop >>changes state, so this is the same for both designs. So, the only difference >>between the two methods is the difference in power to charge and discharge >>the global clock networks for the former case, and the power to charge and >>discharge the clock enable signals in the latter case. I doubt that there's >>much difference. >>Why not try the power estimator and report back? >>cheers, Syms. > > > Actually, it may be the other way around. Driving the global nets is > likely to take more power than driving the inputs of the FFs. By having > multiple clocks, multiple sets of clock lines will require more power > vs. the extra power of driving the FF inputs. I guess it may depend on > the relative speeds of the clocks. > > Which will take more power, a x N x F1 or (b + a x N) x F2 where a is > the power coefficient for a FF input only, N is the number of FFs > enabled at the lower speed and F1 is the high speed clock frequency; b > is the power coefficient for driving a clock line and F2 is the low > speed clock? Another way to express this is > > A F2 > - * N <?> ------- > B F1 - F2 > > Or the breakeven point would be > > B * F2 > N = -------------- > A * (F1 - F2) > > If N is greater than this, the enabled FFs will use more power. If N is > less than this, the enabled FFs will use less power. > > Obviously it is not a simple choice, but depends on several aspects of > your design and the FPGA. The design will even affect A and B somewhat > since FFs in more columns will require more column lines to be driven. > I am not sure the calculator will consider all these effects. But the > timing analyzer will. Too bad they can't combine the timing analysis > with power estimation. I think their is a lot more design info > available in the timing analyzer that could be used to calculate power > consumption. Expanding on this, there was data posted not long ago here, about the relative power of a 'true clock net', vs a signal used as clock. ISTR someone from Altera also mentioned a tool /floorplan approach, that trys to pack logic onto physical clock branches/stubs, and so avoids driving un-used clock lines. Would suit a stable design, and one where the saving was worth the effort It is also good to see IC vendors starting to quote Clock power figures for Enabled and Disabled counters - that gives a feel for ratios of .CLK and .Q power capacitances. They could easily add this to the power estimator/post route analyser. Probably just needs customer demand.... :) -jgArticle: 68824
Clock Enables vs multiple clocks is a trade-off. If you are not concerned about power, then a single low0skew global clock and a "sloppier" network of CEs requires the least amount of thinking. Multiple derived clocks mean that you have to think about clock transfer from one clock domain to the next, you may have to use multiple PLL/DLL/DCMs. In the extreme case, the use of CE will always save power. Think of a design with 10 flip-flops clocked at 200 MHs, the remaining 500 flip-flops clocked at 1 MHz. It sure would reduce power when the fast clock is only routed to the 10 flip-flops and the remaining 500 get that a slow clock (vs 200 MHz all over the chip, plus a1 MHz CE signal to most flip-flops) Peter Alfke > From: "Symon" <symon_brewer@hotmail.com> > Newsgroups: comp.arch.fpga > Date: Mon, 19 Apr 2004 13:39:48 -0700 > Subject: Re: Clock Enables and Power > > Hi Jon, > You could try using the Xilinx Power Estimator tool. I'm not sure that > you're right that several separate clocks are better than a clock enabled > design. Here's my reasoning. > A major part of the power consumption is the energy used when a flip-flop > changes state, so this is the same for both designs. So, the only difference > between the two methods is the difference in power to charge and discharge > the global clock networks for the former case, and the power to charge and > discharge the clock enable signals in the latter case. I doubt that there's > much difference. > Why not try the power estimator and report back? > cheers, Syms. > > > "Jon" <jon8spam@yahoo.com> wrote in message > news:d68b01eb.0404191107.7fd1adf4@posting.google.com... >> Hi all, >> I had a question about Xilinx Virtex II FPGA's. In general is there >> an easy way to estimate the power increase by using clock enables vs. >> generating multiple internal clocks. Has anyone had any experience >> with coding a design both ways and looking at the power increase? I >> assume that there must be some power increase because the clock is now >> driving the input stage of all the Flops but internally it is gated by >> the enable. >> >> Thanks >> >> Jon > >
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