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Yes, you can. Peter Alfke Simone Winkler wrote: > > Thank you! And how can i realize a 32-bit wide FIFO? At the moment I use the > Xilinx-FIFO-designs for Spartan-II. They use block ram - but the biggest > module i can get is 16bit-wide. Is it possible to use 2 instances of > ramb4_s16_s16 and drive each instance with the same clock, enable signals > and so on? > > Thank you, > > Simone > > "Mike Lewis" <someone@microsoft.com> schrieb im Newsbeitrag > news:4P-dnWSWl-I__kqi4p2dnA@magma.ca... > : If you make the FIFO 32 bits wide on both ports. > : Then alternate between writing to the lower > : and upper half of the 32 bit datapath on the > : "16 bit" side of the fifo you have effectively > : converted from 16 to 32 bits when travelling through the > : FIFO.Article: 64001
toby wrote: > I was trying to use a macro 'expression' -- > > `define MAXIMUM2( x, y ) ( ((x)>(y))?(x):(y) ) // return greater value > > parameter A_W = 10; // Abus width (#bits) > parameter B_W = 12; // Bbus width (#bits) > parameter C_W = `MAXIMUM2( A_W, B_W ); // Cbus: intersect(A_W, B_W) > > This works in NC-Verilog 4.0, Modelsim 5.6, Design Compiler 2003.06, and > Ambit/PKS 5.0. Xilinx ISE 6.1i's "XST" doesn't like it. Overall, so > far so good! > > Then I tried to get more clever ... > > `define MAXIMUM3(x,y,z ) ( (`MAXIMUM2(x,y)>z) ? (`MAXIMUM2(x,y)):(z) ) > > This barfs on most of the above... I just tested that `define statement in DC_shell 2003.06-SP1 -- it compiles just fine. I also tried `define MAXIMUM3(x,y,z) `MAXIMUM2(`MAXIMUM2(x,y),z)) again...DC_shell 2003.06-SP1 compiles that just fine.Article: 64002
I'm not sure if you can use the canned FIFOs from coregen. What you really need is a FIFO with byte write enables. You might have to design your own FIFO with this feature. Mike "Simone Winkler" <simone.winkler@gmx.at> wrote in message news:1071155783.567185@news.liwest.at... > Thank you! And how can i realize a 32-bit wide FIFO? At the moment I use the > Xilinx-FIFO-designs for Spartan-II. They use block ram - but the biggest > module i can get is 16bit-wide. Is it possible to use 2 instances of > ramb4_s16_s16 and drive each instance with the same clock, enable signals > and so on? > > Thank you, > > Simone > > > "Mike Lewis" <someone@microsoft.com> schrieb im Newsbeitrag > news:4P-dnWSWl-I__kqi4p2dnA@magma.ca... > : If you make the FIFO 32 bits wide on both ports. > : Then alternate between writing to the lower > : and upper half of the 32 bit datapath on the > : "16 bit" side of the fifo you have effectively > : converted from 16 to 32 bits when travelling through the > : FIFO. >Article: 64003
The problem here is that Simone never explained what she is really out to do. Is there really a need for a FIFO of significant depth, or can one just use a few registers ? Where do the 32 bit address and the 16-bit data come from, and since the other 16 data bits are don't care, why are they not just ignored ? As long as we are being kept in the dark about the real intention, any suggested "solution" is meaningless. Sorry, Simone, for being so blunt. Peter Alfke ============================= Mike Lewis wrote: > > I'm not sure if you can use the canned FIFOs from coregen. > What you really need is a FIFO with byte write enables. > You might have to design your own FIFO with this feature. > > Mike > > "Simone Winkler" <simone.winkler@gmx.at> wrote in message > news:1071155783.567185@news.liwest.at... > > Thank you! And how can i realize a 32-bit wide FIFO? At the moment I use > the > > Xilinx-FIFO-designs for Spartan-II. They use block ram - but the biggest > > module i can get is 16bit-wide. Is it possible to use 2 instances of > > ramb4_s16_s16 and drive each instance with the same clock, enable signals > > and so on? > > > > Thank you, > > > > Simone > > > > > > "Mike Lewis" <someone@microsoft.com> schrieb im Newsbeitrag > > news:4P-dnWSWl-I__kqi4p2dnA@magma.ca... > > : If you make the FIFO 32 bits wide on both ports. > > : Then alternate between writing to the lower > > : and upper half of the 32 bit datapath on the > > : "16 bit" side of the fifo you have effectively > > : converted from 16 to 32 bits when travelling through the > > : FIFO. > >Article: 64005
Frank wrote: > What I want to do is > the following: When running the application, I want to be able to return to > the bootloader in order to download a new application. But just jumping to > the start address of the bootloader is (in my opinion) not enough. The > kernel still keeps running, I guess. How can I make this possible?? Is there > a way to stop the kernel? Or another way to replace the application with a > new one (by using the bootloader). Or is described behaviour not possible > when using the kernel?! > Here's one way to do this: Bootloader0: standalone executable that loads xilkernel.elf and app1.elf and app2.elf, and then jumps to xilkernel's start address xilkernel.elf: xilkernel executable, transfers control to app1.elf and when it exits, transfers control to app2.elf (process_table has app1.elf at a higher priority than app2.elf) app1.elf: does something special, then exits app2.elf: does something else special If you want to reuse the memory of app1 for app2, recompile a slightly modified bootloader as a xilkernel-based elf file (just like app1.elf) with a different start address and load it along with app1.elf instead of app2.elf as above. Then when app1.elf exits, the modified bootloader is invoked by the kernel to load app2.elf into the same memory as app1.elf and create a new process for app2.elf (using process_create()). -- MohanArticle: 64006
I've come across plenty of designs in the older devices that go between clock
domains without concern about skew as well. It doesn't make it right. Fact is,
the average design that has several layers of logic between flip-flops is going
to be fine, as there is enough delay in the LUTs and routing to outweigh the
skew. It is in the carefully done (and occasional accidental case) where you
have a flip-flop in one domain connected to the direct in input to the flip-flop
in the other domain (skipping the LUT) that is the potential problem. If you
have a LUT in between, you'll need to have a good bit of jitter on the input in
order to have enough skew to break the design, at least in lab conditions. The
cases where I had problems were designs with the arrangement as described above,
that had also been floorplanned. Trouble is, there is no minimum propagation
spec, so it is difficult to determine how much margin a given number of LUTs or
routing delay buys you. The safe design takes very little extra logic, so it is
to me a no-brainer to put it in to avoid the situation altogether.
jean-francois hasson wrote:
> Hi,
>
> I agree with the fact that crossing clock domains with special care is still
> possible even with higher clock frequencies. However, I believe some designs
> involving the Virtex II Pro cross clock boundaries (300 MHz to 100 MHz and
> the opposite) without concern about skew. Does that mean that the skew is
> negligible compared to propagation delay by construction of the Virtex II
> Pro ? Would it be the same for Virtex II ?
>
> JF Hasson
>
> "Ray Andraka" <ray@andraka.com> a écrit dans le message de news:
> 3FD73863.BE23FD47@andraka.com...
> > The input_jitter constraint does not factor in jitter caused skew between
> clock
> > nets. It only decreases the available cycle time in your period
> constraint to
> > account for cycle to cycle variations (jitter) in the clock for that net.
> I
> > don't know if the VirtexII suffers to the same degree or not (and I
> haven't
> > chanced it) from DLL output spreading due to input jitter.
> >
> > Safe crossing between related clock domains in not overly difficult, and
> is
> > still possible to do with the faster clock speeds. The only work around
> other
> > than deliberate safe crossing design is to guarantee the delay between two
> > flip-flops on different but related clocks is greater than the maximum
> possible
> > clock skew between those flip-flops, which is to say you have to depend on
> LUTs
> > and routing to delay the data signal. If speed is critical, then adding
> the
> > delays can hurt you more than doing a proper safe crossing.
> >
> > John_H wrote:
> >
> > > The new version of Xilinx tools (6.1i and on) appear to be doing a more
> > > complete job on this analysis. The biggest problem earlier was the
> effect
> > > of input jitter on the DCM that couldn't be accounted for. Uneven
> loading
> > > on the clock nets was also an issue. Now the tools allow an
> INPUT_JITTER
> > > constraint to go along with your specified period and duty cycle. Also
> with
> > > the automated elimination of hold-time violations, it looks like the
> tools
> > > are filling in for the corner cases of design as long as we, the
> designers,
> > > give the tool the right info.
> > >
> > > I'm now happier making the transition between same-edge clock domains
> > > without special treatment though I know where to look first if my design
> > > starts to misbehave.
> > >
> > > "jean-francois hasson" <jfhasson@club-internet.fr> wrote in message
> > > news:3fd377da$0$6982$7a628cd7@news.club-internet.fr...
> > > > Hi,
> > > >
> > > > I remember reading a few lines on this newsgroup about the fact that a
> DLL
> > > > in a Virtex might not be able to handle a negligible skew between two
> > > > outputs (clk0 and clk2X for instance) in some situations like a heavy
> > > > loading difference between the two clock trees with maybe an important
> > > (but
> > > > in the datasheet spec ?) jitter on the input clock. Ever since I read
> this
> > > I
> > > > did not consider I could change from one clock domain to the other
> without
> > > > special care. Has anyone something new concerning these potential
> cases ?
> > > If
> > > > there is still a possibility does it apply only to Virtex or also to
> > > Virtex
> > > > II ? The reason I ask is that the designs coming up are running faster
> and
> > > > faster making it more difficult to consider changing clock domains
> with
> > > some
> > > > extra precaution.
> > > > Thanks,
> > > >
> > > > JF
> > > >
> > > >
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 64007Hi, does anyone know if the Xilinx 6 tools work on Red Hat Enterprise or Fedora? I see this note on the Xilinx web site: RedHat 7.3 and 8.0 are supported for the 6.1i Release. RedHat 9.0 supports the Linux environment variable "LD_ASSUME_KERNEL=2.4.1" which allows version 9.0 to run applications that are compatible with previous versions of RedHat. This environment variable will allow ISE 6.1i to run, but it is not supported or tested by Xilinx. Thanks, GusArticle: 64009
On Thu, 11 Dec 2003 09:39:14 +0100, Jo Pletinckx <jo_pletinckx@yahoo.com> wrote: >Hi all, > >I have a 4-FPGA design with nearly identical VHDL source code, so in >order to speed development, I started using the command-line tools >instead of the Xilinx IDE (which basically also runs the cmd line tools >from the shell). I've encountered strange behavior since: > >1. MPPR and PAR with the same cost table generate different results on >my PC (w2k, sp3, running 5.2i sp3). This is not such a big issue, as I >wrote my own batch to do an MPPR by calling PAR with different cost >tables values. > >2. PAR run from the ISE and PAR from the command line generate different >results, with identical options and input files (I actually used the >.cmd_log file to write my own batch file). More specifically, ISE >returns result A, cmd line returns B. >Strangely enough, I ran the cmdline tools on another PC, with identical >settings, and this returned result A as well. > >I browsed through the Xilinx answer database for clues, and I found no. >17134, describing a similar problem. A workaround is presented, but when >I implement it (it involves settings the PL_NODIROPT env. variable to >1), I get yet another result, C. > >Has anyone encountered this problem before and was able to solve it? I've seen plenty of cases in which different PCs with supposedly identical installations of Xilinx software produce different FPGA images from identical source with identical options. I've also seen examples of MPPR and SPPR producing different results with the same cost table. It sounds like you have just one PC, so there must be some difference in the input to PAR (for your point #2), perhaps an environment variable or command line option. In most cases, the difference doesn't seem to matter. We did find some examples of routes from one PC working while supposedly identical routes from another PC didn't work. The solution was to test everything in the lab, and avoid reusing the PC configurations that are known to produce bad results. (IIRC this was all reported to Xilinx some time ago. I think it was happening with 4.x software.) Regards, Allan.Article: 64010
I came across a small surplus of Altera MAX 7000Es. On Altera's website I found information about how to program the Altera MAX 7000S. Is programming the MAX 7000E the same or does it require special equipment? Thanks, Derek SimmonsArticle: 64011
Jimbo wrote: > > Does anyone know why Xilinx' socket function library, xilsock.h, does > not contain a xilsock_connect() function? > > Also, do you know how xilsock_accept() works? It appears to be > non-blocking by default. Is this the case? > XilNet was developed to fit into smaller devices and hence we have restrictions. Currently, we have only server support functionalities in XilNet. Since xilsock_connect is more of a client functionality, this is not supported. As of xilsock_accept(), the way it works is by polling the ethernet driver for packets. If a request for a new connection is received, then a reply is sent to the client (TCP handshaking happens) and a flag XILSOCK_NEW_CONN is returned to the application to indicate that a new connection is received. The flags returned to the application from XilNet is documented in xilsock.h. If you want something that is not supported in XilNet, there is an open source project called lwip that has a full standalone TCP/IP stack for processors from Xilinx (PowerPC and MicroBlaze). Finally, there are various operating systems that support these processors and provide TCP/IP implementations - see http://www.xilinx.com/ise/embedded/epartners/listing.htm for more info on OS support. -- MohanArticle: 64012
On 8 Dec 2003 06:54:50 -0800, dathathreya.bhat@wipro.com (Datha) wrote: >Can somebody help me in understanding few USB related queries? > >What is USB host controller? >What is USB device controller? >What is USB OTG controller? > >What are the different siuations which will make USB to generate interrupt? > >What are 'End points'? > >What is the meaning of 'OTG tranceiver in bi-directional mode'? > >What is the meaning of 'Non-OTG tranceiver in uni-directional mode'? > >What is transeiver? > >Thanx in advance >-datha This should help: http://www.lvr.com/usb.htm Philip Freidin FliptronicsArticle: 64013
When you get the EDK, you can start getting a better feel of the entire FPGA Processor System. Without EDK, you are pretty much handicapped in getting to use the PowerPC in Virtex2Pro. Not only do you have to get EDK, I think one would also require a copy of the formal Xilinx training notes on Embedded development, to get started using embedded development quicker. The tools are not hard to understand or use, its just the time factor to gather "How to do things" is pretty cumbersome. The EDK comes with a trial version of VS Works OS I think, but I am thinking of using BSD unix. hope this helps. Cheer Anup MS wrote: > Has anyone used this embedded PowerPC in the Virtex2 Pros? > > We are working on a project where we will be pushing some functions > into the processor on the FPGA. Basically- it will handle all the > data path exceptions. > > I am interested to hear how people interfaced the data to the > processor (DPRAM, DMA, registers, etc) and especially interested to > hear how they (or whether they) tested everything. > > What sort of OS did you run? How hard was it to get everything to > work together- to debug? How is the EDK toolset? Did you take formal > training? > > We order a development board and will be banging on that soon. > > Thanks, > WP --Article: 64014
I believe its not an integer divide routine but a binary one.. if it was.. they would have the same latency as the Xilinx pipelined version. divide by 2 is of course, easy because that's native to binary. Simon "Valentino" <vlentn@yahoo.it> wrote in message news:79780d60.0312101004.8a90d74@posting.google.com... > Hi, > > I'm developing a digital signal processing algorithm on Xilinx Virtex2 > FPGA. I use the Xilinx ISE 6.1i developing environment. > I'm trying to use the "/" (divisor) operator included in the ieee > "numeric_std" library but the systesis produces the following error > message: > > "ERROR:Xst:769 - C:/test/div.vhd line 35: Operator <INVALID OPERATOR> > must have constant operands or first operand must be power of 2" > > Does the ieee "/" operator is really defined for constant or power of > 2 operators only? > > How can I evaluate Q=NUM/DEN, where NUM and DEN are not constant, not > of power 2 and of type SIGNED ? > > I already tested the Xilinx "Pipelined Divider V2.0" core but I can't > use it because of it's very high latency. > > Thanks. > > ------------------------------ > > It follows the source code that generates the error message: > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_SIGNED.ALL; > use IEEE.NUMERIC_STD.ALL; > > > entity div is Port ( > clk: in std_logic; > NUM: in SIGNED(15 downto 0); > DEN: in SIGNED(15 downto 0); > Q: out SIGNED(15 downto 0) ); > end div; > > > architecture Behavioral of div is > begin > > process (clk, NUM, DEN) > begin > if clk='1' and clk'event then > Q <= NUM/DEN; > end if; > end process; > > end Behavioral;Article: 64015
Allan Herriman wrote: > On Thu, 11 Dec 2003 09:39:14 +0100, Jo Pletinckx > <jo_pletinckx@yahoo.com> wrote: > > >>Hi all, >> >>I have a 4-FPGA design with nearly identical VHDL source code, so in >>order to speed development, I started using the command-line tools >>instead of the Xilinx IDE (which basically also runs the cmd line tools > >>from the shell). I've encountered strange behavior since: > >>1. MPPR and PAR with the same cost table generate different results on >>my PC (w2k, sp3, running 5.2i sp3). This is not such a big issue, as I >>wrote my own batch to do an MPPR by calling PAR with different cost >>tables values. >> >>2. PAR run from the ISE and PAR from the command line generate different >>results, with identical options and input files (I actually used the >>.cmd_log file to write my own batch file). More specifically, ISE >>returns result A, cmd line returns B. >>Strangely enough, I ran the cmdline tools on another PC, with identical >>settings, and this returned result A as well. >> >>I browsed through the Xilinx answer database for clues, and I found no. >>17134, describing a similar problem. A workaround is presented, but when >>I implement it (it involves settings the PL_NODIROPT env. variable to >>1), I get yet another result, C. >> >>Has anyone encountered this problem before and was able to solve it? > > > I've seen plenty of cases in which different PCs with supposedly > identical installations of Xilinx software produce different FPGA > images from identical source with identical options. > > I've also seen examples of MPPR and SPPR producing different results > with the same cost table. > > It sounds like you have just one PC, so there must be some difference > in the input to PAR (for your point #2), perhaps an environment > variable or command line option. > > > In most cases, the difference doesn't seem to matter. We did find > some examples of routes from one PC working while supposedly identical > routes from another PC didn't work. > > The solution was to test everything in the lab, and avoid reusing the > PC configurations that are known to produce bad results. > > (IIRC this was all reported to Xilinx some time ago. I think it was > happening with 4.x software.) > > Regards, > Allan. I suspect the GUI will pass other unknown settings to the PAR tool, as I use identical options and identical input files for both the GUI based and cmd line based PAR run. I've opened a case with Xilinx to discuss this further. UPDATE: I set the environment variable PL_NODIROPT=1 on all PCs and now the cmdline PAR on PC_A, PC_B as well as the GUI on PC_A return identical results. Strangely enough, this result is different from the previous ones. (i.e. I now have 3 different end results) Best regards, JoArticle: 64017
> Here's one way to do this: > Bootloader0: standalone executable that loads xilkernel.elf and app1.elf and app2.elf, and then jumps to xilkernel's start address > xilkernel.elf: xilkernel executable, transfers control to app1.elf and when it exits, transfers control to app2.elf (process_table has app1.elf at a higher priority than app2.elf) > app1.elf: does something special, then exits > app2.elf: does something else special > > If you want to reuse the memory of app1 for app2, recompile a slightly modified bootloader as a xilkernel-based elf file (just like app1.elf) with a different start address and load it along with > app1.elf instead of app2.elf as above. Then when app1.elf exits, the modified bootloader is invoked by the kernel to load app2.elf into the same memory as app1.elf and create a new process for > app2.elf (using process_create()). > What do you exactly mean with "tranfer control"? In your described solution both applications (app1.elf and app2.elf) are running at the same time or is app2.elf not getting any time to run because app1.elf has a higher priority? I was assuming that both processes would run but the application with the highest priority was getting more time. But if I understand your solution, the process with the highest priority is getting ALL the time?! Another point: what if I want to download multiple times a new application? Do I have to define a lot of processes and each of them with a priority that is lower then the previous? app1, address x, priority highest app2, address y, priority higher app3, address z, priority high At startup (when jumping to the kernel) app1 is executed, then I can download app2 at address y and exit app1. Now app2 is running. When downloading again a new application it has to be downloaded to address z and app2 has to be exited. Is this what you mean? If so, how can I download by use of the bootloader? Just jump from app1 (or from app2 the second time downloading) to the bootloader (which is in bram) and exit after downloading? Does the kernel not complain about this?! About your suggestion of reusing the memory. Do you mean to have two bootloaders, one in bram which downloads the kernel, application and a second bootloader? The second bootloader is then in external sdram and has lower priority as the application. When exiting the application, this second bootloader is executed. This second bootloader places the new application into sdram and executes a process_create?! If it does, it has to be a process create with a higher priority of itselfs. Is the bootloader automatically stopped by the kernel in that case?! Maybe there is a third way to download a new application. I was reading in the docs and saw that if you have one application, you can make an executable which contains the kernel stuff and the application. In the application the user needs to use the system calls with a sys_ prefix (sys_thread_create for example). In my situation I have only one application that is running, so perhaps it's a good solution. Now I can download the complete application (user code + kernel stuff) to sdram and jump to it. When I want to download a new application, I just jump to the bootloader in bram and download a new complete application (at the same start address as the previous one) and jump to it. Is this possible in the described way? What to do with the xilkernel.elf file (just leave it where it is and don't use it, I guess)? Do I need some compiler/linker options to get a complete application or just using the system calls with sys_ prefix is enough? TIA, FrankArticle: 64018
Is it possible to use the opb sdram controller with a 32-bits opb bus to a microblaze one side and a 16-bits sdram to the other side? What if I do a 32-bits access to sdram. Will the controller convert this automatically in two 16-bits cycles? The datasheet of the opb sdram controller says: "Since the sdram will always be accessed to provide data the width of the OPB bus, ...". So it looks like it will convert a 32-bits access to two 16-bits accesses, but can anyone acknowledge this? FrankArticle: 64019
Dear All, I have a following question about Xilinx Spartan-IIE configuration related pins. Do TDO and CCLK pin have internal pullup resistor attached to it during configuration? Please note that the term"configuration" implies all of configuration modes (JTAG, Master/Slave serial and SelectMAP) Sincerely, hiroArticle: 64020
Hello, > I plan to buy digilent combo board DIO2 combo. Does anybody know if a > download cable will be included in the package? also, do they provide > the software like foundation or webpack? Yes, the cable is included. But you need dowload de webpack from xilinx's site. > I plan to implement some work of dsp, like FFT, FILTER. Hope this > spartan II (200k gates) FPGA on this board helps. Has anybody tried > that on digilent's board either? I'm doing a OFDM in my D2-DIO2 combo, that have a IFFT. I'm using the FFT from www.opencores.org, because de FFT from Coregen don't work properly in Spartan-2.Article: 64021
Hello, I am using a Virtex2 device with a DSP core, written in VHDL and a Microblaze. The Microblaze has as peripherals a UART, SPI, GPIO, interrupt controller (INTC), external memory controller (EMC), instruction cache , user IP-IF and a Watchdog/Timer (WDT) core. All peripherals are connected via the OPB to the Microblaze. Now, the problem. The interrupt controller has 5 input lines (priority 1 to 5). When the interrupt handler on the microblaze is called it disables all lower priority interrups by clearing the IER (interrupt enable register) in the INTC. This is for my understanding the way to realize interrupts with different priorities, to allow higher priority interrupts to interrupt lower priority interrupts. That works. But the great problem is that all lower priority interrupts which occure during a higher priority interrupt is serviced (low prio interrupt enable bit is cleared in the INTC) will be discarded by the INTC, thus not serviced, after the high prio interrupt is finished. I think there is a "bug" in the INTC, because my interpretation of the docu is that the status register (ISR) will register all incoming interrupts. All my communiction (UART / SPI) is interrupt driver. And therefore losing interrupts leads to a broken communiction, which is very bad :(. If the watchdog timer interrupt is lost the system reboots, which is very very bad :(. Has anybody of you recognized similar problems? How do you used a microblaze with interrupt controller? Does anybody share my opinion of that interrupt controller "bug"? Thank you very much for your help, Reiner Abl -- _____________________________________ www.rockmotion.deArticle: 64022
Has anyone had any experience of using LP_ROM modules in Lattice XPGA Devices? I have generated an LPM_ROM and loaded it with an initialisation file, the code compiles and the floorplanner shows that EBR's are being used for the ROM. However i can't seem to run a functional simulation in Modelsim, the data from the ROM stays at "UUUUUUUU" whatever the address signal is. Thanks, MattArticle: 64023
v2.10 "dhanashree" <mytechiedata@math.net> wrote in message news:a3c11f6f.0312110521.e5ae0b@posting.google.com... > Hi, > > I am a novice to hardware programming... > I have a query..I need to know which PCI versions any motherboard can support... > E.g I wish to find which versions of PCI my i810 chipset motherboard > (or rather any motherboard) can support > Is there any method to accomplish this? > > Thanks and regards,Article: 64024
> The method I used to do for PQ208s and such was to make my PCBs with > lead&tin coating. Now, all what I needed to do was to glue the PQ208 part in > its place, and use hot air on the pins. Less than 2 minutes for a perfect > job. thats a good idea!
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