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kkaranasos@in.gr (kpk) wrote in message news:<f2753b28.0312310022.7c2153f6@posting.google.com>... > Can anyone send me a 4-bit binary divider circuit in this email : > kkaranasos@in.gr ? I must make this homework for my university and i > am late. > I have to make this circuit only with NAND gates. > > PLEASE HELP !!!!!!!!! > > Thanks a lot In a few years there may be a job for you at the NY Times as a technology correspondant. Just make it up as you go or dredge it from the net. It wouldn't be anymore crazy than the real thing. Happy new year every oneArticle: 64426
Use only the 144 MHz clock and maybe the 72 MHz. if the others are necessary because you cant "guess" the correct position of the edge, then use a double flip flop and an xor to generate internal clock enables for all the rest (just treat them as inputs.) A simple state machine could also be used to monitor the other clocks and generate the same clocks internally to the FPGA so that they are always in the correct phase. You can do the same with the clock sources but remember monostability (add a third flip flop in front of the two). Simon "A Day & A Knight" <kelvin8157@hotmail.com> wrote in message news:bt7sbj$5kh$1@mawar.singnet.com.sg... > Hi, there: > > I have ASIC source codes from a previous communication chip. It has some 23 > clocks, > many of them are derived from a 144MHz clock (72/36/24/18/.../2/1MHz), only > three from > other sources. The ASIC codes made use of a clock generator with clock > gating... > > How am I going to handle all these different clocks? In a Vertex chip, there > is only 16 clock buffers. > > May I use a "always @ posedge clk144mhz clk72mhz <= ~clk72mhz " to generate > a 72mhz while > use same global buffer as 144mhz? > > Best Regards, > Kelvin > > >Article: 64427
On Thu, 01 Jan 2004 23:23:02 GMT, Spehro Pefhany <speffSNIP@interlogDOTyou.knowwhat> wrote: >On Thu, 01 Jan 2004 22:53:26 GMT, the renowned Bob Perlman ><bobsrefusebin@hotmail.com> wrote: > >>On Thu, 1 Jan 2004 17:17:38 -0500, "Jerry" <nospam@nowhere.com> wrote: >> >>>WOW, your prof let you use NANDs? we had to do this using only >>>relays. Wish I had an easy prof like yours. >>> >>>(:>) >>> >>>Jer >> >>Hah! Luxury! When I was a boy, Professor Babbage made us use gears >>and levers! Compared to that experience, designing with today's EDA >>tools seems...well, pretty much the same, actually. >> >>Bob Perlman >>Cambrian Design Works > >You had gears and levers? We would have given our right arms for gears >and levers! Cowrie shells was what we had, and were glad for it. > > >Best regards, >Spehro Pefhany Here is a divider using pots. http://w1.859.telia.com/~u85920178/index.htm look under "useful circuits" then "simplist computer" Regards, John Crighton SydneyArticle: 64428
> How am I going to handle all these different clocks? In a Vertex chip, there > is only 16 clock buffers. I don't know how practical this is in your situation, but you could drive all your registers off of the 144 MHz and then use the appropriate clock enables. To do this, you can create a Perl script that will go through the code and automatically insert enable code where needed. How hard this will be depends on the quality of the code you've inherited. If you manage to do that, then you're done with the easy part. The hard part will be verifying that you didn't break anything. Unfortunately it's doubtful extensive test code came along with the source code, so you will have to do it yourself. If you don't like the idea of that, I suppose you could keep all your 23 clocks, and use regular routing resources for the least used clocks. Then throw in aggressive MAXSKEW timing constraints to try and manage it all. I have never tried this, but I think you'd get more headache and stress with this option. A harder time routing, and perhaps tough to track down timing bugs. Well hopefully someone will come up with an easier solution. Best of luck.Article: 64429
: What program you using ..Quartus? Xilinx ISE Webpack 5.2i with ServicePack, Modelsim XE 5.6e Starter.Article: 64430
Hi I know that the "reg"'s are all zeroes when powered on (on Xilinx FPGAs). Is this a good idea (assumption) to work on? Can I assume the same for ASIC development? that is I don't have to change my codes later on? Thanks.Article: 64431
Hi I've been coding a rs-232 rx/tx module. after some hardwork, it's all working fine for timeing and everything (rx/tx) -- except one thing-- whenever I reprogram the FPGA, the first byte received always has 0x80 bigger than what was actually sent. everything works fine afterward. I'm using comDebug. I don't use flow control, and only RXD,TXD lines. Any suggestion? Thanks.Article: 64432
In news:3ff7a626.15827459@News.CIS.DFN.DE, John Crighton typed: > > Here is a divider using pots. > http://w1.859.telia.com/~u85920178/index.htm > look under "useful circuits" then "simplist computer" I can't find those links on the site.Article: 64433
> whenever I reprogram the FPGA, the first byte received always has 0x80
> bigger than what was actually sent. everything works fine afterward.
> I'm using comDebug.
What does in mean *the first bite received*? After what? If after power-on
the revise async resets in appropriate process. If all the bytes are ORed
with '1' then you catch the stop bit.
Please remember two things when programming rs232:
- sample bits at the middle of bit slice; and
- pass to receiving next bit at the middle of stop bit.
Article: 64434Tom Del Rosso wrote: > In news:3ff7a626.15827459@News.CIS.DFN.DE, > John Crighton typed: >> >> Here is a divider using pots. >> http://w1.859.telia.com/~u85920178/index.htm >> look under "useful circuits" then "simplist computer" > > I can't find those links on the site. It has weird navigation. I found it by right-click/open in new window on 'Projects' link near the top. Not obvious... mfcArticle: 64435
Do you use an "async_rst" signal to reset the FPGA after configuration? If not, be careful as the registers start at "0" regardless of the input levels. Could you share your code so that we can take a look? You can also find some sample code here http://www.fpga4fun.com/files/async.zip Jean "Paul" <paulw@mmail.ath.cx> wrote in message news:3ba4d769.0401040325.fe13f47@posting.google.com... > Hi > > I've been coding a rs-232 rx/tx module. after some hardwork, it's all > working fine for timeing and everything (rx/tx) -- except one thing-- > whenever I reprogram the FPGA, the first byte received always has 0x80 > bigger than what was actually sent. everything works fine afterward. > I'm using comDebug. > > I don't use flow control, and only RXD,TXD lines. > > Any suggestion? Thanks.Article: 64436
Simone Winkler wrote:
> Hello!
>
> I've got a strange problem that I don't know any solution for - up to now I
> tried everything, but it didn't work.
> The state machine always stops to go to the next state - I
> really don't understand why.
>
> I've got a state machine with 5 states: SEL_EP, WRITE_INIT, WRITE_DATA,
> VAL_BUF and IDLE. It gets stuck after the WRITE_INIT state, just remains in
> the WRITE_INIT state all the time. WHY????
> The 2nd (smaller) problem is, that the data at write_out comes one clock
> cycle too late. I understand why, but how can i change this?
>
> I don't know if it's a good idea to solve my problem with my kind of code,
> i'm an "advanced beginner" and as I am used to program "sequential
> programming languages" I've got big problems with doing sequential things in
> vhdl. What is the easy way to do things one after the other, e.g. write one
> byte after the other? (also to be synthesizable).
>
> I put the code at http://members.liwest.at/simsi/stuff/usb.vhd, because it's
> quite long to put it here. (don't be afraid - no virus!)
>
> Please help me! I really don't know where to go on.
And later posted:
> Xilinx ISE Webpack 5.2i with ServicePack, Modelsim XE 5.6e Starter.
You should be able to use Modelsim to duplicate the lockup, and
therefore see what input to the state machine is causing you the problem.
BTW, you may not be getting what you expect with at least one of your
procedures since the clocked part of the procedure is within another if
statement.
Also, the proper newsgroup for this type of question is
news:comp.lang.vhdl
Have fun,
Marc
Article: 64437Hi I am using System ACE module from Insight with Virtex 2 pro board. Of all the things i am facing a very trivial but more complicated situation. In order to make the files stored in flash card readable by system ace module, it need to be formattted by win 98 not by win 2000 or XP( as xilinx said formatting done by dos on win 2000 and xp has problems ).Now that, i want some utility that can help me to format by flash card with an option to change the sector size, since win 98 doesnt have an option to change the sector size. I searched for some on the web but couldnt find one, and this raises me a question of what does insight and xilinx had in mind when they come up with such a product that can be formatted only by win 98(which is obselete )and not support customers with any formatting utility,since i had already spent a lot of time on this issue in consulting with xilixn hotline and my fae. Any help on guiding me to find the formatting utility would be appreciated. Thanx for your effort and time. Thank you Regards Ram nathanArticle: 64438
Andy Peters wrote: > Chris Carlen <crcarle@BOGUS.sandia.gov> wrote in message news:<bsa1a102rfm@enews3.newsguy.com>... > >>The Verilog they provided is (just counter section within an always @ >>(posedge clk) begin procedural construct): >> >>//Counter section: >> if(run) begin >> if(dir) begin >> q[3:1] = q[2:0]; //Shift lower bits (Left Shift) >> q[0] = !q[3]; //Circulate inverted MSB to LSB >> end >> else begin >> q[2:0] = q[3:1]; //Shift upper bits (Right Shift) >> q[3] = !q[0]; //Circulate inverted LSB to MSB >> end >> end > > > Jeez. More blocking assignments in clocked always blocks! Further > proof of my assertion that models and examples are built by a > company's most junior engineers, and that the companies involved don't > bother checking anything before throwing it up on the web. The only > possible explanation is that they just don't care. > > If we can't trust the examples, how can we trust the post-P&R > simulation models? > > --a Good points. I guess I will be cautious about using the examples for coding style. I will be diving in to the text seriously starting Monday when I'm back to work. Hopefully the text will learn me the right way. Good day and thanks for the input. -- _____________________ Christopher R. Carlen crobc@earthlink.net Suse 8.1 Linux 2.4.19Article: 64439
"Jean Nicolle" <j.nicolle@sbcglobal.net> wrote in message news:<%XZJb.6009$_r6.2064@newssvr29.news.prodigy.com>...
> Do you use an "async_rst" signal to reset the FPGA after configuration?
>
> If not, be careful as the registers start at "0" regardless of the input
> levels.
>
>
>
> Could you share your code so that we can take a look? You can also find some
> sample code here http://www.fpga4fun.com/files/async.zip
>
> Jean
>
There is no buffer right now, so it cannot receive continuous bytes.
working on that when I got this "first byte" problem figured out.
`define LENGTH (50000000/38400)
module top2(clk,RXD,TXD,led0,led1);
input clk;
input RXD;
output TXD,led0,led1;
reg [1:0] s1;
reg [7:0] char_w;
wire [7:0] char_r;
reg go_r,go_w;
send qq1 (clk,char_w,go_w,ok_w,TXD);
recv qq2 (clk,char_r,go_r,ok_r,RXD);
assign led0=~char_w[6];
assign led1=~char_w[7];
always @(posedge clk) begin
case (s1)
0: begin s1<=s1+1; go_r<=1; go_w<=0; end
1:if (ok_r) begin s1<=s1+1; go_r<=0; char_w<=char_r; end
2: begin s1<=s1+1; go_w<=1; end
3:if (ok_w) begin s1<=s1+1; go_w<=0; end
// default: s1<=s1+1;
endcase
end
endmodule
module send(clk, din, go, ok, TXD);
input clk;
input [7:0] din;
input go;
output ok; reg ok_r;
output TXD; reg TXD_r;
reg [31:0] cnt;
reg [7:0] step;
assign TXD=~TXD_r;
assign ok=ok_r;
reg s1;
always @(posedge clk) begin
case (s1)
0 : begin
cnt<=0;
step<=0;
ok_r<=0;
TXD_r<=0;
s1<=1;
end
1 : if (go != 0)
begin
cnt<=cnt+1;
if (cnt==`LENGTH) begin step<=step+1; cnt<=0; end
if (step==12) begin s1<=0;ok_r<=1; end
else if (step==0) TXD_r<=1;
else if (step>=9) TXD_r<=0;
else if ((step>0)&&(step<9)) TXD_r<=~din[step-1];
end
endcase
end
endmodule
module recv(clk, din, go, ok, RXD);
input clk;
output [7:0] din; reg [7:0] din_r;
input go;
output ok; reg ok_r;
input RXD; reg RXD_r;
reg [31:0] cnt;
reg [7:0] step;
assign ok=ok_r;
assign din=din_r;
reg s1;
reg s2;
always @(posedge clk) begin
RXD_r<=~RXD;
case (s1)
0 : begin
cnt<=0;
step<=0;
ok_r<=0;
s1<=1;
end
1 : if (go != 0)
case (s2)
0 : if (RXD_r == 1) begin s2<=1;din_r<=0; end
1 : begin
cnt<=cnt+1;
if (cnt==`LENGTH) begin step<=step+1; cnt<=0; end
if (step==9) begin s1<=0;s2<=0;ok_r<=1; end
else if (step==0) begin end
else if ((step>0)&&(step<9)&&(cnt==(`LENGTH/16)))
din_r[step-1]<=~RXD_r;
end
endcase
endcase
end
endmodule
Article: 64440Hi did I mention that a Maxim MAX3386E RS232 voltage converter was between fpga and the connector on my board. maybe it has something to do with it. also, after some debugging. I found out a few facts: 1. if I send 0x00 from comDebug, the last 2 MSB's are correctly received. (from LED lights.) the echoed value received from comDebug is 0x80. 2. if I send 0x10 from comDebug, the last 2 MSB's are correctly received. (from LED lights.) the echoed value received from comDebug is 0x90. 3. if I send 0x20 from comDebug, the last MSB is correctly received. but the 6th bit was wrong. (from LED lights.) the echoed value received from comDebug is 0xA0. 4. if I send 0x40 from comDebug, the 6th and 7th got switched. (from LED lights.) the echoed value received from comDebug is 0xC0. 5. if I send 0x80 , the echoed value received from comDebug is 0x80. (however, the led indicate I received 0x00.) so from this I can conclude there is something wrong in both the send and recv modules -- for the first byte. strangely every byte afterward is OK.Article: 64441
"Paul" <paulw@mmail.ath.cx> wrote in message news:3ba4d769.0401040319.40ffdbcd@posting.google.com... > Hi > > I know that the "reg"'s are all zeroes when powered on (on Xilinx > FPGAs). Is this a good idea (assumption) to work on? Can I assume the > same for ASIC development? that is I don't have to change my codes > later on? > > Thanks. Its the worst idea I have seen on this newsgroup to assume the state of registers at power up in an ASIC. BAD BAD BAD, 300 lashes with a broken O'scope lead for the assumption. Watch your simulator. It should have unknown in registers that were not initialized. Some registers initial state is a don't care, some are very critical, it all depends on your design. JerArticle: 64442
Hi, I am using Xilinx PCI_64_66_CORE Build 106 (04-04-2003) with ISE 4.2i/FPGA Express/VHDL design flow. When I try to translate, a.k.a. NGDBUILD, the design, I encounter the following errors: ERROR:NgdBuild:393 - Could not find INST(S) 'PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD' in design 'gefsc_top'. INST entry is 'INST "PCI_CORE/PCI_LC/PCI-AD64/IO31/OFD" IOB = TRUE ;' ERROR:NgdBuild:393 - Could not find INST(S) 'PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD' in design 'gefsc_top'. INST entry is 'INST "PCI_CORE/PCI_LC/PCI-AD64/IO30/OFD" IOB = TRUE ;' ERROR:NgdBuild:393 - Could not find INST(S) 'PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD' in design 'gefsc_top'. INST entry is 'INST "PCI_CORE/PCI_LC/PCI-AD64/IO29/OFD" IOB = TRUE ;' The error continues for the whole bus width, and for other signals as well. I think the ucf file specifies the constraints using "/" to reference the instance, but the core instantiates in a different way. There is a file by the name of "pci_lc_i.vhd" which I found the instance PCI_AD64_IO31_OFD instantiated as: PCI_AD64_IO31_OFD : X_FF port map( ..... Does this mean I have to change the ucf file's constraint statements? Can anyone in the group who has used xilinx logicore pci64 advice me on this? Any help is greatly appreciated. Regards, LCArticle: 64443
Hello...
Can anybody tell me that why Nios SDK cant display floating point
datatype if I include excalibur.h as the header file? The C code that
process simple floating point works correctly only if I exclude the
excalibur.h file. The problem occur when I need the software
subroutine for the standand peripherals but I cant display the
processing time if the calculation formula involved floating point.
Article: 64444Hi, there: Assume my chip uses the CLK180 and CLK90 at same time, does it mean CLK180 & CLK90 uses the same global clock tree? Or, do I need to instantiate a BUFG for each of them? Best Regards, KelvinArticle: 64445
Hi, Currently I'm working on a OPB to ISA bridge to be included as a peripheral in a Microblaze system. To verify that the bridge works, I've also made a GPIO that is connected as a peripheral on the ISA bus. The ISA data bus is bidirectional and is thus implemented as a tristate port. Since the data port on the ISA GPIO also is bidirectional, that is also implemented as a tristate. The problem is that when the two tristate signals are connected in the system.mhs file (data = isa_sd) XST interprets that to connect the isa_sd_i with data_i, isa_sd_o with data_o, and isa_sd_t with data_t. I have also tried to separate the data ports on the GPIO side, but I haven't worked out how to specify that isa_sd_o should be connected to data_i and isa_sd_i to data_o. Does anyone with more experience on this matter than me have any good suggestions on how to solve the problem? JohanArticle: 64446
paulw@mmail.ath.cx (Paul) wrote in message news:<3ba4d769.0401040319.40ffdbcd@posting.google.com>... > Hi > > I know that the "reg"'s are all zeroes when powered on (on Xilinx > FPGAs). Is this a good idea (assumption) to work on? Can I assume the > same for ASIC development? that is I don't have to change my codes > later on? > > Thanks. This is a very bad idea. Bad/no design for exiting reset state will cause your ASIC/FPGA to be unreliable - sometimes it will start working, sometimes not. In addition, most simulators HATE it - they will start with everything in "unknown" state. Reset-recovery problems are very hard to simulate (same category as meta-stability problems - not really deterministic), so that the design appears to be OK in simulation. Best practice: * EVERY flip-flop should be explicitly reset (including FFs in I/O pads). * Resets are global nets, treated exactly like clocks. Most FPGAs allow using dedicated clock nets for reset - recommended. * Each clock-domain should have its own reset. The trailing edge of the reset signal should be synchronous to the clock and shouldn't violate reset-recovery timing for any FF. (use a synchronizer for reset - the probability of two FFs stuck in meta-stable state is much lower than one or two of a set including tens of thousands FFs in the clock-domain). * Just to make your design clear, use the same signal-name everywhere for every reset net (also good practice for clock nets).Article: 64447
Hi, there: I saw this statement in Virtex-2 datasheet, how do I make use of these local clocks? Is there any documents on these local clocks? Best Regards, Kelvin Local Clocking In addition to global clocks, there are local clock resources in the Virtex-II devices. There are more than 72 local clocks in the Virtex-II family. These resources can be used for many different applications, including but not limited to memory interfaces. For example, even using only the left and right I/O banks, Virtex-II FPGAs can support up to 50 local clocks for DDR SDRAM. These interfaces can operate beyond 200 MHz on Virtex-II devices.Article: 64448
"Jerry" <nospam@nowhere.com> wrote in message news:<vvhf7ii29ntnbf@corp.supernews.com>... > "Paul" <paulw@mmail.ath.cx> wrote in message > news:3ba4d769.0401040319.40ffdbcd@posting.google.com... > > Hi > > > > I know that the "reg"'s are all zeroes when powered on (on Xilinx > > FPGAs). Is this a good idea (assumption) to work on? Can I assume the > > same for ASIC development? that is I don't have to change my codes > > later on? > > > > Thanks. > > Its the worst idea I have seen on this newsgroup to assume the state of > registers at power up in an ASIC. > BAD BAD BAD, 300 lashes with a broken O'scope lead for the assumption. > Watch your simulator. It should have unknown in registers that were not > initialized. > Some registers initial state is a don't care, some are very critical, it all > depends on your design. > > Jer Can't I just tell the foundry that I need the regs to be zeroes at powered on? Anyone done this before?Article: 64449
On 5 Jan 2004 01:01:03 -0800, paulw@mmail.ath.cx (Paul) wrote: >"Jerry" <nospam@nowhere.com> wrote in message news:<vvhf7ii29ntnbf@corp.supernews.com>... >> "Paul" <paulw@mmail.ath.cx> wrote in message >> news:3ba4d769.0401040319.40ffdbcd@posting.google.com... >> > Hi >> > >> > I know that the "reg"'s are all zeroes when powered on (on Xilinx >> > FPGAs). Is this a good idea (assumption) to work on? Can I assume the >> > same for ASIC development? that is I don't have to change my codes >> > later on? >> > >> > Thanks. >> >> Its the worst idea I have seen on this newsgroup to assume the state of >> registers at power up in an ASIC. >> BAD BAD BAD, 300 lashes with a broken O'scope lead for the assumption. >> Watch your simulator. It should have unknown in registers that were not >> initialized. >> Some registers initial state is a don't care, some are very critical, it all >> depends on your design. >> >> Jer > > >Can't I just tell the foundry that I need the regs to be zeroes at powered on? >Anyone done this before? No, reset is a functionality which needs to be designed in. There are several reasons for this. One is that some methodologies require that there be no asynchronous resets and and initialization be synchronously loaded. But this requires a clock to work. Also async reset flops are usually larger and slower than non-reset flops so it's a plus if you don't need them. Also it doesn't depend on the foundry but the cell library you use. The best solution is to use asynchronous resets with external reset being synchronized with two flops per each clock domain where the reset signal is needed. This way you can time the reset recovery constraint and there are NO metastability issues to be dealt with and two flops are all that's needed. The two flops used in reset synchronization are similar but not the same two flops which are used in cross clock domain transfers. Hope this helps, Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations
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