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Hello, I have an XILINX FPGA evaluation board with a JTAG pod, which connects to the parallel port. To download my VHDL code I'm using the iMPACT software. If I repeatably download code to the FPGA it starts to act in a strange way e.g. parts of it just stop working. The only way I can overcome this is to remove the power supply and then reattach it, therefore reseting it. After doing this everything works fine. Is this a common problem with FPGA's or am I doing something wrong? Could it be a problem in my code or do I just have to keep toggling the power to the FPGA? Thanks for any advice,Article: 65001
If your board RJ45 connector is hard-wired to the PHY chip, you can't use it, you need to buy a separate RJ45 connector and wire it manually to 2 IOs of the FPGA. JeanArticle: 65002
Hi can someone concisely explain what is 802.3 mii. it seems my PHY chip has this function. what does it do? (i spend half an hour googling and still can't figure out what it does) is it some higher level of abstraction that's easiler to interface? why they design this chip with rx and tx in nibbles ? why not bytes... lxt972 ThanksArticle: 65003
Paul wrote:
> Hi
>
> can someone concisely explain what is 802.3 mii.
> it seems my PHY chip has this function.
> what does it do?
This sounds a little too close to homework for comfort.
Quoting from the LXT972 datasheet:
"provides a Media Independent Interface (MII) for easy attachment to
10/100 Media Access Controllers (MACs)."
Or said another way, it is supposed to make connecting to a MAC device
easy...
> (i spend half an hour googling and still can't figure out what it does)
> is it some higher level of abstraction that's easiler to interface?
Higher levels of abstraction almost always make things easier -
otherwise people wouldn't bother with the abstraction! The question is
how does it make things easier?
> why they design this chip with rx and tx in nibbles ?
> why not bytes...
Cause that is how MII is defined. Can you think of any reasons that, if
you were designing this interface, you might choose nibbles over bytes?
It sometimes helps to imagine specific examples in cases like this, so
here is one: imagine designing a 24 port Ethernet switch.
Have fun,
Marc
Article: 65004Looking for references/papers on implementations of anisotropic filters in FPGAs. Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 65005
Jean Nicolle wrote: (snip) > About the reflection, since this particular experiment is an emitter only, > I'm relying on the other end device (an Ethernet switch) to do proper > termination (which it does, according to my measurements). > Once I work further on the receiver part, I certainly need to pay attention > to terminating the lines i.e. putting a resistor across the pair. It is still best to terminate both directions, but it will generally work if you terminate one end, for protocols that only send one direction on each pair. As you say, if the receiver is terminated, there won't be a reflection. It the transmitter is properly terminated, the reflection from the receiver will be absorbed at that point, and won't cause problems (most of the time). When you get to gigabit, using both directions on each pair at the same time, proper termination of both ends is much more important. Termination at both ends for unidirectional systems allows a tolerance for mismatch. If 10baseT is terminated at 120 ohms, then using cable between 100 ohms and 150 ohms will result in at most about 20% reflection. At most about 20% of that, or 4% of the original will then reflect back again from the other end. -- glenArticle: 65006
Hi Nial, Yes you are correct. When I wrote my Srec-converter program, I looked at a nios-built Srec file, and all records were contiguous. Later on, I realized in some programs, nios-build will skip bytes here and there. Live and learn. > cruzin <cruiser144@hotmail.com> wrote in message > news:775730eb.0401172120.28d24bd6@posting.google.com... > > Hi Petter, > > > > I wrote a program to convert an Srec file to a binary file and then > > downloaded this over a PCI/Avalon bridge. > > > > I have found my problem, which was that I assumed the Srec file was > > always writing a contiguous memory region, when in fact sometimes > > addresses are skipped, presumably for alignment optimization. > > If you have a look at the srec spec, I'm fairly sure the > first data after the 's' on every line is the address that > line starts at. > > > Nial > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > Cyclone based 'Easy PCI' dev board > www.nialstewartdevelopments.co.ukArticle: 65007
Hi, I have a very simple Stratix SOPC system: An Avalon DMA block whose read and write masters both connect to a MegaRAM. The DMA control bus is mastered by Nios. My DMA blocks registers are set up as: np_dmareadaddress = 0x10000; // base of MegaRAM np_dmawriteaddress = 0x11000; // 1024 words in np_dmalength = 32; // xfer 32 bytes np_dmacontrol = 0x8C; // do 32-bit xfer, end when length=0 and GO! I verified the registers by reading them back, and the status reg indicates operation just as I would expect. When I simulate this system in Active-HDL everything works as expected. On actual hardware, unfortunately, I must always run the DMA operation twice to get the right data into MegaRAM - the first time always writes data to the destination address that is from the PREVIOUS time that I ran the DMA operation. It always write 4 words of old data; after these 4 words, the written data is current and correct. The only way I can rationalize this is that the FIFO inside the DMA block is writing data to the destination before the source data has been read into it. My questions are: - Can I use the Avalon DMA block to DMA to/from MegaRAMs? Or do the source and/or destination resources have to be streaming slaves? (ie. can a streaming master such as DMA work with non-streaming slaves such as MegaRAMs? - Why does simulation give me the correct results? Does it have to do with me running on Stratix, whereas Active-HDL may assume I'm running on Apex, etc? - Is there a bug with the DMA block, or am I doing something stupid?Article: 65008
I think only the Virtex II or Pro has a "reset device" command from JTAG. You need to ground the prog pin or remove the power each time. The only other way might be to make a "blank" design and load that before you load your design. Just as a matter of jargon you download bitstreams that make come from VHDL you don't download a VHDL file. Steve -- CONFIDENTIALITY NOTICE This communication (and/or the documents accompanying it) may contain privileged or other confidential information. If you are not the intended recipient, you are hereby notified that any use, disclosure, copying, distribution or the taking of any action in reliance on the contents of this information is strictly prohibited. If you have received it in error, please advise the sender by reply e-mail and immediately delete the message and any attachments without copying, using or disclosing the contents. Thank you for your cooperation. "Chris" <Chris@nospam.com> wrote in message news:buduhr$meb$1@news7.svr.pol.co.uk... > Hello, > > I have an XILINX FPGA evaluation board with a JTAG pod, which connects to > the parallel port. To download my VHDL code I'm using the iMPACT software. > If I repeatably download code to the FPGA it starts to act in a strange way > e.g. parts of it just stop working. The only way I can overcome this is to > remove the power supply and then reattach it, therefore reseting it. After > doing this everything works fine. > > Is this a common problem with FPGA's or am I doing something wrong? Could > it be a problem in my code or do I just have to keep toggling the power to > the FPGA? > > Thanks for any advice, > >Article: 65009
I have found a tube of these AMD parts from on old project. AMD no longer manufactures these parts. Does anyone know who picked up these parts from AMD ? I am also looking for a simple programmer for these parts. I have found $500+ programmers out on the net, but I would like to keep it cheap. Thanks for any info. hamiltonArticle: 65010
Hi I've just read through the page. Found one problem: // IP header 7'h14: pkt_data <= 8'h08; 7'h15: pkt_data <= 8'h00; According to my textbook from Tanenbaum. This 2 bytes should be the length of the MAC data. From the rest of codes, it should be "0x48 - 8" , i.e. 7'h14: pkt_data <= 8'h00; 7'h15: pkt_data <= 8'h40; // IP header ... ... I wonder why it should work if it did. (I can't test it yet.) Does that imply you can switch positions for CRC and some 4 data bytes? Also one more question: I notice there are idle bits inserted for mechester encoding. is that necessary? Since I have a PHY chip, I guess I don't have to worry about that. Just curious. Thanks.Article: 65011
Hi Kelvin, This should work fine, the DCM multiplies and divides at the same time (in simplistic terms) so the spec isn't exceeded. cheers, Syms. "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:bud50h$9ab$1@reader01.singnet.com.sg... > Hi, there: > > I tried one simulation with the following parameters to derive a 36MHz from > 40MHz crystal... > It works in simulation, but does it work in Virtex-2 with speed grade of 6? > I am cautious as > 40 * 9 makes 360MHz and it is beyond the Virtex-2's DCM timing > specification. > > defparam DCM1.CLKFX_DIVIDE = 10; > defparam DCM1.CLKFX_MULTIPLY = 9; > > I also tried to use a state machine to divide crystal into 4MHz and then > multiply by 9, but it Model-Sim > complained the input clock jitter was beyond 1ns... > > How may I do this task? > > Thanks for your advice... > Kelvin > > > >Article: 65012
On Sun, 11 Jan 2004 14:26:48 -0500, Ralph Malph <noone@yahoo.com> wrote: >Bob Perlman wrote: >> >> On 30 Dec 2003 09:53:47 -0800, news@sulimma.de (Kolja Sulimma) wrote: >> >> >> If you think there's even a chance that you're going to be designing >> >> in a certain component, get a formal price quote from the salesman, >> >> rep, or distributor. And if you can't get a quote, maybe you can't >> >> get the part, either. >> >> > Bob Perlman >> >> Cambrian Design Works >> > >> >The issue was, that the formal quotes for pieces in 5k quantities >> >where a factor of 20 above the prices quoted by Xilinx for 250k >> >quantities. >> >And nobody in this group really believed that you get a 95% volume >> >discount. >> >> If a formal quote for 5k pieces comes in at 20X a formal quote for >> 250k pieces, that's interesting information. But if a formal quote >> for 5k pieces is 20X the 250k price stated in a press release, that's >> hardly surprising. >> >> Which is it? >> >> Any price you see in a press release should have a "j" after it. > >"J" for joke? "J" as in "imaginary number." EEs employ "j" instead of "i" because we use the latter for current. Bob Perlman Cambrian Design WorksArticle: 65013
> You could try to obtain a used DAS9200 or TLA510 system with a pattern > generator board (these generate patterns based on a 50MHz clock). > These systems are for sale on Ebay every now and then. Or you can rent these things from companies like ElectroRent IIRC or GE or whatever. They are not that difficult to use, we used to have a HP PG on the network to download files into ram and that would throw the pattern at your HW. The matching HP LA would observe the results and get it back onto the network. The only issue I had was the memory buffers were very small relative to PC memory and the bus widths were too narrow, kinda dinasours by todays std. An FPGA just calls out to be used as an PG+LA in a box to custom spec, but thats another project. Or just use one of the ready made boards withs lots of IO and onboard ram. johnjakson_usa_comArticle: 65014
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:<dRDNb.11195$gD6.6510@newssvr25.news.prodigy.com>... > It's a single data path. > > It looks like none of the current FPGA's will support this in non-trivial > application. > > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > Indeed, the X Avnet? board I previously mentioned was RLDRAM1 about 300MHz DDR and RAS cycle 25ns IIRC. I don't see why you couldn't use RLDRAM2 at the lower DDR rates but still get 20ns RAS cycle at least its as close to 10ns SRAM as you will get for now. I also mistakenly said the IOs were split, I was looking at another Cypress SRAM at same time. If anyone does get/see RLDRAM2 running on X esp Spartan3, I'd like to know about it too, but I can live with lower IO rates, shame about the common IOs. johnjakson_usa_comArticle: 65015
--------------------------- > > Selected Device : 2s200pq208-6 > > Number of Slices: 396 out of 2352 16% > Number of Slice Flip Flops: 161 out of 4704 3% > Number of 4 input LUTs: 652 out of 4704 13% > Number of bonded IOBs: 86 out of 144 59% > Number of TBUFs: 64 out of 2352 2% > Number of BRAMs: 1 out of 7 14% > Number of GCLKs: 1 out of 4 25 > > > What I do/understand incorrectly ? > > Regards, > Przemyslaw Wegrzyn I see the exact same problem in WebPack 6.1 (no service pack) when toying a cpu datapath into Spartan3-400. Datasheet says 16 blockrams, report says 1 of 8. Hopefully the service pack v3 will fix that, right. Also I seem to recall Webpack would allow Spartan3-1000 or was that wishfull thinking. Another point of note, when choosing a cpu datapath width that might be adder or blockram cycle limited, I found that the 1st registered output of blockram is some slower than normal pipe stage. Seems optimal result is for 16b wide datapath that allows adds and ram access to both hit close to 200MHz but only if bram output has extra pipe stage. A cpu that has blockram regfile output feeding alu logic and 32bit wide is double penalized down to 120MHz or so. This leads to architecture decisions based on low level details that will be far different than classic risc (MicroBlaze at 85MHz etc) but seems otherwise justified for higher performance since I can always use multi cycle opcodes. johnjakson_usa_comArticle: 65016
On 18 Jan 2004 10:17:25 -0800, paulw@mmail.ath.cx (Paul) wrote: >Hi > >I saw this cool project on fpga4fun on 10baseT ethernet. it's so cool >needs only 2 lines. like rs-232. >I like to try it, but my board has this LXT972 chip (ethernet PHY >thingy, like those MAXxxxx rs-232 voltage convertor thingy) sitting >between my >x2cv2000 fpga and the connector. it has so many pins that i don't know >what to do with them. It's called MII, and is quite a simple interface. Had you tried reading the datasheet? http://www.intel.com/design/network/products/lan/datashts/24918603.pdf Note: the LXT972 does 4B5B code conversions (when in 100Base-T mode) or Manchester encoding (when in 10Base-T mode). It is not a simple voltage level converter like a MAX232. >Can someone know about voltage and stuff tell me how to do. >can i rewire say 2 of the 5 rs-232 lines to be used as Ethernet_TDp >and Ethernet_TDm ? If you want a truly Ethernet standard interface you should stick with the hardware you have. Otherwise, you can use Jan's interface if you have access to some spare I/O pins. Regards, Allan.Article: 65017
On 18 Jan 2004 17:31:14 -0800, paulw@mmail.ath.cx (Paul) wrote: >Hi > >I've just read through the page. Found one problem: > >// IP header > 7'h14: pkt_data <= 8'h08; > 7'h15: pkt_data <= 8'h00; > >According to my textbook from Tanenbaum. >This 2 bytes should be the length of the MAC data. >From the rest of codes, it should be "0x48 - 8" , i.e. > 7'h14: pkt_data <= 8'h00; > 7'h15: pkt_data <= 8'h40; >// IP header > ... > ... > >I wonder why it should work if it did. (I can't test it yet.) >Does that imply you can switch positions for CRC and some 4 data bytes? > >Also one more question: >I notice there are idle bits inserted for mechester encoding. is that necessary? >Since I have a PHY chip, I guess I don't have to worry about that. Just curious. You've come across the difference between Ethernet II and IEEE802.3. Ethernet II frame: Dest Addr (6 bytes) Src Addr (6 bytes) Ethertype (2 bytes, 0800 for IPv4) Data FCS (4 bytes) IEEE802.3 SNAP frame: Dest Addr (6 bytes) Src Addr (6 bytes) Length (2 bytes) DSAP (1 byte) SSAP (1 byte) CTRL (1 byte) OUI (3 bytes) type (2 bytes) Data FCS (4 bytes) Note that the Ethertype fields have values that are (usually) greater than the maximum frame length, so that (usually) there is no ambiguity. I say usually because jumbo Ethernet frames can have lengths up to 9k bytes or so, and some Ethertypes have values less than 9k. This is probably why jumbo ethernet frames always use Ethernet II framing (and are not approved by the IEEE). BTW, you could try reading the IETF RFC that describes how to encapsulate IPv4 in ethernet frames (rather than relying on Tanenbaum). I don't recall the RFC number, but I'm sure you know how to use a search engine. http://www.ietf.org Regards, Allan.Article: 65018
Hi, I am currently having a design with multiple reconfigurable modules implemented as separate edifs. I've followed to modular design instructions from the xilinx documentation and have managed to get ngdbuild and map to work fine on all my modules. When I try to do a PAR, after the placement is done, the router takes 15 minutes to start dumping results onto the console. But, once it starts routing, the process seems to finish off in a couple of seconds. The design it is trying to route is a collection of 8 2:1 multiplexers. I dont see why it should take 15 minues for such a small design. The area constraints for the design also seem to be correct. Any ideas why the long runtimes? device = xc2v6000 p.s. does it matter for routing if i organise my modules in columns or rows, assuming they span the entire column/row? does it affect the time it takes to route an area which spans the breadth of the device rather than the height? regards, nachiket.Article: 65019
is it becuase the area is way too big for your codes? i had one pexerience when my reconfiguration module is 58 slices, and the area allocated to it is 3072 slices. it took over two hours to route that small module...fixed module is 3000+ slices in an area of 30000 slices, and it took 10 minutes only...In the trial synthesis, I will use an xc2v2000 to replace my xc2v6000 and see how it works... I also found that, Route Phase 1 takes most of the time, while other 8 stages takes only a fraction of the total time... In the tutorials I created at home, the slice numbers are 759(fixed) out of 1536, 292/338(reconfigurable) out of 1,536, the whole flow, from synthesis to assembly, only took 20 minutes... Hope you could share your experiences after you finished the project... Best Regards, Kelvin... Nachiket Kapre <nachikap@yahoo.com> wrote in message news:eadce17c.0401182056.482e630f@posting.google.com... > Hi, > I am currently having a design with multiple reconfigurable modules > implemented as separate edifs. I've followed to modular design > instructions from the xilinx documentation and have managed to get > ngdbuild and map to work fine on all my modules. When I try to do a > PAR, after the placement is done, the router takes 15 minutes to start > dumping results onto the console. But, once it starts routing, the > process seems to finish off in a couple of seconds. The design it is > trying to route is a collection of 8 2:1 multiplexers. I dont see why > it should take 15 minues for such a small design. The area constraints > for the design also seem to be correct. Any ideas why the long > runtimes? > > device = xc2v6000 > > p.s. does it matter for routing if i organise my modules in columns or > rows, assuming they span the entire column/row? does it affect the > time it takes to route an area which spans the breadth of the device > rather than the height? > > regards, > nachiket.Article: 65020
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<bud50h$9ab$1@reader01.singnet.com.sg>... > Hi, there: > > I tried one simulation with the following parameters to derive a 36MHz from > 40MHz crystal... > It works in simulation, but does it work in Virtex-2 with speed grade of 6? > I am cautious as > 40 * 9 makes 360MHz and it is beyond the Virtex-2's DCM timing > specification. > > defparam DCM1.CLKFX_DIVIDE = 10; > defparam DCM1.CLKFX_MULTIPLY = 9; RTFM, RTFM, RTFM there is somewhere a notice in datasheets that the DCM can be used in such situation where the virtual CLK is way beyound operating frequency, the DCM will still work. So you should be safe, using the DCM with those parameters as given. Antti http://xilinx.openchip.orgArticle: 65021
Dear Sir or Madam, I want to simulate a VHDL design. It includes RAM structures with .mif files (memory initialization files in QuartusII). Modelsim seems not to support that kind of files. So I use .hex files. In QuartusII they can be included in the MegaWizard- PlugInManager. But how do I involve these .hex files when simulating in Modelsim? Do they have to be compiled additionally to the design VHDL files or do they have to be linked to in the testbench? When trying to simulate after compiling the VHDL modules I get an error message "Fatal error ... altera_mf.vhd ... not found". Kind regards Andres Vazquez G & D System DevelopmentArticle: 65022
"Jasmine Hau" <hauyuanwen1980@yahoo.com> wrote in message news:fc6016ce.0401161933.778f4654@posting.google.com... > Hi,I am currently doing research on the Elliptic Curve Cryptosystem > (ECC) on Smart Card Prototype. > I will build a ECC Smart card prototype and download the > entire design into Altera FPGA APEX Device which is EP20K200EFC484-2x. > This prototype does not have an embedded OS. To test and verify my > design, I will build a testbench for Elliptic Curve Digital Signature > and ECC-based Mutual Authentication. > Currently, the Operating System on my PC is Windows2000 with > NTFS File System. My Altera Nios Development Board communicates with > the PC through UART. To build the testbench, i need to write a > software which will be built and run on the Nios SDK shell and able to > do the following functions: > 1. Open a new file or read a existing file (plain-text) in the > Operating System Windows2000 environemnt in my PC. > 2. The file will be sent from my PC to my Smart Card prototype > through UART. > 3. The file (plaintext) will be processed in my Smart Card > prototype to create a Digital Signature. > 4. Both of the original file (plaintext) and the digital > signature will then sent back to PC from smart card prototype through > UART. > > My question is: Does the Nios-gnupro support the file access > system such as fopen, fprintf, fclose? I have written a simple program > which is able to run on Visual Studio but can't execute while in > nios-build process. I wonder does the Nios-gnupro support the file > access system. Thanks for your reply. Wish you all have a nice day. I think you are confusing the issues here quite significantly. The OS you have on your PC is basically irrelevant - when I asked what OS you had, I meant what OS your embedded processor is running - and the answer is none. So unless you implement (or find) functions to create a virtual file system in the Nios's local memory, then it has no fopen, etc., functions. Even with such memory-based file access, it would not give you what you want. Forget file access for the Nios - it is not what you are looking for. You need something running on the PC which accesses files there, and sends them through the UART to the Nios board. The Nios program must take its data from the UART, not through fopen, and send its results back through the UART. Unless you need the Nios program to be able to choose the files itself, you can probably do this using a simple terminal program on the PC (maybe the nios-run terminal, or download something like Tera Term Pro or RealTerm). If you need more than that, you can write a PC program to handle the file access and send data back and forth across the UART.Article: 65023
That makes sense. Terminating the receiver is just a matter of putting a resistor across the wire pair. Now, the question is, how to terminate the transmitter? If I assume cat5 cables (100ohms differential impedance?), my first thought is to put two 50ohms series resistors on the transmitter side. The downside is, it is going to cut in half the incident wave. Any better way? JeanArticle: 65024
Hi, there: I have fixed module A (right) and reconfigurable module B & C(left), the clock buffers are all A's resource area. I need a local constant vcc_fake to control the BUFGMUX. However, my available IOs are only on the right-side of the FPGA, meaning the vcc_fake travels diagonally from the right-middle to the top-middle of the chip, and across the fixed module A's allocated area... In active-module implementation, I found the routing of this vcc_fake between A and B/C are different now. What will happen in the final assembly? Which routing will PAR adopt in the final assembly? Thanks for your advice. Kelvin
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