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ad.rast.7@nwnotlink.NOSPAM.com (Alex Rast) wrote: > >We did think very long and hard about testing, and had several meetings >where we really examined the design carefully, with a view to testability. >But there's also the side of that your board needs to do what it needs to >do. There's not much good designing a highly testable board that doesn't >perform the task you're designing it for. It does seem to me that the >available testing options for high-speed, synchronous interfaces are very >few and far between. The option that people have been recommending, of >putting another identical board in our system to use as a test interface, >is one I thought about and I think, with the consensus being that this is >the best way to go, is what I'll do. Is this, then, the typical way people >test high-speed cards and interfaces? I'm quite surprised that there aren't >more testing/prototype systems available for these kinds of hardware, which >must surely be extremely common. You could try to obtain a used DAS9200 or TLA510 system with a pattern generator board (these generate patterns based on a 50MHz clock). These systems are for sale on Ebay every now and then. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 64976
Hi everyone, 1. Where can i find a free Version of Quartus on Linux OS. I would like to test it. 2. is there any chance to apply QUIP's softwares on architectures that are other than Altera's devices.( Academic tools SIS+VPR allow this) Thanks in advance -- Hayder.Mrabet UPMC LIP6/ASIM Tel: 01 44 27 71 23Article: 64977
On 16 Jan 2004 11:07:19 EST, "Brannon King" <bking@starbridgesystems.com> wrote: >I've made an image illustrating a certain optimization that the VHDL/Verilog >compilers seem to make, but which the mapper does not seem to make. Can >someone explain why this is not done in the mapper? > >Picture: http://www.starbridgesystems.com/images/brans/or_gates.png > >The picture shows some linearly cascaded OR gates vs. a binary tree of OR >gates. The Xilinx Map/Par seem to have a much easier time with timing >constraints when the incoming file is organized binarily, yet it would seem >to me that would be an easy optimization for the mapper to perform. > >What I want to do is use some 3rd-party EDIF generator tools and yet I'm >forced to manually tile out my gates binarily. Thoughts? > Consider using Leonardo Spectrum. I know it can read EDIF as well as VHDL/Verilog, and see no reason why its optimisation tools can't be used on a design read in from EDIF (though I've had no reason to try this myself) - BrianArticle: 64978
Hi ! I'm using XST to synthesise my VHDL sources. Target device is XC2S200 in PQ208 package. According to the Spartan II family datasheet, this device containes 14 BlockRAMs , 4096bits each, which gives 56kbits total. But unfrotunately XST reports only 7 blocks available in the log file ! And of course I'm going to exceed it :(. Here are parts of the log file. ---- Target Parameters Output File Name : bitstream_cpu Output Format : NGC Target Device : xc2s200-6pq208 Device utilization summary: --------------------------- Selected Device : 2s200pq208-6 Number of Slices: 396 out of 2352 16% Number of Slice Flip Flops: 161 out of 4704 3% Number of 4 input LUTs: 652 out of 4704 13% Number of bonded IOBs: 86 out of 144 59% Number of TBUFs: 64 out of 2352 2% Number of BRAMs: 1 out of 7 14% Number of GCLKs: 1 out of 4 25 What I do/understand incorrectly ? Regards, Przemyslaw WegrzynArticle: 64979
Is there any way to speed up simulation (functional or timing) when simulating a Xilinx FPGA which uses the DCM? The DCM requires that the simulator resolution be set to ps range and this really slows down the simulation speed. I have reduced time delays in my design to reduce the simulation time required, however it still takes about 1 hour per millisecond of simulation time. Other than getting a faster computer are there any other things that can be done to reduce the simulation time? I have already removed high frequency signals (clocks) from the simulator waveform window and used variables where possible.Article: 64980
sighhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh :-( "Stephen Williams" <spamtrap@icarus.com> wrote in message news:a36f$40086bdb$40695902$18612@msgid.meganewsservers.com... > Kelvin @ SG wrote: > > Hi, there: > > > > I am using ise WebPack for learning purpose. I am learning modular design > > while > > I can't live without the FPGA Editor...even if a viewer is okie... > > > > I used ISE w6.1.03, but there is no editor on it. > > > > May I know which version has this functionality on it? > > No versions of WebPack have FPGA Editor. You need a for-money > version to get it. > > (My other gripe: No versions of WebPack support Linux native. Grumble.) > > > -- > Steve Williams "The woods are lovely, dark and deep. > steve at icarus.com But I have promises to keep, > http://www.icarus.com and lines to code before I sleep, > http://www.picturel.com And lines to code before I sleep." >Article: 64981
Thank you very much Philip. I am reading the Libraries Guide now. I understand that the simulation model is not meant to synthesize. The Libraries Guide is the single biggest file in the documentation, so I missed it when I download the files. Best Regards, Kelvin "Philip Freidin" <philip@fliptronics.com> wrote in message news:7c87009bgg454q3qoft9olvrjcb61omfn7@4ax.com... > On Tue, 13 Jan 2004 13:49:28 +0800, "Kelvin @ SG" <kelvin8157@hotmail.com> wrote: > >Thank you Freidin! > > You can call me Philip. > > >By the way, what is the name of the PDF document from Xilinx which > >explains how to use these Xilins-specific components, e.g. DCM, LUT, DLL, > >etc? > > All the primitives are documented in the Libraries Guide. Get it from: > > http://www.xilinx.com/support/sw_manuals/xilinx6/download/ > > You should also read the data sheet for the product you are using > as it will give a application view of the function, whereas the > the Libraries Guide is mor of a usage view. You should also look > at the application notes section for in-depth info. > > http://www.xilinx.com/xlnx/xweb/xil_publications_index.jsp?category=Applicat ion+Notes > > >I only know the simulation source codes from ***/src/unisims & src/simprims > >can provide some limited information. > > The simulation models often can give you info that neither the data sheet > or libraries guide give you, BUT, the simulation models do not tell you how > the function is actually implemented. Sometimes the simulation models are > incorrect (not the basic stuff, but the really complex functions). > > >BesT Regards, > >Kelvin > > Enjoy, > Philip > > > > > =================== > Philip Freidin > philip@fliptronics.com > Host for WWW.FPGA-FAQ.COMArticle: 64982
On 16 Jan 2004 08:39:37 -0800, pbrowne0@excite.com (Patrick Browne) wrote: > I noticed that XILINX will not run in multiple instances. What does this mean? Bob Perlman Cambrian Design WorksArticle: 64983
Hi Petter, I wrote a program to convert an Srec file to a binary file and then downloaded this over a PCI/Avalon bridge. I have found my problem, which was that I assumed the Srec file was always writing a contiguous memory region, when in fact sometimes addresses are skipped, presumably for alignment optimization. > cruiser144@hotmail.com (cruzin) writes: > > > I can download a program to memory using "nios-run my_prog.srec" and > > it works fine. > > > > However, when I write the program into the same memory manually (ie. > > memory fill command), nios will not wrong the program properly. > > Maybe a stupid question: How do you run your manually entered program? > Are you using the go (G) command in germs? Can you use go to *re-run* > the downloaded srec file? > > PetterArticle: 64984
Hi, there: I tried one simulation with the following parameters to derive a 36MHz from 40MHz crystal... It works in simulation, but does it work in Virtex-2 with speed grade of 6? I am cautious as 40 * 9 makes 360MHz and it is beyond the Virtex-2's DCM timing specification. defparam DCM1.CLKFX_DIVIDE = 10; defparam DCM1.CLKFX_MULTIPLY = 9; I also tried to use a state machine to divide crystal into 4MHz and then multiply by 9, but it Model-Sim complained the input clock jitter was beyond 1ns... How may I do this task? Thanks for your advice... KelvinArticle: 64985
cruzin <cruiser144@hotmail.com> wrote in message news:775730eb.0401172120.28d24bd6@posting.google.com... > Hi Petter, > > I wrote a program to convert an Srec file to a binary file and then > downloaded this over a PCI/Avalon bridge. > > I have found my problem, which was that I assumed the Srec file was > always writing a contiguous memory region, when in fact sometimes > addresses are skipped, presumably for alignment optimization. If you have a look at the srec spec, I'm fairly sure the first data after the 's' on every line is the address that line starts at. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone based 'Easy PCI' dev board www.nialstewartdevelopments.co.ukArticle: 64986
OK. As I am probably inside the recommended spec and for granted in the the abs max spec I stop worrying. Thank you Austin, Kolja Sulimma Austin Lesea <austin@xilinx.com> wrote in message news:<bu92l9$jjb2@cliff.xsj.xilinx.com>... > All, > > The voltage drop to the part might be just about 50mV.... > > Seriously. > > I would try it an see what voltage the part actually is at relative to > the regulator. You might be pleasantly surprised. > > Remember the part is specified by Xilinx to operate at the abs max > voltage AND temperature for the rated lifetime. > > We prefer you stay within the recommended values, however. > > Austin > > fabbl wrote: > > According to the data sheet, the absolute maximum VCCINT is 1.32 volts. This > > would be 4% high side tolerence for a 1.25 V regulator. I am not aware of > > any derating Xilinx has for higher voltages with their Spartan 3 device. I > > would conclude a 1.25 V regulator would be acceptable. If you were really > > paranoid you could tweak down the regulator by adjusting the passives in the > > circuit. > > > > "Kolja Sulimma" <news@sulimma.de> wrote in message > > news:b890a7a.0401160555.6965219c@posting.google.com... > > > >>This again is a question for Austin: > >> > >>The recommended operating conditions for spartan-3 are VCCINT < 1.26V. > >>What will happen if I power it with 1.28V? > >> > >>Antything more serious than a live expectancy reduced from 20 years to > >>15 years? > >> > >>You know, there a only a few small 1.2V regulators on the market but > >>there a plenty of 1.25V versions around. But those have a tolerance of > >>a few percent... > >> > >>Kolja Sulimma > > > > > >Article: 64987
Greg Steinke <gregs@altera.com> wrote in message news:5c1de958.0401161225.534fd029@posting.google.com... > All, > There was a related thread on this topic, and I replied to it. I am > cross posting the response to this thread as well: > > The EPCS Serial Configuration Devices are programmed through a serial > interface. While the device itself does not include JTAG, we have > developed a method of programming it by JTAG by routing the data > through the Cyclone device. In short: > 1. The Cyclone FPGA is configured through JTAG. > 2. The EPCS programming data is sent from the PC to the JTAG port of > the Cyclone FPGA. This is done by Jam, so it can come from a PC, or > from a Jam player running on an embedded microprocessor. > 3. The logic in the FPGA captures data from the JTAG port of the > Cyclone FPGA, reformats it to conform to the EPCS interface, and > drives it to the EPCS device. That's all very well if you can get to the board to plug in a JTAG connector, but what if you want the ability to allow remote updates. I would like to be able to allow customers to update my Easy PCI board, over the PCI bus. This is achievable at the minute but it requires a NIOS core be permanently included in the design which uses a fair bit of the chip resource. A small core allowing the Cyclone devices to easily access the ASMI interface would be a big bonus. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone based 'Easy PCI' dev board. www.nialstewartdevelopments.co.ukArticle: 64988
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> writes: > I would like to be able to allow customers to update > my Easy PCI board, over the PCI bus. This is achievable I've done this using very little logic resources. It has a separate pci register (or even function) which has four writable bits (output enable, tck,tms, and tdi) and one readable bit (you can of course make a large buffer for efficiency). The device driver can then control this register and to drive all the jtag signals. You can then generate patterns to write to a jtag programmable configuration device, or control the scan chain of the fpga to generate a sequence to write data to a plain flash. You might want to have a mux or similar to select the jtag input from your fpga (isp controller) or from the jtag connector on the board. It's also smart to have storage for two fpga configurations so you can revert to the fail safe one in case something goes wrong, i.e. a power loss during isp etc. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 64989
andrebt@uai.com.br (Andre) wrote in news:4bfc232.0401151221.48b9724b@posting.google.com: > Hi! > I'm trying to synthecize a pic VHDL core on Altera Quartus II web > edition, but when I make changes on the ROM.vhdl(It's using Case-When > clauses), the compiler reports: > ; Total logic elements ; 0 ; > ; Total pins ; 20 ; > ; Total memory bits ; 0 ; > ; Total PLLs ; 0 > > if I don't change the rom program, it reports: > ; Total logic elements ; 2,137 ; > ; Total pins ; 20 ; > ; Total memory bits ; 0 ; > ; Total PLLs ; 0 ; > . > > > Someone can tell me why this it happen? > > Thank you, > Andre, > Student of science computer - Brazil Do you have any output pins defined for your top level?Article: 64990
What is your target? If it is an FPGA with fast carry chains, then it generally
doesn't make sense to use a CSA architecture unless it is for an educational
exercise. In most technologies, fast adders are more resource intensive than
the simplest adder (a ripple carry adder). A CSA adder tree postpones the
carry so that only one of the more expensive adders is needed; all the other
adds are just half adders. This provides the speed of a multiplier implemented
using fast adders throughout without the attendant expense. In the case of an
FPGA with a fast carry chain, the lowest cost adder (a ripple carry adder using
the fast carry chain) also happens to be the fastest, in fact with the Xilinx
architecture
the fast carry chain adders use HALF the resources one without the fast carry
chain uses because the carry half of the half adders is in dedicated logic that
is
there whether you use it or not. Since the cheapest adder in the FPGA is also
the
fastest, there is no need to resort to schemes such as a CSA (a wallace tree is
a CSA
adder tree arranged as a tree structure). The one place a CSA architecture
makes sense
with the FPGA is if you are really out there on the speed such that you are
pipelining the
carry in the adder in order to achieve the speed.
In answer to your question, the CSA connections can be generated algorithmically
and I am
sure there is something out there to do it, but I am not aware of it.
Sleep Mode wrote:
> Hi all,
>
> I am trying to design a 16-bit integer multiplier in VHDL and I want to use
> a Carry-Save-Adder (CSA) tree for generating the interim subproducts
> and -then- with an additional CPA (or other) adder to add them to the final
> 32-bit product; i.e. I want to build a full-tree multiplier.
>
> My question is whether there is some automatic (core) generator for the
> CSA-tree interconnections since it is rather complicated to do it by hand...
> If not, is there any fast method of drawing it manually (pen-and-paper) so
> that I can translate it to VHDL later on?
>
> Thanks in advance guys,
> Chris
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 64991
The CSA tree combines like weighted bits, and produces one bit of the same weight
and
one with weight * 2. Basically, just keep combining like weighted bits until there
is just
two bits of each weight, then add those with a conventional adder.
Ray Andraka wrote:
> What is your target? If it is an FPGA with fast carry chains, then it generally
>
> doesn't make sense to use a CSA architecture unless it is for an educational
> exercise. In most technologies, fast adders are more resource intensive than
> the simplest adder (a ripple carry adder). A CSA adder tree postpones the
> carry so that only one of the more expensive adders is needed; all the other
> adds are just half adders. This provides the speed of a multiplier implemented
> using fast adders throughout without the attendant expense. In the case of an
> FPGA with a fast carry chain, the lowest cost adder (a ripple carry adder using
> the fast carry chain) also happens to be the fastest, in fact with the Xilinx
> architecture
> the fast carry chain adders use HALF the resources one without the fast carry
> chain uses because the carry half of the half adders is in dedicated logic that
> is
> there whether you use it or not. Since the cheapest adder in the FPGA is also
> the
> fastest, there is no need to resort to schemes such as a CSA (a wallace tree is
> a CSA
> adder tree arranged as a tree structure). The one place a CSA architecture
> makes sense
> with the FPGA is if you are really out there on the speed such that you are
> pipelining the
> carry in the adder in order to achieve the speed.
>
> In answer to your question, the CSA connections can be generated algorithmically
> and I am
> sure there is something out there to do it, but I am not aware of it.
>
> Sleep Mode wrote:
>
> > Hi all,
> >
> > I am trying to design a 16-bit integer multiplier in VHDL and I want to use
> > a Carry-Save-Adder (CSA) tree for generating the interim subproducts
> > and -then- with an additional CPA (or other) adder to add them to the final
> > 32-bit product; i.e. I want to build a full-tree multiplier.
> >
> > My question is whether there is some automatic (core) generator for the
> > CSA-tree interconnections since it is rather complicated to do it by hand...
> > If not, is there any fast method of drawing it manually (pen-and-paper) so
> > that I can translate it to VHDL later on?
> >
> > Thanks in advance guys,
> > Chris
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 64992Hi I saw this cool project on fpga4fun on 10baseT ethernet. it's so cool needs only 2 lines. like rs-232. I like to try it, but my board has this LXT972 chip (ethernet PHY thingy, like those MAXxxxx rs-232 voltage convertor thingy) sitting between my x2cv2000 fpga and the connector. it has so many pins that i don't know what to do with them. Can someone know about voltage and stuff tell me how to do. can i rewire say 2 of the 5 rs-232 lines to be used as Ethernet_TDp and Ethernet_TDm ? thanks.Article: 64993
Alex Rast wrote:
> It does seem to me that the
> available testing options for high-speed, synchronous interfaces are very
> few and far between. The option that people have been recommending, of
> putting another identical board in our system to use as a test interface,
> is one I thought about and I think, with the consensus being that this is
> the best way to go, is what I'll do. Is this, then, the typical way people
> test high-speed cards and interfaces? I'm quite surprised that there aren't
> more testing/prototype systems available for these kinds of hardware, which
> must surely be extremely common.
One reason may be that simulation is commonly used
for design verification of synchronous logic.
-- Mike Treseler
Article: 64994Hi FPGAProto board is now available for purchase. The board has 100K gate spartan-II FPGA, 4MX16 SDRAM, prog. Oscillator, pin headers for prototyping etc. For more information go to http://www.c-nit.net Thanks SumitArticle: 64995
Patrick Browne wrote: > I would like to have 4 to 9 FPGAs running at once. Consider designing the system using an HDL with a separate entity/module for each FPGA. For functional simulation you may instance as many entities as you like into a single testbench. > I noticed that XILINX will not run in multiple > instances. Wait until your functional simulation work is complete before you attempt synthesis. With a properly synchronized design, code and netlist sims should work the same. -- Mike TreselerArticle: 64996
Cornel Arnet wrote:
> # ** Fatal: (vsim-7) Failed to open VHDL file "A()" in rb mode.
> # No such file or directory. (errno = ENOENT)
> # Time: 0 ns Iteration: 0 Process:
> /mydesign/inst6_alpm_instance_adp0_adpram/clock File:
> C:/quartus/eda/sim_lib/apex20ke_atoms.vhd
> # FATAL ERROR while loading design
> # Error loading design
>
> Anybody can help?
Parenthesis are not allowed in a VHDL filename.
Consider siming your source level before gate level.
-- Mike Treseler
Article: 64997
Nick Suttora wrote:
> the simulation time required, however it still takes about 1 hour per
> millisecond of simulation time. Other than getting a faster computer
> are there any other things that can be done to reduce the simulation
> time? I have already removed high frequency signals (clocks) from the
> simulator waveform window and used variables where possible.
Consider siming your source level before gate level.
That's about ten times faster.
-- Mike Treseler
Article: 64998Sounds reasonable. Jean "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:bu43s0$vcl$1@news.tu-darmstadt.de... > Jean Nicolle <j.nicolle@sbcglobal.net> wrote: > : Allan, did you get my email yesterday? I sent you a few screenshots. > > : Anyway: > : 1. is fixed. > > : 2. and 3. > : Looks like the way to meet the spec is to buy an isolation transformer and > : follow the apps notes, a good source seems to be http://www.pulseeng.com/, > : so it should be just a matter to buy these. > > An old 10 MBit card might be a good source for the transformer.. > > ... > > : > > 4. The receiver may work better with a 120ohm (or so) resistor > ... > > Please don't fullquote. It only fills up the archive with redundancy... > > Bye > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 64999
Yes, there are lots of manufacturers of magnetics. I found this page http://www.interfacebus.com/inductors_transformers.html About the reflection, since this particular experiment is an emitter only, I'm relying on the other end device (an Ethernet switch) to do proper termination (which it does, according to my measurements). Once I work further on the receiver part, I certainly need to pay attention to terminating the lines i.e. putting a resistor across the pair. Thanks. Jean (and I remembered not to fullquote this time).
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z