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Well, there's no file named "A()" ...and I've already done the source level simulation. Cornel Arnet "Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message news:400AEA95.2050309@flukenetworks.com... > Cornel Arnet wrote: > > > # ** Fatal: (vsim-7) Failed to open VHDL file "A()" in rb mode. > > # No such file or directory. (errno = ENOENT) > > # Time: 0 ns Iteration: 0 Process: > > /mydesign/inst6_alpm_instance_adp0_adpram/clock File: > > C:/quartus/eda/sim_lib/apex20ke_atoms.vhd > > # FATAL ERROR while loading design > > # Error loading design > > > > Anybody can help? > > Parenthesis are not allowed in a VHDL filename. > Consider siming your source level before gate level. > > -- Mike Treseler >Article: 65051
In qu@rtus I could not find how to change the memory initialization file during simulation without re-compile. As I remembered, in Max-Plus you just need to reload the new .mif file, no need to re-compile the project. Who knows how to do it in qu@rtus? Thx a lot.Article: 65052
On Mon, 19 Jan 2004 12:01:55 -0800, Ted wrote: > I have to make a change to a XC4005pc84-5 part but I don't have the tools that > support XC4000 parts. I've gone all the way back to Alliance Series 1.5i > and XC4000E's are supported but not XC4000's. I believe I need an old set > of M1 tools but I don't know where to find them. Does anyone know where I > can get an old set of Xilinx tools that can supports XC4000 parts (not > XC4000E parts). > > Thanks for any info. > > Ted You probably need the XACT tools, if the 4000s weren't supported in 1.5 then they probably weren't supported in M1 either.Article: 65053
Hi guys, I was wondering if there were any good starter kits you know of and where I am able to purchase them, I want to dip into VHDL a bit and try out my creations on a FPGA, nothing too fancy as I'm no engineer, just a hobbyist :) I saw one on Xilinx's online store for ~$50 US is that a good choice?Article: 65054
I believe you need the Classic package. http://www.xilinx.com/webpack/classics/wpclassic/index.htm Steve -- CONFIDENTIALITY NOTICE This communication (and/or the documents accompanying it) may contain privileged or other confidential information. If you are not the intended recipient, you are hereby notified that any use, disclosure, copying, distribution or the taking of any action in reliance on the contents of this information is strictly prohibited. If you have received it in error, please advise the sender by reply e-mail and immediately delete the message and any attachments without copying, using or disclosing the contents. Thank you for your cooperation. "Ted" <tfrankli_1@yahoo.com> wrote in message news:b81b4ee0.0401191201.6ecdd41b@posting.google.com... > I have to make a change to a XC4005pc84-5 part but I don't have the tools that > support XC4000 parts. I've gone all the way back to Alliance Series 1.5i > and XC4000E's are supported but not XC4000's. I believe I need an old set > of M1 tools but I don't know where to find them. Does anyone know where I > can get an old set of Xilinx tools that can supports XC4000 parts (not > XC4000E parts). > > Thanks for any info. > > TedArticle: 65055
I'm successfully using Chipscope Pro with a Microblaze system, but I'm using UART Lite instead of JTAG UART. Change the UART and enjoy the nice waveforms that Chipscope produces (it took me some time to learn how to use Chipscope though, but it was worth it in the end). Cheers Johan "Antti Lukats" <antti@case2000.com> wrote in message news:80a3aea5.0401191153.121c251a@posting.google.com... > > Has anybody tried Chipscope Pro with a MicroBlaze based system? > > > > I am using JTAG-Uart for debugging purposes and now I want to use > > ChipScope Pro at the same time, but when I try to implement it > > generates an error with BSCAN. > > > >I know that JTAG-Uart uses a BSCAN and ChipScope also needs another > >one. If I take out the JTAG-Uart from the design it works. > > There is single BSCAN per FPGA, > that BSCAN instance has two "user" instructions. > > If either JTAG UART or ChipScope uses both user instructions then > it most likely is nogo with JTAG Uart and ChipScope at the same > time, if both use only one user instruction then it could at > least theoretically be possible. But I think it is not possible > at this time. > > Ok, I can confirm at current time it is not possible: if you > look at opb_jtag_uart RTL sources you see that even it is > using only one user instruction from the 2 available ones > it uses the BSCAN instance in a way that it can not be > shared with Chipscope, > > and second - even it would worked, I think XMD and ChipScope > can not share the JTAG interface so it wouldnt work anyway > > antti > xilinx.openchip.orgArticle: 65056
arkagaz@yahoo.com (arkaitz) wrote in message news:<c1408b8c.0401190708.4e21862a@posting.google.com>... > Has anybody tried Chipscope Pro with a MicroBlaze based system? Yes we have done this many times. > I am using JTAG-Uart for debugging purposes and now I want to use > ChipScope Pro at the same time, but when I try to implement it > generates an error with BSCAN. Only one application can take ownership of the JTAG cable and attached BSCAN component, so to be clear, you can create a single netlist that will work with both applications, but you can not have both applications using the cable simultaneously. > I know that JTAG-Uart uses a BSCAN and ChipScope also needs another > one. If I take out the JTAG-Uart from the design it works. You need to generate the Chipscope ICON core without a BSCAN component. This is a checkbox in the GUI. There will be a number of new signals on the ICON component that then need to be attached to the BSCAN component that has already been instantiated in the opb_jtag_uart. The jtag_uart uses scan chain 2, so scan chain 1 is available for chipscope. I would highly recommend adding a BUFG to the BSCAN DRCK2 signal in the OPB_JTAG_UART when making the modifications, as we saw rather flaky behavior from the core (without floorplanning to account for local clocking). A BUFG was the easiest solution for us, as we had plenty of them left. Unfortunately, we can not distribute the code for our modified OPB_JTAG_UART without permission of Xilinx, as it is based on their copyrighted code. Fortunately there is now source code in EDK 6.1i, so the instructions herein should be sufficient. The MicroBlaze team does have our code, but has not chosen to include it in the distribution. Regards, Erik Widding. --- Birger Engineering, Inc. -------------------------------- 617.695.9233 100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.comArticle: 65057
> > p.s. does it matter for routing if i organise my modules in columns or > rows, assuming they span the entire column/row? does it affect the > time it takes to route an area which spans the breadth of the device > rather than the height? It is better to line up your muxes vertically. That is how the configuration memory is set up. If you put your muxes all across the top, for example, You will have to reload the whole device. If you line them up along a set of columns then you only have to reconfigure the columns (not counting any routes that go across horizontally). SteveArticle: 65058
Jonathan Bromley wrote: > ISTR that the programming algorithm for PALCE devices was > reasonably straightforward, so you could probably do > something home-grown - maybe using some of your newly- > found PALs in its logic :-) Is this algorithm documented somewhere ?? The data sheet I found does not mention any algorithm. I have picked Atmel ATF1504 as a replacement device. ThanksArticle: 65059
Actually, this is close to correct. Nothing is "multiplied". The 40 MHz reference clock will be divided by 10 to reach 4 MHz. The output will be divided by 9 to give 4 MHz. The two signals at 4 Mhz are compared at the phase comparator to control the oscillator. But you do have to assure that 4 MHz is within the range that the phase comparator can work. symon wrote: > > Hi Kelvin, > This should work fine, the DCM multiplies and divides at the same time (in > simplistic terms) so the spec isn't exceeded. > cheers, Syms. > > "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message > news:bud50h$9ab$1@reader01.singnet.com.sg... > > Hi, there: > > > > I tried one simulation with the following parameters to derive a 36MHz > from > > 40MHz crystal... > > It works in simulation, but does it work in Virtex-2 with speed grade of > 6? > > I am cautious as > > 40 * 9 makes 360MHz and it is beyond the Virtex-2's DCM timing > > specification. > > > > defparam DCM1.CLKFX_DIVIDE = 10; > > defparam DCM1.CLKFX_MULTIPLY = 9; > > > > I also tried to use a state machine to divide crystal into 4MHz and then > > multiply by 9, but it Model-Sim > > complained the input clock jitter was beyond 1ns... > > > > How may I do this task? > > > > Thanks for your advice... > > KelvinArticle: 65060
Kolja Sulimma wrote: > > > > > A friend told me that the 50,000 piece price on the slowest XC3S400 in > > the FG456 package would be around $20. The press releases are talking > > about the "smallest" package and 250,000 quantities giving a price > > around $5. I don't know what the "smallest" package is, but I would > > like to meet the guy who is getting the $5 price. > > And from my last insight quote for the xc3s200 the smallest package is > three Euro more expensive than the FT256 > (VQ100 is smaller both in dimension and in pincount than FT256) Maybe the mean "smallest" in price?Article: 65061
Try constraining them to particular places. Depending on your
constraints, it may be taking the placer some time to come up with a
satisfactory placement, or may be taking the router a long time to route
the mess the placer made. Also, you'll want to organize them as a column
to minimize the reconfiguration time (reconfig happens by column), as well
as to match up to any arithmetic you might have in the design.
Nachiket Kapre wrote:
> Hi,
> I am currently having a design with multiple reconfigurable modules
> implemented as separate edifs. I've followed to modular design
> instructions from the xilinx documentation and have managed to get
> ngdbuild and map to work fine on all my modules. When I try to do a
> PAR, after the placement is done, the router takes 15 minutes to start
> dumping results onto the console. But, once it starts routing, the
> process seems to finish off in a couple of seconds. The design it is
> trying to route is a collection of 8 2:1 multiplexers. I dont see why
> it should take 15 minues for such a small design. The area constraints
> for the design also seem to be correct. Any ideas why the long
> runtimes?
>
> device = xc2v6000
>
> p.s. does it matter for routing if i organise my modules in columns or
> rows, assuming they span the entire column/row? does it affect the
> time it takes to route an area which spans the breadth of the device
> rather than the height?
>
> regards,
> nachiket.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 65062What libraries would that be? Isn't FPGA editor their own product? Or is there something not *free* about Linux? BTW, to Kelvin, since when does WebPack provide support for modular configuration? I would love to know because I would like to use it. But then I really don't mind paying $500 for a tool like this. John_H wrote: > > Doesn't Xilinx need to pay a per-seat royalty for the libraries that provide > the capabilities you're lamenting? > > Lets all get something free from someone who has to pay for it !!! > > "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message > news:bucl4a$vm4$1@reader01.singnet.com.sg... > > sighhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhhh :-( > > > > > > "Stephen Williams" <spamtrap@icarus.com> wrote in message > > news:a36f$40086bdb$40695902$18612@msgid.meganewsservers.com... > > > Kelvin @ SG wrote: > > > > Hi, there: > > > > > > > > I am using ise WebPack for learning purpose. I am learning modular > > design > > > > while > > > > I can't live without the FPGA Editor...even if a viewer is okie... > > > > > > > > I used ISE w6.1.03, but there is no editor on it. > > > > > > > > May I know which version has this functionality on it? > > > > > > No versions of WebPack have FPGA Editor. You need a for-money > > > version to get it. > > > > > > (My other gripe: No versions of WebPack support Linux native. Grumble.) > > > > > > > > > -- > > > Steve Williams "The woods are lovely, dark and deep. > > > steve at icarus.com But I have promises to keep, > > > http://www.icarus.com and lines to code before I sleep, > > > http://www.picturel.com And lines to code before I sleep." > > > > > > >Article: 65063
Yeah, but can you get CPLDs in QFN packages??? Sometimes a "little" logic goes a long way. :) Too bad we can't get any sort of FPGA in a physically small package. I could do a lot with a 100 LEs (or 50 slices) in a TQFP32/48 or a QFN32/48. The new tiny packages are really amazing. I know I am not alone, but it seems we are not running with the herd. Peter Alfke wrote: > > The 22V10 originated at AMD (I was there!), but later became the > "standard" for high-end PALs. You can find it with anybody who (still) > makes PALs. Try Lattice, TI, NSC... > There are bipolar and CMOS versions, sharing the same functionality and > pin-out, but obviously not the programming. > The 22V10 dates back to the early 'eighties. That's 20 years ago. At my > analogy of 15 human years per 1 programmable logic year, these 22V10s > are 300-year-old "senior citizens". Using them for a new design would > be silly (inhumane?). > One cheap CPLD runs circles around several 22V10s, and CoolRunner CPLDs > consume almost no power... > Peter Alfke > ======================== > hamilton wrote: > > > > I have found a tube of these AMD parts from on old project. > > > > AMD no longer manufactures these parts. Does anyone know who > > picked up these parts from AMD ? > > > > I am also looking for a simple programmer for these parts. > > > > I have found $500+ programmers out on the net, but I would like > > to keep it cheap. > > > > Thanks for any info. > > > > hamiltonArticle: 65064
Ted wrote: > > I have to make a change to a XC4005pc84-5 part but I don't have the tools that > support XC4000 parts. I've gone all the way back to Alliance Series 1.5i > and XC4000E's are supported but not XC4000's. I believe I need an old set > of M1 tools but I don't know where to find them. Does anyone know where I > can get an old set of Xilinx tools that can supports XC4000 parts (not > XC4000E parts). > > Thanks for any info. Are you sure they aren't bitstream compatible? I seem to recall that a lot of different XC4000xxx families used the same bit stream, they just used different voltages, etc.Article: 65065
x86asm wrote:
> Hi guys, I was wondering if there were any good starter kits you know of
> and where I am able to purchase them, I want to dip into VHDL a bit and
> try out my creations on a FPGA, nothing too fancy as I'm no engineer,
> just a hobbyist :) I saw one on Xilinx's online store for ~$50 US is
> that a good choice?
>
Unless you just want to just run the canned demos,
I would suggest that you defer picking a device or buying
a board until you learn some vhdl language for synthesis
and simulation.
Work with modelsim or sonata until you have some synth code
and a working simulation testbench for your creation.
-- Mike Treseler
Article: 65066Here is what I wrote for the 1998 data book: "Any XC4000E device is pin-out and bitstream-compatible with the corresponding XC4000 device. An existing XC4000 bitstream can be used to program an XC4000E device, but since the XC4000E includes many new features, an XC4000E bitstream cannot be loaded into an XC4000 device." And X000EX and -XL are all derived from ther XC4000E... So this means, you need XC4000-type software, and we are looking into that... Peter Alfke, Xilinx Applications =========================== Ralph Malph wrote: > > Are you sure they aren't bitstream compatible? I seem to recall that a > lot of different XC4000xxx families used the same bit stream, they just > used different voltages, etc.Article: 65067
at Sun, 18 Jan 2004 19:58:02 GMT in <400AE54A.3050405@flukenetworks.com>, mike.treseler@flukenetworks.com (Mike Treseler) wrote : >Alex Rast wrote: >> ...The option that people have been >> recommending, of putting another identical board in our system to use >> as a test interface... is what I'll do. Is >> this, then, the typical way people test high-speed cards and >> interfaces? I'm quite surprised that there aren't more >> testing/prototype systems available for these kinds of hardware, which >> must surely be extremely common. > >One reason may be that simulation is commonly used >for design verification of synchronous logic. That's a nice thought, but sooner or later, simulation must give way to actual testing. There's only so much you can confirm through simulation, and at some point, you have to try the real hardware and see what it actually does. I must also point out that there are certain types of circuits that are difficult, sometimes even impossible, to simulate, not to mention others that may be easy to set up but take forever to run even on fast machines. Simulation is an important and valuable first step, but IMHO it would take a rather credulous engineer to put his entire trust in the siumulation results. -- Alex Rast ad.rast.7@nwnotlink.NOSPAM.com (remove d., .7, not, and .NOSPAM to reply)Article: 65068
ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0401182339.27407c4f@posting.google.com>... > Dear Sir or Madam, > > I want to simulate a VHDL design. It includes RAM structures > with .mif files (memory initialization files in QuartusII). > Modelsim seems not to support that kind of files. > So I use .hex files. > In QuartusII they can be included in the MegaWizard- > PlugInManager. > But how do I involve these .hex files when simulating in Modelsim? > Do they have to be compiled additionally to the > design VHDL files or do they have to be linked to in the testbench? > When trying to simulate after compiling the VHDL modules I get > an error message "Fatal error ... altera_mf.vhd ... not found". > > Kind regards > Andres Vazquez > G & D > System Development If you have used the Megawizard PlugIn Manager and specified that the memory should be initialized along with the correct hex file, there is no additional step needed, to specify the memory files to Modelsim. You can verify this by opening the VHDL or Verilog file written out the Megawizard and check the INIT_FILE parameter. Its value should be the path to the hex file. If you are using Modelsim SE/PE then use the following vcom commands in Modelsim (This is taken from the Quartus online help) For VHDL 87-compliant designs: vcom -work work <path to library>\220pack.vhd vcom [-87] -explicit -work work <path to library>\220model_87.vhd vcom -work work <path to library>\altera_mf_components.vhd vcom [-87] -work work <path to library>\altera_mf_87.vhd vcom -work work <design name>.vhd vcom -work work <test bench>.vhd For VHDL 93-compliant designs: vcom -93 -work work <path to library>\220pack.vhd vcom -explicit -work work <path to library>\220model.vhd vcom -work work <path to library>\altera_mf_components.vhd vcom -93 -work work <path to library>\altera_mf.vhd vcom -work work <design name>.vhd vcom -work work <test bench>.vhd where path to library would look like d:\quartus30\eda_simlib. Hope this helps. - Subroto Datta Altera Corp.Article: 65069
Close, but no cigar. You can use any combination of input frequency, M, and D, as long as the output frequency is above 24 MHz, and does not exceed the max, somewhere around 400 MHz.( M and D each cannot exceed 32 ). The phase comparator is never the limitation. Peter Alfke, Xilinx Applications Ralph Malph wrote: > > Actually, this is close to correct. Nothing is "multiplied". The 40 > MHz reference clock will be divided by 10 to reach 4 MHz. The output > will be divided by 9 to give 4 MHz. The two signals at 4 Mhz are > compared at the phase comparator to control the oscillator. But you do > have to assure that 4 MHz is within the range that the phase comparator > can work. > > symon wrote: > > > > Hi Kelvin, > > This should work fine, the DCM multiplies and divides at the same time (in > > simplistic terms) so the spec isn't exceeded. > > cheers, Syms. > > > > "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message > > news:bud50h$9ab$1@reader01.singnet.com.sg... > > > Hi, there: > > > > > > I tried one simulation with the following parameters to derive a 36MHz > > from > > > 40MHz crystal... > > > It works in simulation, but does it work in Virtex-2 with speed grade of > > 6? > > > I am cautious as > > > 40 * 9 makes 360MHz and it is beyond the Virtex-2's DCM timing > > > specification. > > > > > > defparam DCM1.CLKFX_DIVIDE = 10; > > > defparam DCM1.CLKFX_MULTIPLY = 9; > > > > > > I also tried to use a state machine to divide crystal into 4MHz and then > > > multiply by 9, but it Model-Sim > > > complained the input clock jitter was beyond 1ns... > > > > > > How may I do this task? > > > > > > Thanks for your advice... > > > KelvinArticle: 65070
Perhaps I should quote the passage: " Two attributes, set at design time, control the synthesized output frequency. The CLKIN clock input is multiplied the fraction formed by CLKFX_MULTIPLY as the numerator and CLKFX_DIVIDE as the denominator. For example, to create a 155MHz output using a 75MHz CLKIN input, the Frequency Synthesizer multiplies CLKIN by the fraction 31/15. Note that it does not multiply CLKIN by 31 first, then divide by the result by 15. Multiplying CLKIN by 31 would result in a 2.325GHz output frequency-well outside the frequency range of the Spartan-3 DCM." "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:buh78s$jjd1@cliff.xsj.xilinx.com... > See page 54, second paragraph in XAPP462: Using Digital Clock Managers > (DCMs) in Spartan-3 FPGAs. > http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf > > -------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > General Products Division > Spartan-3/II/IIE FPGAs > http://www.xilinx.com/spartan3 > --------------------------------- > Spartan-3: Make it Your ASIC > > "Peter Alfke" <peter@xilinx.com> wrote in message > news:400C191A.6C001E1D@xilinx.com... > > Just to confirm it officially: > > In frequency synthesis mode, M/D is done as a combined mathematical > > operation. Therefore it is irrelevant that the multiplication by itself > > might exceed the max frequency. I remember publishing this in several > > places, but cannot find it right now. It is one of the major nice > > features of the DCM. > > > > Peter Alfke, Xilinx Applications > > ================ > > Antti Lukats wrote: > > > > > > " > > > RTFM, RTFM, RTFM > > > there is somewhere a notice in datasheets that the DCM can be used > > > in such situation where the virtual CLK is way beyound operating > > > frequency, the DCM will still work. > > > > > > So you should be safe, using the DCM with those parameters as given. > > > > > > > >Article: 65071
Hi, All: Thank you very much for your replies. I understand it now and I will try it out. Best Regards, Kelvin Steven K. Knapp <steve.knappNO#SPAM@xilinx.com> wrote in message news:buhvu1$26l2@cliff.xsj.xilinx.com... > Perhaps I should quote the passage: > > " > Two attributes, set at design time, control the synthesized output > frequency. The CLKIN clock input is multiplied the fraction formed by > CLKFX_MULTIPLY as the numerator and CLKFX_DIVIDE as the denominator. For > example, to create a 155MHz output using a 75MHz CLKIN input, the Frequency > Synthesizer multiplies CLKIN by the fraction 31/15. Note that it does not > multiply CLKIN by 31 first, then divide by the result by 15. Multiplying > CLKIN by 31 would result in a 2.325GHz output frequency-well outside the > frequency range of the Spartan-3 DCM." > > "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message > news:buh78s$jjd1@cliff.xsj.xilinx.com... > > See page 54, second paragraph in XAPP462: Using Digital Clock Managers > > (DCMs) in Spartan-3 FPGAs. > > http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf > > > > -------------------------------- > > Steven K. Knapp > > Applications Manager, Xilinx Inc. > > General Products Division > > Spartan-3/II/IIE FPGAs > > http://www.xilinx.com/spartan3 > > --------------------------------- > > Spartan-3: Make it Your ASIC > > > > "Peter Alfke" <peter@xilinx.com> wrote in message > > news:400C191A.6C001E1D@xilinx.com... > > > Just to confirm it officially: > > > In frequency synthesis mode, M/D is done as a combined mathematical > > > operation. Therefore it is irrelevant that the multiplication by itself > > > might exceed the max frequency. I remember publishing this in several > > > places, but cannot find it right now. It is one of the major nice > > > features of the DCM. > > > > > > Peter Alfke, Xilinx Applications > > > ================ > > > Antti Lukats wrote: > > > > > > > > " > > > > RTFM, RTFM, RTFM > > > > there is somewhere a notice in datasheets that the DCM can be used > > > > in such situation where the virtual CLK is way beyound operating > > > > frequency, the DCM will still work. > > > > > > > > So you should be safe, using the DCM with those parameters as given. > > > > > > > > > > > > > >Article: 65072
You may look at the Avnet's Spartan-3 promotion...The brochure claims buying one demo board get one free later, at 95US$...but I don't know who is elligible to that promo... Best Regards, Kelvin Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:400C5E31.802@flukenetworks.com... > x86asm wrote: > > Hi guys, I was wondering if there were any good starter kits you know of > > and where I am able to purchase them, I want to dip into VHDL a bit and > > try out my creations on a FPGA, nothing too fancy as I'm no engineer, > > just a hobbyist :) I saw one on Xilinx's online store for ~$50 US is > > that a good choice? > > > > Unless you just want to just run the canned demos, > I would suggest that you defer picking a device or buying > a board until you learn some vhdl language for synthesis > and simulation. > > Work with modelsim or sonata until you have some synth code > and a working simulation testbench for your creation. > > -- Mike Treseler >Article: 65073
Ralph Malph wrote: > Yeah, but can you get CPLDs in QFN packages??? Sometimes a "little" > logic goes a long way. :) > > Too bad we can't get any sort of FPGA in a physically small package. I > could do a lot with a 100 LEs (or 50 slices) in a TQFP32/48 or a > QFN32/48. The new tiny packages are really amazing. > > I know I am not alone, but it seems we are not running with the herd. All it takes is enough noise to convince the vendors to add the smaller packages - it's not a massive investment, mainly a mindset problem - 'We don't do that because no one buys them'. The SPLD/CPLD market is in 'follow mode', but the Microcontrollers and Logic have by now widely deployed QFN, and lattice have recently added QFN in 22V10, and TQFP48 in CPLD. So the other, more sluggish, vendors will follow eventually.... Some will claim BGA is their small package solution, but they miss the point that cannot go onto single sided PCB. > Peter Alfke wrote: > >>The 22V10 originated at AMD (I was there!), but later became the >>"standard" for high-end PALs. You can find it with anybody who (still) >>makes PALs. Try Lattice, TI, NSC... >>There are bipolar and CMOS versions, sharing the same functionality and >>pin-out, but obviously not the programming. >>The 22V10 dates back to the early 'eighties. That's 20 years ago. At my >>analogy of 15 human years per 1 programmable logic year, these 22V10s >>are 300-year-old "senior citizens". Using them for a new design would >>be silly (inhumane?). Sweeping statements are dangerous.... We still use 16V8's for new designs, because of their price/size. Poor CPLD package offering is one problem slowing the replcaement of 22V10 : There are many sockets where your '300 year old' analogy has no more modern physical replacement. There are cost equivalents, but not physical equivalents, and I call that 'a little blinkered' -jgArticle: 65074
hmurray@suespammers.org (Hal Murray) wrote in message news:<100fc784surjk85@corp.supernews.com>...
>
> >I can't live without the FPGA Editor...even if a viewer is okie...
> >I used ISE w6.1.03, but there is no editor on it.
>
> What are you trying to look at?
>
> You may be able to get some of the info you want from the floorplanner.
> It doesn't show you a detailed wiring, but it does show you the main
> blocks.
>
The latest Webpack versions now include XDL, Xilinx's nifty ASCII FPGA
{dis}assembler, which let you examine/create a ncd file in ASCII form.
Look in %XILINX%\help\data\xdl
Brian
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