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"Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message news:400DBD0E.6080303@flukenetworks.com... > Save some sort of CRC hash with each value push. > Apply correction(hash) when a value is popped. I applied this method in the original design (on a pc), but it is not deterministic - a value could change several times before it emerges from the fifo, resulting in multiple indexes into an array to find the ultimate answer. I can e-mail or post snippets of code to explain this better. I tried building my own fifo, which took an input value, compare value, and change value. Upon inserting the input value in the fifo, if any of the values in the fifo were equal to the compare value, they were updated to the change value. Given the depth requirements of the fifo, this implementation will not fit in the fpga I am currently using. I like the idea of not indexing into the fifo, and just applying some sort of correction to the value that is removed, but there will need to be some way of correcting that value in one cycle, to maintain deterministic performance. PatrickArticle: 65126
So does this mean from now on if I reply to a query for a proto/starter board, you will start beating me :) Sumit "Antti Lukats" <antti@case2000.com> wrote in message > you already posted to this newsgroup that you have a protoboard for sale > as you have noticed your posting hasnt got any replies. Trying to push > your ad for your board again, doesnt make it better for your sales.Article: 65127
Mike Treseler wrote: > BrakePiston wrote: > >> Hi there, I am trying to gain a deeper understanding of the way >> testing is conducted on FPGA devices. I am interested in BIST testing >> for dynamic faults, not manufacturing testing. Can you clarify what you mean by 'dynamic fault' - is this a failure to config, or a timing violation, or ?? > > > FPGA *devices* are tested at the factory. > The FPGA design function is tested using simulation. > Dynamic faults are eliminated by using > synchronous design style and by meeting static timing requirements. and by regular updates to the device speed/timing files, that the simulation SW engine uses :) >> >> My question is: how exactly can you apply a test vector (or even just >> a 1 or 0) to an interconnect line? Can you just connect the output of >> a LUT to the wire and observe the output? Some FPGA SW allows a 'flying probe' to be compiled with the design, rather like the 'Scope probe onto a PCB with a sea of TTL gates' many years ago. Mainly used for early design cycle debug problems. You design can (should?) also include test modes, allowing things like preload and readback. For example, if your FPGA is a slave to a Micro, it can be usefull for POST (and debug) uses to include read-back even of write registers. Slightly more logic is used, but rarely does that bump you into the next device. > > > In theory you can shift any pattern you like into the boundary scan > registers on any compliment device. In practice, this requires lots > of software to do anything useful. Here we license boundary scan software, > but use it only in production for the purpose of > finding solder opens and shorts on circuit boards. > >> I am asking this because of all the documentation I have read, nobody >> mentions where they get the test vectors from. >> >> Am i just being stupid and failing to see the obvious here? > > > I expect that the number of people actually doing functional test > of fpgas using boundary scan vectors is near zero. It would be > very difficult and very slow. We do Physical Vector Test a lot with SPLD/CPLD designs, but the FPGAs have a slightly different feature mix. FPGAs have much higher logic/pin ratios, and the high reliance on simulation puts pressure on the vendors to get the simulation files right asap. -jgArticle: 65128
Patrick Klacka wrote: > "Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message > news:400DBD0E.6080303@flukenetworks.com... > > >>Save some sort of CRC hash with each value push. >>Apply correction(hash) when a value is popped. > > > I applied this method in the original design (on a pc), but it is not > deterministic - a value could change several times before it emerges from > the fifo, resulting in multiple indexes into an array to find the ultimate > answer. I can e-mail or post snippets of code to explain this better. > > I tried building my own fifo, which took an input value, compare value, and > change value. Upon inserting the input value in the fifo, if any of the > values in the fifo were equal to the compare value, they were updated to the > change value. Given the depth requirements of the fifo, this implementation > will not fit in the fpga I am currently using. > > I like the idea of not indexing into the fifo, and just applying some sort > of correction to the value that is removed, but there will need to be some > way of correcting that value in one cycle, to maintain deterministic > performance. Yes, this would avoid the many-compares needed on change in-situ, and could suit FPGA structures. Assuming a byte wide FIFO, you could use 256 x 8 SyncRAM as the check/replace -> init to Value==Index for nochange, and then change contents as needed. It does presume only one replace value is valid/alive for all FIFO content. ( ie a delta to 'Change-to' applies from that instant, to all FIFO change-froms.) -jgArticle: 65129
I'm a consultant/contractor. A new customer is requiring me to carry commercial general liability coverage, including contractual liability (errors and omissions). I carried a $1M policy from Hartford for several years, but let it lapse in '02 after customers quit insisting on it. I paid $500/yr back then. Any recommendations, and what should I expect to pay? I'm in California. Thanks, Robert (real email: rsefton@nextstate.com)Article: 65130
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<400D7312.1090304@flukenetworks.com>... > g. giachella wrote: > > I have launched the place & route of the same project on two different > > machines, a PC 2.6 GHz (WIN 2000) and a COMPAQ XEON 700 MHz > > Workstation (WIN NT 4). Same project means same .vhd, .edf, .csf, > > .psf, .ssf, .esf, .quartus files. > > The QUARTUS release is the same (same build, same SP). > > I obtained two different placements and two different compile times > > (PC = 1h 40 min, Workstation = 5h 22 min): the file ..fit.rpt > > evidences that the options "Use Local Routing Input" and "Use Local > > Routing Output" were set differently between them during the > > compilation. > > As the project are the same and the seed is also the same, I would > > expect identical place and route. > > > > Any comment ? Am I missing somenthing ? > > Your win2k box is faster than your nt box. > > Lets assume that place & route is mostly compute bound. > In that case, if I didn't know the answer, I would > estimate the NT test time as: > > (100 min) (2.6/.7) = 371 min = 6 hours > > > So you are doing better than I would expect. > > > -- Mike Treseler The different compile time is just CPU speed differences, as Mike explained. For the different placement and routing, I can only think of two things: 1. You changed some option without realizing it between the two compiles. Are "Use Local Routing Input" and "Use Local Routing Output" options you set for the compiler, and you're saying they have different values in the two fit.rpt files? If so, that indicates you have unintentionally changed a setting between the two compiles, which would explain the different place and route. 2. We have occasionally gotten different fits on different versions of Windows due to things like qsort breaking ties differently in different windows versions. A slight difference at one point in the compile leads to a different fit on the two platforms. Both are valid fits; they are just different. As we find these cases, we get rid of them by doing things like writing our own qsort that breaks ties in a deterministic way. So it's rare, but we do find these cases. Regards, Vaughn AlteraArticle: 65131
Hayder Mrabet <hayder.mrabetNOSPAM@lip6.fr> wrote in message news:<pan.2004.01.19.17.19.32.297377@lip6.fr>... > Hi everyone, > > 1. Where can i find a free Version of Quartus on Linux OS. > I would like to test it. There's no free version on the web for Linux. But for educational use I should be able to get you a full Quartus Linux license. I'll contact you by email. > 2. is there any chance to apply QUIP's softwares on architectures > that are other than Altera's devices.( Academic tools SIS+VPR allow this) No, QUIP interfaces to Quartus, which only supports Altera's architectures. So SIS + VPR still have their place for exploring totally different architectures. > Thanks in advance > --Article: 65132
x86asm <isaac_8e@hotmail.com> wrote in message news:<45YOb.12249$7JB1.3852@news04.bloor.is.net.cable.rogers.com>... > Hi guys, I was wondering if there were any good starter kits you know of > and where I am able to purchase them, I want to dip into VHDL a bit and > try out my creations on a FPGA, nothing too fancy as I'm no engineer, > just a hobbyist :) I saw one on Xilinx's online store for ~$50 US is > that a good choice? See http://www.altera.com/products/devkits/kit-dev_platforms.jsp for a listing of Altera's development boards. The $99 7K board and $195 Cyclone board are good choices for someone on a budget. The Cyclone board has a better (bigger & faster) FPGA on it, but for hobby projects you likely want to focus at least as much on the board I/O capabilities as you do on the FPGA on the board. So it's good to look at the list of what's on the board and see if it meets your I/O needs. As other posters have pointed out, there's no shortage of dev kits at pretty low prices out there. The cheapest solution of all to get some experience is just to download a CAD suite and start synthesizing & simulating without a development kit. You can get the web edition of Quartus for free from http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmain.html. Regards, Vaughn AlteraArticle: 65133
"Robert Sefton" <rsefton@abc.net> wrote in message news:buku7v$ibgbo$1@ID-212988.news.uni-berlin.de... > I'm a consultant/contractor. A new customer is requiring me to carry > commercial general liability coverage, including contractual liability > (errors and omissions). I carried a $1M policy from Hartford for several > years, but let it lapse in '02 after customers quit insisting on it. I > paid $500/yr back then. Any recommendations, and what should I expect to > pay? I'm in California. > > Thanks, > > Robert > (real email: rsefton@nextstate.com) > Robert, We've can't get General & E&O from the same carrier, so we split it up. Our general is about $500/yr, but the E&O is about $6000/yr through the IEEE. If you find a way to get this type coverage for less, please let me know. BlakeArticle: 65134
bread_pitt@web.de (Patrick Birger) wrote in message news:<4454c7b.0401201545.1341dbc4@posting.google.com>... > Rene Tschaggelar <none@none.none> wrote in message news:<22121bd70e95748cc78f4729260a05bb@news.teranews.com>... > > > > have a look at http://www.ebv.com for the Altera parts. > > Thanks for the address. I've called them: same problem as with > "Spoerle" > 1. They only sell to companies, not to private persons. > 2. Their minimum package quantity is in general 30-90. But I don't > want to order some 50 FPGAs, 10$ each. > > Is it impossible to buy a single altera FPGA chip without founding a > company?? > > Patrick distributors DO sell in "sample" quantity if asked too. but yes, for some items minimum quantity is "tube" www.digikey.com is greate for small quantity also with pricing as example small quantity Xilinx pricing at digikey is almost 1:1 same as from disti (disti may give 5% lower price) well with digikey shipping and tax applies so small quantity goes more expensive. I think this applies to other similar catalog companies as well :( www.jopdesign.com had some ACEX chips overleft you could ask Martin antti xilinx.openchip.orgArticle: 65135
"Patrick Klacka" <pklacka@trexenterprises.com> wrote in message news:e0a3e27d.0401201404.1d41416d@posting.google.com... > Hello > > Given two values, compare_value and change_value, is it possible to > simultaneously update all values within a fifo that equal > compare_value to change_value without having to devote a number of > clock cycles proportional to the depth of the fifo? > > The memory storage need not be a fifo, but that is how it should > function when reading and writing to it. Also, a value will only be > pulled off the fifo when another values is inserted, thus ensuring > that the fifo will always remain full. The simultaneous update of the > values will only happen at the time that a new value is inserted. I am > currently using an Altera Stratix 1S10, and could take advantage of > one or more of its features, but I'm hoping for a solution that is not > device dependent. > > Thanks in advance for any help or suggestions that may lead to a > solution to this problem. > > Patrick Nice problem, Patrick I think I see two problems: 1) Store/retrieve data like a FIFO. 2) Conditionally replace all values. So its like you need a FIFO that stores indexes into a table, then if you receive a value that's already in the table, you do a compare and if there's a match, you update the table with the new value. This way all other index values in the table will all be replaced. Does this describe a viable solution? If so, then it seems to me, the best way to do this is with a CAM, a FIFO and a RAM. Input data goes into CAM and if you get a hit, you save the CAM address into the FIFO. If not, you add the new value to the CAM and the RAM at the same new address and store the address to the FIFO. When data is read from the FIFO, you use the FIFO output to index into the RAM to retrieve the value. If the compare matches, you write the new value to the address in the CAM and the RAM. The timing might be a little hairy, but I think this will work. Hope this makes sense, BlakeArticle: 65136
Hello, Peter Alfke <peter@xilinx.com> wrote: [OP wants to know how to do BIST for dynamic faults on FPGAs] > Each individual Xilinx FPGA is 100% functionally and performance tested > ( at high temperature and low Vcc). We drive tens of millions of test > vectors at hundreds of different device configurations, trying to test > every little part of the device. Well, I believe you're achieving 100% of stuck-at failures, but do you really do some tests to achieve a 100% coverage for delay faults? I'm just curios because I know no way doing propper delay tests without a lot of additional testing hw on chip. But maybe there are some improvements made the last three years. Anyway, you can't do tests before selling a fpga, that replaces Bist for dynamic faults in the way I understood dynamic faults. Dynamic faults will occure sometime during lifetime of the fpga due to material aging or (especially in SRam based Fpgas) due to single event effects. bye ThomasArticle: 65137
On 19 Jan 2004 12:01:55 -0800, tfrankli_1@yahoo.com (Ted) wrote: >I have to make a change to a XC4005pc84-5 part but I don't have the tools that >support XC4000 parts. I've gone all the way back to Alliance Series 1.5i >and XC4000E's are supported but not XC4000's. I believe I need an old set >of M1 tools but I don't know where to find them. Does anyone know where I >can get an old set of Xilinx tools that can supports XC4000 parts (not >XC4000E parts). > >Thanks for any info. > >Ted The software that you need is prior to M1. It is the XACT sw, the last version was 5.2.1 (DOS) 6.0.1 (Win 3.1). This sw requires a dongle to run. The dongle needs a printer port that doesn't run too fast (recent machines can cycle port reads and writes too fast to the printer port, and the dongle does not respond correctly. An ISA bus plugin printer port card has a higher probability of running the dongle that the now more common PCI based parallel printer ports) Philip Philip Freidin FliptronicsArticle: 65138
On Mon, 19 Jan 2004 21:36:00 GMT, x86asm <isaac_8e@hotmail.com> wrote: >Hi guys, I was wondering if there were any good starter kits you know of >and where I am able to purchase them, I want to dip into VHDL a bit and >try out my creations on a FPGA, nothing too fancy as I'm no engineer, >just a hobbyist :) I saw one on Xilinx's online store for ~$50 US is >that a good choice? There is an extensive list of boards listed at: http://www.fpga-faq.com/FPGA_Boards.shtml Many of these can be programmed with the free sw from Xilinx and Altera. Philip =================== Philip Freidin philip@fliptronics.com Host for WWW.FPGA-FAQ.COMArticle: 65139
"Sumit Gupta" <do_not_reply_to_this_addr@yahoo.com> wrote in message news:<Z%lPb.14145$7H6.2810@newssvr27.news.prodigy.com>... > So does this mean from now on if I reply to a query for > a proto/starter board, you will start beating me :) > > Sumit No - you can do whatever you want. This is what we all do actually. ;) It was just an advice that posting ad with so small 'interval' doesnt do much good. The original poster probably read your first ad already, so reminding it once again did not increase your possible sales. my 2 cents worth of advice. and - I do not beat (hit) people or animals. Never had reason too. but, the boy next door did hang himself to dead, and my last words to him, well if they would have been different he could be alive thats something I never know. [thats true story] sorry Sumit, do not take critics so hard. I have monitored your c-nit and wondered "what he is up too" ? when I did see the proto for sale, then the question was answered. hope it goes as planed with your venture and for you more - your board is listed in our gallery for more than a week http://xilinx.openchip.org/gallery so we started to advertize your board already :) antti to the original poster - in the "gallery" are 36 Spartan II(E) boards, 4 Spartan III boards tooArticle: 65140
On 20 Jan 2004 11:59:07 GMT, jacky Renaux <renaux.jacky_nospam@wanadoo.fr> wrote: >I still use webpack 4.1 version (due to win98) and I have >fpga editor .. > >jacky Are you sure? Maybe you mean the floorplanner? PhilipArticle: 65141
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<400D7312.1090304@flukenetworks.com>... > g. giachella wrote: > > I have launched the place & route of the same project on two different > > machines, a PC 2.6 GHz (WIN 2000) and a COMPAQ XEON 700 MHz > > Workstation (WIN NT 4). Same project means same .vhd, .edf, .csf, > > .psf, .ssf, .esf, .quartus files. > > The QUARTUS release is the same (same build, same SP). > > I obtained two different placements and two different compile times > > (PC = 1h 40 min, Workstation = 5h 22 min): the file ..fit.rpt > > evidences that the options "Use Local Routing Input" and "Use Local > > Routing Output" were set differently between them during the > > compilation. > > As the project are the same and the seed is also the same, I would > > expect identical place and route. > > > > Any comment ? Am I missing somenthing ? > > Your win2k box is faster than your nt box. > > Lets assume that place & route is mostly compute bound. > In that case, if I didn't know the answer, I would > estimate the NT test time as: > > (100 min) (2.6/.7) = 371 min = 6 hours > > > So you are doing better than I would expect. > > > -- Mike Treseler I agree with you, but my real question is: why, if the two projects starting point is the same, the two placements obtained are different, when compared ? Is Quartus p&r algorithm non deterministic ?Article: 65142
Hi i'm going to use spartan3 50K fpga . If i have a 3.3 input voltage to my card do i have to create 2.5V and 1.2V . i was wandering also what is the evarage current that the spartan3 consume from those powers. i will use something like 80% from the chip CLB's Regards Avi HalfonArticle: 65143
Hi, Patrick, please specify the part number and quantities for the Altera and National devices you are looking for (Speed, package ...) and send me the list(rr@devboards.de). Please add your Name, address, telefon number... Oscillators you can buy at www.farnell.de regards, RRArticle: 65144
Dear Mr Datta, thank you for your answer. I have looked at the memory ini file during compilation and I get the following warning message: "Warning: Memory depth value (1024) in design file differs from memory depth value (32768) in Memory Initialization File - truncated remaining initial content value to fit RAM" The used RAM has the following input / output widths: input wrdata[0..0] (quasi one single bit) input wraddress[14..0] input rdaddress[9..0] output rddata_q[31..0] So I used a .mif file of 32768 words á 1bit = 32768bits (initialized with zeros). Why is the depth of the RAM said to be 1024? Thank you in advance. Best regards Andrés Vázquez Guntermann & Drunck System Development > > It is difficult to pinpoint the cause without seeing the design and > the vectors. For a start make sure that the input signals(waveforms) > being fed into the memory have the correct timing requirements, and if > there is an enable signal it has been set to the right value. Also if > the memory is being simulated as part of a larger circuit, simulate > the memory as a separate project and verify that ir works before > simulating the whole circuit. Hope this helps. > > - Subroto Datta > Altera Corp.Article: 65145
Thank you very much for all your replies. I think I better clarify a few statements! :-) First of all: I have been looking at academic research in the fault and defect tolerance field. - Defect tolerance is aimed at, say, yield improvement whereby a chip with a specific defect can still be used in certain types of applications. Xilinx's Easypath solution is seen by academics as a defect tolerance problem. Or so I seem to understand. - Fault tolerance is aimed at dynamic faults, these are faults developed during the lifetime of a device, as Thomas Stanka explained in his post. All of the project I have looked at have described a way to detect and diagnose (locate) a fault. For what I have understood, there are 3 different ways of conducting these tests, with an unprogrammed FPGA. - Reconfigure the FPGA to implement a test circuit - Design for Testability (introduce extra hardware into the FPGA with the sole aim of testing) - Iddq testing I am interested exclusively in the first of these options. Now, these tests can be further subcategorized into BIST and non-BIST tests. Non-BIST tests require an external "test driver" which generates and analyses the test vectors. BIST, on the other hand, uses different configurations (stored in a ROM outside teh chip) to do all the testing on-chip without need for extra hardware. Now, a possible scenario where I would like to carry these tests is in mission critical applications, where I need to know that the device is working properly. I am not, at this stage, interested in having the chip on- or off-line during testing. Another possible scenario is (very unrealistic, of course) if I buy a Easypath device from Xilinx and want to use it for a different design than the original one. I would then have to test the device, and find where the defect is. So my original question was: if I want to test a wire between CLB A and CLB B, how would I configure CLB A to force a 1 (or a 0) onto the wire? All the work I have seen (academic research) does not tell me how the test vectors are applied, the only say how they are analysed. I would like to point out that I understand the limitations of these types of tests, and I do not want in any way breach any copyright from any manufacturer. I am just an FPGA enthusiast. Best regards to all Nick C On Tue, 20 Jan 2004 17:05:50 +0000, BrakePiston <brakepiston@REMOVEyahoo.co.uk> wrote: >Hi there, I am trying to gain a deeper understanding of the way >testing is conducted on FPGA devices. I am interested in BIST testing >for dynamic faults, not manufacturing testing. > >My question is: how exactly can you apply a test vector (or even just >a 1 or 0) to an interconnect line? Can you just connect the output of >a LUT to the wire and observe the output? > >I am asking this because of all the documentation I have read, nobody >mentions where they get the test vectors from. > >Am i just being stupid and failing to see the obvious here? > >Thanks very much >Article: 65146
It works normally. "Hernán Sánchez" <hernan.sanchez@iname.com> wrote in message news:<bujip3$i1u45$1@ID-169358.news.uni-berlin.de>... > I have Webpack 6.1 Servicepack 3 on Windows 2000 SP4 and it's working Ok. I > think it's something related. > > > Hernán Sánchez > > "Giuseppe³" <miaooaim.REMOVETHIS@tiscali.it> escribió en el mensaje > news:buioe7$heakb$1@ID-61213.news.uni-berlin.de... > > Hi, > > I'm running ISE6.1 on Win2000 sp2 system. > > There is any problem if I install the sp4 ? Is ISE6.1 compatible with sp4? > > > > Thank you > > -- > > . > > Ciao > > Giuseppe > > > >Article: 65147
OK. I tied asking some of this stuff before, but didn't seem to get any full answers... so I'll try to revisit. If there's a Xilinx-support-site or system I should be using instead, then do, please, refer me to it. I'm messing about with 9536 and friends. Real simple PLD stuff. Xilinx/Cadence supplied a sort of library of "things" which could be used to make up 9536 circuits in Orcad. It puzzled the hell out of me, because some of them would compile for the 9536, and some wouldn't. After much reading, I've separated it into 2 libraries. One is basic primitives which work on all Xilinx PLDs, the other is macros which work on the 95xx family. I had to fillet out and dump those objects which were for other PLD series, but I think I'm there now. If anyone wants the OrCAD libs, email me as davidc at Dexdyne dawt com So I can draw Orcad ccts, create edif files, plug the edif into the project in the ISE, and program my devices by JTAG. All pretty slick. But I haven't an idea in hell how to simulate the thing. I've used the Altera IDE, where there is a nice simple simulator, and it's all part of the IDE, and it took me a very short time to get to grips with. But Xilinx seems to have decided not to write their own, but bundle someone else's. I understand I have to put the results into the ModelSim stuff, which seems to be capable of doing way more complex things than I'm every going to try this year, but it is very fierce fo9r a newbie to try to use on a simple 36 cell PLD. It doesn't seem to be integrated into the ISE, and I can't for the life of me work out how to point it at my simple 9536 design, and waggle a few inputs .... Would anyone be able to work though it with me? I'd be happy to email them the Orcad ccts and the output files generated by the ISE. I think I'd have been OK if I put the design into the integrated schematic, but importing EDIFs seems to have confused it, or me. Thanks DavidArticle: 65148
Hi everybody, just a quick question. Can the PowerPC in a Virtex II Pro, be routed to control the JTAG hardware? By that I mean provide instruction and data to the TAP Thanks!!Article: 65149
There is lots of stuff to have a look at try here for starters www.support.xilinx.com/ . The Xilinx tools usually have documentation with them and/or web linked help. There are also free Webpack tools on the Xilinx site should you want to update to recent software. These tools should take edif input or you can do VHDL or Verilog design if you prefer. If you look in the "libraries guide" from Xilinx you will find a list of macros (elements) and what product families support them. If your Orcad suite doesn't support simulation the easiest path to simulate is usually generate a VHDL or Verilog netlist which most simulators support. There are a number of ways to do this but one way is use Webpack's "Generate Post-Fit Simulation Model". Some simulators will also import or compile edif directly. If you want to go through this in more detail please contact me as listed on our website. John Adair Enterpoint Ltd. www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "David Collier" <from_usenet_comp_arch_fpga@dexdyne.com> wrote in message news:memo.20040121112518.252G@DavidC.zen.co.uk... > OK. I tied asking some of this stuff before, but didn't seem to get any > full answers... so I'll try to revisit. > > If there's a Xilinx-support-site or system I should be using instead, then > do, please, refer me to it. > > I'm messing about with 9536 and friends. Real simple PLD stuff. > > Xilinx/Cadence supplied a sort of library of "things" which could be used > to make up 9536 circuits in Orcad. It puzzled the hell out of me, because > some of them would compile for the 9536, and some wouldn't. After much > reading, I've separated it into 2 libraries. One is basic primitives which > work on all Xilinx PLDs, the other is macros which work on the 95xx > family. I had to fillet out and dump those objects which were for other > PLD series, but I think I'm there now. > > If anyone wants the OrCAD libs, email me as davidc at Dexdyne dawt com > > So I can draw Orcad ccts, create edif files, plug the edif into the > project in the ISE, and program my devices by JTAG. All pretty slick. > > But I haven't an idea in hell how to simulate the thing. I've used the > Altera IDE, where there is a nice simple simulator, and it's all part of > the IDE, and it took me a very short time to get to grips with. But Xilinx > seems to have decided not to write their own, but bundle someone else's. > > I understand I have to put the results into the ModelSim stuff, which > seems to be capable of doing way more complex things than I'm every going > to try this year, but it is very fierce fo9r a newbie to try to use on a > simple 36 cell PLD. > It doesn't seem to be integrated into the ISE, and I can't for the life of > me work out how to point it at my simple 9536 design, and waggle a few > inputs .... Would anyone be able to work though it with me? I'd be happy > to email them the Orcad ccts and the output files generated by the ISE. > > I think I'd have been OK if I put the design into the integrated > schematic, but importing EDIFs seems to have confused it, or me. > > Thanks > > David
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