Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 65250

Article: 65250
Subject: Re: Altera/Xilinx Distributor in Europe?
From: news@sulimma.de (Kolja Sulimma)
Date: 22 Jan 2004 13:11:13 -0800
Links: << >>  << T >>  << A >>
I had that problem with motorola parts years ago.
All distributors only would sell to a company.

After telling Motorola at a trade fair in munich, he checked back that
the
contracts between motorola and the distributor required the distri to
sell to anyone.

As it looks like, Xilinx has a contract for exclusive distribution of
its FPGAs with Avnet and Insight. It is hard to believe that any
company would give exclusvie distribution rights to another company
and than allow that company to restrict the customer base. My
experience with insight is, that you need to be persistent.

If in doubt, purchase from digikey. They ship to europe.
Also, look for companies in your area that use FPGA. They might sell
them to you.

For crystals I like http://www.comtec-crystals.com/.

Kolja Sulimma

bread_pitt@web.de (Patrick Birger) wrote in message news:<4454c7b.0401201545.1341dbc4@posting.google.com>...
> Rene Tschaggelar <none@none.none> wrote in message news:<22121bd70e95748cc78f4729260a05bb@news.teranews.com>...
> > 
> > have a look at http://www.ebv.com for the Altera parts.
> 
> Thanks for the address. I've called them: same problem as with
> "Spoerle"
> 1. They only sell to companies, not to private persons.
> 2. Their minimum package quantity is in general 30-90. But I don't
> want to order some 50 FPGAs, 10$ each.
> 
> Is it impossible to buy a single altera FPGA chip without founding a
> company??
> 
> Patrick

Article: 65251
Subject: Xilinx LVDS_25_DT termination issues????
From: johnp3+nospam@probo.com (John Providenza)
Date: 22 Jan 2004 14:05:04 -0800
Links: << >>  << T >>  << A >>
I'm doing a high speed design with 800 MHz LVDS data input into
a Virtex2-Pro V2P7 part.  I've looked at the new 'DT' input
termination mode for the LVDS standard and looked at the
Xilinx Answer Record 17244 for further info.

It sounds like this mode may not have the issues that DCI had.

Does anyone know of any issues with using this input termination
mode?

Thanks!

John Providenza

Article: 65252
Subject: Re: OT: liability insurance
From: Ralph Malph <noone@yahoo.com>
Date: Thu, 22 Jan 2004 17:19:43 -0500
Links: << >>  << T >>  << A >>
Robert Sefton wrote:
> 
> You're killing me, Ray! You seem to be an expert on all of the legal
> requirements and financial costs of running an engineering services
> business the right way. I hope this isn't because you learned the hard
> way how to protect yourself. :) Can you provide a bullet list of the
> things that must be in place to be in compliance legally and to protect
> yourself financially? Business license, P.E. license, CGL and O&E
> insurance ... anything else?

I once asked the county and state to tell me all the licences I would
need to run my business.  I was told that was not their job, it was up
to me to contact every department in the government to ask if I needed
permits from them!  

I expect you could hire yourself out as a resource to inform startups
about all the legal requirements, oh, that's what a lawyer is!

Article: 65253
Subject: Re: xilinx 70% tracking rule
From: Ralph Malph <noone@yahoo.com>
Date: Thu, 22 Jan 2004 17:26:15 -0500
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> Strong words, Rudi !
> But unless you can substantiate your claims, we will ignore them as your
> kind of BS.
> I am an engineer, and I do not make marketing claims, and neither do I
> publish 80% nonsense and 15% lies.

I am not looking to get into this argument, but certainly there are lies
that marketing tells.  I caught Linear Tech in an outright lie in an ad
that claimed a switcher could be built in a certain amount of board
space.  I called and asked for info on that design and was told that
there *was no design*.  It was a number that no one could even explain
how they came up with.  

Closer to home is the ever present lie in the Xilinx data sheets about
logic cell count.  The last time I checked, counting involved actually
counting things.  Xilinx seems to think that counting logic cells
involves counting and then multiplying by 1.125.  

This may be a small case, but so much of what semi companies put out in
ads and in literature is clearly hyped.  You may not like it as an
engineer, but it is the truth.

Article: 65254
Subject: Re: OT: liability insurance
From: Ray Andraka <ray@andraka.com>
Date: Thu, 22 Jan 2004 17:47:20 -0500
Links: << >>  << T >>  << A >>
Expert? no, my expertise is in engineering.  Just somewhat experienced.

I got dinged by the state when I first started out because I didn't have a
P.E. on staff.
Fortunately, they found me right before the deadline for registering for the
spring
exam, and I had already had plans to get it done.  I was able to avert
having the
business shut down by sending a copy of my PE application to the state. The
rest was
found out through due diligence, and working with a good accountant and
lawyer to
set up the business.

Incorporation (not necessarily needed, but it does help with some customers
and
    avoids a bunch of hassles since customers don't have to provide a 1099)
Registration of the business as an engineering firm (need the PE on staff to
do that)
Worker's comp insurance if you have employees
Tax withholding arrangements with all states you have employees in
Business ID number
All the piciune tax filings.
Pension/Retirement plan.


Robert Sefton wrote:

> You're killing me, Ray! You seem to be an expert on all of the legal
> requirements and financial costs of running an engineering services
> business the right way. I hope this isn't because you learned the hard
> way how to protect yourself. :) Can you provide a bullet list of the
> things that must be in place to be in compliance legally and to protect
> yourself financially? Business license, P.E. license, CGL and O&E
> insurance ... anything else?
>
> Thanks,
> Robert
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:4010074A.C0EC4FDE@andraka.com...
> > The P.E. license is issued by the state where you do business.  All
> the states
> > prescribe to the standards set by NSPE.  Basically, it involves a
> combination of
> > experience and sitting for some exams.  The most used route is to sit
> for the
> > Fundamentals in Engineering exam soon after you graduate from college.
> When you
> > pass that exam (also known as the EIT) you are an "engineer in
> training".  In
> > order to sit for the PE exam, you need to have taken the FE exam
> within the past
> > 12 years, or have 20 years of experience in your field of engineering
> (and
> > someone to vouch for it), plus at least 4 years of engineering
> experience.  The
> > FE exam is rather grueling, and I don't think I'd want to take it if I
> wasn't
> > fresh out of school, simply because it covers such a wide range of
> engineering
> > and science topics.  It is stuff that if you haven't seen it lately,
> you'll
> > probably have trouble finishing the exam in the alloted time.   I
> found the PE
> > exam to be fairly easy, although it did take some study because it
> requires some
> > breadth to your EE background...there are many sections on machines,
> > transformers, power etc that I hadn't seen in quite some time.   You
> also need
> > to get references from a number of P.E.s familiar with your work (the
> number
> > required varies by state), and depending on the state, some of those
> may have
> > to be registered in the state you are applying.  I found the hardest
> part was
> > finding the references, as there are not that many P.E.s in electronic
> design
> > for manufacturing.
> >
> > Note that in order to offer engineering services to the public (this
> includes to
> > other firms), you are required to have a P.E. registered to your firm
> in most
> > states.  Without it, the state can generally issue you a cease and
> desist order,
> > and fine and/or imprison you if you don't comply. This is enforced to
> varying
> > degrees in different states.  There is an exemption for engineering
> for
> > manufacturing, but it only applies to engineers on the company
> payroll, not to
> > outside consultants.  If you are consulting, you technically need to
> have a P.E.
> > or have someone on staff with a P.E.
> >
> > I carry professional liability, which covers the designs my firm
> produces.
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 65255
Subject: Re: map gives yet another error!
From: bret.wade@xilinx.com (Bret Wade)
Date: 22 Jan 2004 14:48:45 -0800
Links: << >>  << T >>  << A >>
nachikap@yahoo.com (Nachiket Kapre) wrote in message news:<eadce17c.0401211447.7c0e1e55@posting.google.com>...
> I get the following error while doing map on my design
> 
> --------------------------------------------------------------
> this is what echoes on the terminal...
> "Found an unexpected XMODULE_CELLTYPE property on frag"
> 
> --------------------------------------------------------------
> this is what is seen in the mrp file?
> WARNING:MapLib:328 - Block abcd_inst is not a recognized logical
> block. The mapper will continue to process the design but there may be design
> problems if this block does not get trimmed.
> 
> any help is appreciated.
> nachiket.

Hi Nachiket,

This message is most likely a problem with your design. You have a
symbol in your logical design named "abcd_inst" that either has an
invalid TYPE property or no TYPE property. The TYPE property has to
either be a recognized primitive name or match a hierarchical block in
your design. Ngdbuild should have caught this, but perhaps you are
running with the -u option which allows unexpanded blocks. Check the
.bld file for relevant messages.

Regards,
Bret

Article: 65256
Subject: Re: Why is router software not multi-threaded?
From: Ralph Malph <noone@yahoo.com>
Date: Thu, 22 Jan 2004 17:49:03 -0500
Links: << >>  << T >>  << A >>
Peter Sommerfeld wrote:
> 
> Excuse my ignorance if there is an obvious answer ...
> 
> Is it true that the routing algorithms used in Altera's and Xilinx'
> tools are single-threaded? If so, what is the primary difficulty with
> making them multi-threaded? Is the algorithm particularly difficult to
> partition into parallel units? Or has it simply not been a priority
> for companies making the tools?

I think by definition, a routing task is a single threaded process. 
Although there may be some ways to use multitasking.  I belive that a
routing problem is what computer scientists call NP complete.  It is a
process of exploring a tree (a very huge tree) finding the shortest path
to a leaf (which represents a completed route).  The only algorithm I
know of that can find the best path without exploring the entire tree is
to prune branches when you decide that they are already longer than the
shortest path you have found so far.  So at any given node, there are
multiple paths that can be followed which could be partioned out as
multiple tasks, but if this is done at a low level it will be a very
short lived process.  Even near the top levels any given subtask could
reach a dead end very quickly.  

In the end, no one ever finds the best path.  Algorithms are used that
try the most likely *good* paths and hope for the best.  

I expect the work involved in splitting off subtasks would be
significant compared to the basic function of searching the tree.  But
certainly this is worth a look unless it has already been determined
that the overhead is too large.  


> Now that some of the projects I am working on are taking quite a while
> to fit, I'm thinking it would be nice to parcel out a fit between 5
> machines sometime in the future when/if the software supports it.

If you are just trying to get a solution, then multiprocessing would be
a benifit.  But for most people who are looking to improve their fit,
multiple runs work pretty well.

Article: 65257
Subject: Re: OT: liability insurance
From: oarproductsREMOVE@yahooREMOVE.com (oar)
Date: Thu, 22 Jan 2004 23:04:48 GMT
Links: << >>  << T >>  << A >>

>Registration of the business as an engineering firm (need the PE on staff to
>do that)
>

many firms including mine thus call themselves " contract product
design " firms and avoid the word engineering just to be safe  ...
even tho we have significant industry experience the PE exam requires
a whole lotta studing on mechanical etc.

my question is would this effect E&O insurance ?  mmmm
 

Article: 65258
Subject: Re: WTD: info on AMD palce22v10
From: pildistaja@hotmail.com (Raivo Nael)
Date: 22 Jan 2004 15:07:35 -0800
Links: << >>  << T >>  << A >>
There is one untypical case in the history of FPGAs that no one
mentioned so far. ATT sold aproximately ten years ago Xilinx
compatible chips! Theyr datasheet said that these are pin-to-pin
replacements. Those were marked with ATT prefix and were clones of
XC3000 series chips. Afterwards Lucent Technologyes made also those
chips. Does anyone know more about the story?

I have also heard that NEC was one of those who tryed to make FPGAs...

Raivo

Article: 65259
Subject: Re: Why is router software not multi-threaded?
From: bret.wade@xilinx.com (Bret Wade)
Date: 22 Jan 2004 15:08:28 -0800
Links: << >>  << T >>  << A >>
"John Retta" <jretta@rtc-inc.com> wrote in message news:<hxUPb.22161$1e.13971@newsread2.news.pas.earthlink.net>...
> Look at the PAR section of the dev.pdf (Developers Reference Guide)
> in your Xilinx doc directory.  The -m option of par allows you to specify
> a list of workstations to parse out place-and-route runs.  I used this 3
> years ago in environment of Solaris workstations ..... the effort level to
> get it working was minimal.
> 
> This does not mean that par is multi-threaded.  I just means that you
> can run N different place-and-routes using different placement starting
> points (cost table entries) across multiple machines.

This feature (-m) is called the Turns Engine and will be available
under Linux beginning with version 7.1i. No multi-threaded support
yet, but it's being considered for a future release.

Regards,
Bret

> 
> -- 
> Regards,
> John Retta
> Owner and Designer
> Retta Technical Consulting Inc.
> 
> email : jretta@rtc-inc.com
> web :  www.rtc-inc.com
> 
> 
> "Peter Sommerfeld" <petersommerfeld@hotmail.com> wrote in message
> news:5c4d983.0401220801.700517ba@posting.google.com...
> > Excuse my ignorance if there is an obvious answer ...
> >
> > Is it true that the routing algorithms used in Altera's and Xilinx'
> > tools are single-threaded? If so, what is the primary difficulty with
> > making them multi-threaded? Is the algorithm particularly difficult to
> > partition into parallel units? Or has it simply not been a priority
> > for companies making the tools?
> >
> > Now that some of the projects I am working on are taking quite a while
> > to fit, I'm thinking it would be nice to parcel out a fit between 5
> > machines sometime in the future when/if the software supports it.
> >
> > -- Pete

Article: 65260
Subject: Re: Xilinx LVDS_25_DT termination issues????
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 22 Jan 2004 15:26:18 -0800
Links: << >>  << T >>  << A >>
John,

This is a true differential termination (a resistor) that is switched in 
between + and - inputs.

No 'issues'.

Enjoy,

Austin

John Providenza wrote:
> I'm doing a high speed design with 800 MHz LVDS data input into
> a Virtex2-Pro V2P7 part.  I've looked at the new 'DT' input
> termination mode for the LVDS standard and looked at the
> Xilinx Answer Record 17244 for further info.
> 
> It sounds like this mode may not have the issues that DCI had.
> 
> Does anyone know of any issues with using this input termination
> mode?
> 
> Thanks!
> 
> John Providenza


Article: 65261
Subject: Re: Why is router software not multi-threaded?
From: "Paul Leventis \(at home\)" <paul.leventis@utoronto.ca>
Date: Fri, 23 Jan 2004 00:18:53 GMT
Links: << >>  << T >>  << A >>
(reverse order -- information first, pseudo-rant second :-))

> Now that some of the projects I am working on are taking quite a while
> to fit, I'm thinking it would be nice to parcel out a fit between 5
> machines sometime in the future when/if the software supports it.

Quartus has a mode known as Fast Fit.  This turns down the fitter effort
levels and disables some of the fancier but expensive algorithms.  The
result is a 50% faster compile at the expense of about 10% performance.  If
you're hitting your performance target, you might as well enable this
option.

You can also parallelize the multiple compiles across multiple processors
(trying different options, etc.).  This doesn't help you with your big
design's compile time, unless you break it up into pieces and use the
modular design features such as LogicLock to compile each piece and then
recombine them in a final compile.  But this would likely loose you some
performance too...

> Is it true that the routing algorithms used in Altera's and Xilinx'
> tools are single-threaded? If so, what is the primary difficulty with
> making them multi-threaded? Is the algorithm particularly difficult to
> partition into parallel units? Or has it simply not been a priority
> for companies making the tools?

Parallelizing a routing (or placement) algorithm is very difficult.  The
problem is that the routing of different nets in different
threads/processors may seem like a natural division, except that the routing
of one net will be affected by the routing of another.  I guess you could
partition the nets in the device in a way that they are unlikely to interact
with one another, and then route these nets in parallel, and after each
iteration repartition and try to reconcile conflicts (nets using the same
wire twice) the next time around, but I imagine that you rapidly run into
the situation that after the first few iterations, everything left to
resolve is interconnected in some way and you can no longer parallelize...

On top of this, we'd quickly hit Amdahl's law -- if you make routing
parallelizable by N, run time will quickly be dominated by another piece of
P&R and so performance will not get better by a factor of N.  If you look at
all the things done during a compile -- synthesis, tech-mapping, clustering,
placement, routing, delay annotation/computation, timing analysis at various
steps, etc. -- that's a lot of very different algorithms that all need to be
parallelized in order to realize a significant gain in compile time.

In addition, the approximations/limitations we would need to impose on the
algorithms in order to parallize them may very well result in a reduction in
achieved performance & fitting.  Let's say parallel place & route achieves
10% worse performance for 60% run-time gain.  Would this be worth it?  Not
if you can instead enable "Fast Fit" mode in serial place and route and try
a little less hard and thus lose 10% performance for a 50% gain...

There is a fair bit of academic literature on the subject.  I can't recall
having seen any implementations of parallel place & route that competed well
with the best academic serial place & route tools, but then again I haven't
looked that hard.

Regards,

Paul Leventis
Altera Corp.



Article: 65262
Subject: Re: Synthesizing pipelined multipliers in Synplify Pro
From: Jim Lewis <Jim@SynthWorks.com>
Date: Thu, 22 Jan 2004 16:58:17 -0800
Links: << >>  << T >>  << A >>
Sandeep,
Check out my paper on,  "Coding a 40 x 40 Multipler".
The paper explores coding styles for coding a pipelined
multiplier.

You can find it at:
    http://www.synthworks.com/papers/index.htm

Also Ray Andraka has some great papers on implementing
math in FPGAs.  See:  http://www.andraka.com/multipli.htm

Cheers,
Jim

Sandeep wrote:
> Does anyone have experience with synthesizing multipliers using "*"
> operator in Synplify ? To pipleline the multiplier has anyone tried
> the piplelining feature in Synplify and/or by attaching attributes to
> output registers ? I know it works on a multiplier by itself. But in a
> larger design the pipleline stages are reduced to 1 or 2 even though I
> attached 4-5 registers to the multiplier output.
> 
> Sandeep

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


Article: 65263
Subject: Re: WTD: info on AMD palce22v10
From: Ralph Malph <noone@yahoo.com>
Date: Thu, 22 Jan 2004 20:03:51 -0500
Links: << >>  << T >>  << A >>
Raivo Nael wrote:
> 
> There is one untypical case in the history of FPGAs that no one
> mentioned so far. ATT sold aproximately ten years ago Xilinx
> compatible chips! Theyr datasheet said that these are pin-to-pin
> replacements. Those were marked with ATT prefix and were clones of
> XC3000 series chips. Afterwards Lucent Technologyes made also those
> chips. Does anyone know more about the story?
> 
> I have also heard that NEC was one of those who tryed to make FPGAs...

I thought Peter mentioned ATT.  ATT semi became Lucent who by then was
making a new chip more like the 4000 family with Sync RAM in the LUT. 
Seems they bought rights to the various patents on the 4000 and decided
to not do the clone thing, but rather to branch out and differentiate
themselves.  Their new product became known as ORCA and spawned three or
so generations all of which was sold to Lattice.  I used some of the 2C
and 3C parts on a board I built.  But, once again, it was the lack of
good software or support that made me drop them.  Their chip editor tool
really sucked and the rest was not so good.  So they went with NeoCad
for their official tool.  When NeoCad was bought by Xilinx all the
current customers had rights to the source code and had to do their own
maintenance and upgrades just like Xilinx was doing.  I guess Xilinx
figured this "leveled" the playing field.  In reality, it leveled the
competition.  

One really good point that was lost when NeoCad was bought, was the fact
that you could use one tool and target mulitple vendor's chips.  Now we
have HDL which allows the same thing if you buy each back end tool.

Article: 65264
Subject: 10GbE MACs
From: "Robert Sefton" <rsefton@abc.net>
Date: Thu, 22 Jan 2004 17:08:59 -0800
Links: << >>  << T >>  << A >>
Shopping for an 802.3ae MAC core. I've identified the following vendors
so far who seem to have real cores available in verilog rtl (VHDL not an
option):

Mentor
Cadence
MorethanIP
GDA Technologies
Sistolic

For anyone interested, Paxonet and NoBug Consulting have VHDL MACs.

This is for an ASIC project but may also involve an FPGA prototype. Has
anyone used any of these cores? I'm particularly interested in cores
than have been implemented and validated (including interoperability
testing) in silicon. Also, if there are other vendors not listed here
I'd be interested.

You can reply to me privately at rsefton@nextstate.com if you don't want
to post to the ng.

Thanks,

Robert



Article: 65265
Subject: Re: Spirit on Mars
From: jakespambox@yahoo.com (Jake Janovetz)
Date: 22 Jan 2004 17:12:25 -0800
Links: << >>  << T >>  << A >>
You're saying that FPGAs enjoy higher volumes than SRAMs?  Interesting...


Austin Lesea <austin@xilinx.com> wrote in message news:<bup6dl$8dl2@cliff.xsj.xilinx.com>...
> The reason for the failure of other parts could be that they are NOT 
> FPGAs.  FPGAs are manufactured in huge volumes, and are all tested in 
> the qualification for latch up under irradiation.  Many SRAM,s and other 
> products do not have the volume to afford such testing, and in fact 
> recent shrinks of common parts are known to latch up with a single 
> event, and destroy themselves.
> 
> Austin

Article: 65266
Subject: asic vs fpga comparison issues
From: paraagv@hotmail.com (paraag)
Date: 22 Jan 2004 17:21:02 -0800
Links: << >>  << T >>  << A >>
Hi

How do i compare asic power/timing features for the same design with
an FPGA having that same design....i mean what tecnology does xilinx
use to fabricate their die ,

The Xpower readings from the ISE foundation gives an estimate of power
, but i would like to know with which asic flow is this power
comparable ultimately leading to a hybrid chip ( if it was possible)

thanks
Paraag

Article: 65267
Subject: Re: xilinx 70% tracking rule
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 22 Jan 2004 18:28:12 -0800
Links: << >>  << T >>  << A >>
Ralph, you don't find me quoting those "12% inflated" numbers.
I hate thatfake arithmetic, but I have at times explained the reasoning
behind it, without endorsing it. It seems to be a trap without an easy
exit. Hell, we don't need those lousy 12.5% to look good. This is stuff
from a bygone era.
Anyhow, this does not make it "80% nonsense and 15% lies".
I have a right to defend myself and my company against silly
accusations.  We don't have to agree always, but we need not accept insults.

Peter Alfke
=========================================
Ralph Malph wrote:
> 
>  
> Closer to home is the ever present lie in the Xilinx data sheets about
> logic cell count.  The last time I checked, counting involved actually
> counting things.  Xilinx seems to think that counting logic cells
> involves counting and then multiplying by 1.125.
> 
> This may be a small case, but so much of what semi companies put out in
> ads and in literature is clearly hyped.  You may not like it as an
> engineer, but it is the truth.

Article: 65268
Subject: Re: WTD: info on AMD palce22v10
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 22 Jan 2004 18:45:04 -0800
Links: << >>  << T >>  << A >>
Xilinx selected ATT as a legitimate second source for XC3000 ( such
things seemed to be important in those days), with the hope of speeding
up the XC4000 project.
When this did not work out and relationships soured, ATT came out with
ORCA in competition with XC4000. All this later ended up with Lattice.

Another lesson:
 FPGAs do not transplant well from one manufacturer to the other
 ( see Altera-to-Cypress, Actel-to-T.I., Xilinx-to-MMI, before it got
swallowed by AMD, Xilinx-to-ATT. The judgement is still out on
AMD-to-Lattice, and ATT-to-Lattice  ) 

Lots of blood on the battlefield..
And fast progress and happy customers !

Peter Alfke.
==================
Raivo Nael wrote:
> 
> There is one untypical case in the history of FPGAs that no one
> mentioned so far. ATT sold aproximately ten years ago Xilinx
> compatible chips! Theyr datasheet said that these are pin-to-pin
> replacements. Those were marked with ATT prefix and were clones of
> XC3000 series chips. Afterwards Lucent Technologyes made also those
> chips. Does anyone know more about the story?
> 
> I have also heard that NEC was one of those who tryed to make FPGAs...
> 
> Raivo

Article: 65269
Subject: Re: asic vs fpga comparison issues
From: Peter Alfke <peter@xilinx.com>
Date: Thu, 22 Jan 2004 18:57:11 -0800
Links: << >>  << T >>  << A >>
The flexibility in logic and routing causes FPGAs to have lower speed
and higher power consumption than ASICs of similar technology.
FPGAs make up (partially) for this by always being at the cutting edge
of technology. 130 nm and 9-layer metal in high-volume production since
2003, 90 nm in Spartan3 volume production now.  Most ASICs use older
technology, and any existing ASIC design is hardly ever ported to a
newer technology. And at over one million dollars per mask set (plus
verification and test development costs), the number of ASIC customers
becomes naturally limited. FPGA manufacturers can amortize these same
costs over hundreds and thousands of applications.

Peter Alfke
=========================================
paraag wrote:
> 
> Hi
> 
> How do i compare asic power/timing features for the same design with
> an FPGA having that same design....i mean what tecnology does xilinx
> use to fabricate their die ,
> 
> The Xpower readings from the ISE foundation gives an estimate of power
> , but i would like to know with which asic flow is this power
> comparable ultimately leading to a hybrid chip ( if it was possible)
> 
> thanks
> Paraag

Article: 65270
Subject: CFP: 2004 MAPLD International Conference
From: "Richard B. Katz" <richard.b.katz@nospamplease.nasa.gov>
Date: 23 Jan 2004 03:29:08 GMT
Links: << >>  << T >>  << A >>



                           Call for Papers


            7th Mil/Aerospace Applications of Programmable 
            Logic Devices International Conference (MAPLD)

         Ronald Reagan Building and International Trade Center
                           Washington, D.C.
                        September 8-10, 2004

                Hosted by the NASA Office of Logic Design


   The 7th annual MAPLD International Conference's extensive program
   will include presentations, seminars, workshops, and exhibits
   on programmable logic devices and technologies, digital engineering,
   and related fields for military and aerospace applications.
   Devices, technologies, logic design, flight applications, fault
   tolerance, usage, reliability, radiation susceptibility, and
   encryption applications of programmable devices, processors,
   and adaptive computing systems in military and aerospace systems
   are among the subjects for the conference.

   We are planning an exciting event with presentations by
   Government, industry, and academia, including talks by 
   distinguished Invited Speakers.   This conference is open to
   US and foreign participation and is not classified.  For related
   information, please see the NASA Office of Logic Design Web Site
   (http://klabs.org). 


   This year, there will be special emphasis on the following themes: 

       "War Stories" and Lessons Learned
       Programmable Logic and Obsolescence Issues 
       Implementing high performance, high reliability processor cores.
       Logic design evaluation, design guidelines, and recommendations. 
       Verification methods for radiation hardness and fault tolerance. 
       Applications such as MIL-STD interfaces, UAV's, and controllers.
       Automated Checkers for low reliability design constructs. 
       PLD tools/methods that we need but vendors don't supply.


   CONFERENCE HOME PAGE - http://klabs.org/mapld04 - contains 
   an abundance of information on both technical and programmatic
   aspects of the conference.


   SEMINARS - Two full-day seminars will be presented:

       VHDL Synthesis for High-Reliability Systems
       Aerospace Mishaps and Lessons Learned


   PANEL SESSION: 

       "Why Is Space Exploration So Hard?  The Roles of Man and Machine"


   WORKSHOPS & "BIRDS OF A FEATHER" SPECIAL SESSIONS

       Mitigation Methods for Reprogrammable Logic in
           The Space Radiation Environment
       Reconfigurable Computing - New Extended Format!
       PLD Failures, Analyses, and the Impact on Systems - NEW for 2004!
       Digital Engineering and Computer Design - A Retrospective and
           Lessons Learned for Today's Engineers 
       "An Application Engineer's View" - Back for 2004! 
       "NESC and Software" - a joint session of MAPLD and the NASA
           Engineering and Saftey Center


   TECHNICAL SESSIONS:

       Applications: Military and Aerospace
       Systems and Design Tools
       Radiation and Mitigation Techniques
       Processors: General Purpose and Arithmetic
       Reconfigurable Computing, Evolvable Hardware, and Security
       Poster Session


   INDUSTRIAL and GOVERNMENT EXHIBITS AND SPONSORS
   (early reservations, more to come):

      NASA Office of Logic Design         Mentor Graphics Corporation
      Xilinx Corporation                  Synthworks
      Tensilica                           Actel Corporation
      Annapolis Microsystems              Space Micro, Inc.
      SEAKR Engineering                   Aldec
      IEEE Aerospace and Electronics      Systems Society
      Hier Design                         Global Velocity
      Lattice Semiconductor               Quicksilver Technology
      Celoxica                            BAE Systems
      Nallatech                           The Andraka Consulting Group 
      Aeroflex                            Synopsys
      Peregrine Semiconductor             Starbridgesystems
      Condor Engineering                  AccelChip
      NASA Engineering and Safety Center


   For more information, please visit http://klabs.org/mapld04
   or contact:

      Richard Katz - Conference Chair   NASA Goddard Space Flight Center
      mapld2004@klabs.org               Tel: (301) 286-9705

Article: 65271
Subject: Re: Xilinx Spartan3 Timing Problems - Whats about the chips
From: anjanr@yahoo.com (Anjan)
Date: 22 Jan 2004 20:06:11 -0800
Links: << >>  << T >>  << A >>
Hi Steve,
I have a question about spartan 3. We are xilinx customers and have
ordered spartan 3 device long back. Also we have ordered engineering
samples. But the distributor can't answer when the order comes to us.
Can you please tell me whether spartan 3 1.5m devices are being
shipped(engineering samples)?
Anjan

Article: 65272
Subject: Re: Random data generator...
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Fri, 23 Jan 2004 15:15:07 +1100
Links: << >>  << T >>  << A >>
On Thu, 22 Jan 2004 10:19:12 -0800, Peter Alfke <peter@xilinx.com>
wrote:

>David Nyberg wrote:
>> 
>> Anybody ever come accross a way to design and build a random high speed
>> data pattern generator?  It just dawned on me that I'm going to need a
>> way to test the MUX design I posted to 300MB/s!
>
>David, decide whether you need true randomness, or whether pseudo-random
>is good enough. If it is, you can build linear-feedback shift register
>structures quite easily, and make them as long and as fast ( and
>parallel) as you want.

The ITU-T specify some LFSR tap sets for use in test equipment.  The
O.150 series of specifications contains the information.  These turn
out to be the same as the ones in XAPP-052 for lengths 7, 15, 23 and
31, with XOR feedback (and the shift register initialised to all
ones).  There's also a 20 bit one, but it isn't a standard LFSR.
The 23 and 31 bit ones are suited to high speed testing.

There are standard ways of unrolling the LFSR to make it parallel to
achieve higher bit rates.  300MB/s isn't very fast for an FPGA though.

These LFSRs have been designed for testing *serial* data links.
Experience gained when I was at Agilent indicated that they don't have
enough transitions to properly stress wide parallel interfaces.

A combination of LFSR and an alternating all ones / all zeros pattern
seemed ok.

Regards,
Allan.

Article: 65273
Subject: Xilinx CoreGen - java - Windows 2000 error
From: "jtw" <wrightjt@hotmail.com>
Date: Fri, 23 Jan 2004 06:24:54 GMT
Links: << >>  << T >>  << A >>
I believe I have correlated the error I get every time I exit CoreGen with
java; i.e., I think it is the java program that is causing the error as it
attempts to close.  The error I get relates to attempted access of low
memory (I don't recall the address right now--I'm at home--but I believe it
is consistent.)  I got this under ISE Alliance 5.x whenever I ran CoreGen;
now that I've upgraded to 6.x, I also get it when I start up.  Other than
the irritating message, things seem to work properly.

I briefly checked support on Xilinx's web site; didn't see anything relevant
using "java" as the key word.

Jason



Article: 65274
Subject: Re: Non deterministic routing in Quartus 3.0 ?
From: giachella.g@laben.it (g. giachella)
Date: 23 Jan 2004 00:01:18 -0800
Links: << >>  << T >>  << A >>
Petter Gustad <newsmailcomp6@gustad.com> wrote in message news:<8765f37trt.fsf@zener.home.gustad.com>...
> giachella.g@laben.it (g. giachella) writes:
> 
> > I have launched a new compilation on a pc only and, again, the result
> > is different from the previous launched on the same pc. I don't
> > understand why ...
> 
> Do you have smart compilation enabled? If yes, then it will use the
> result of the previous iteration as the base for the next.
> 
> Make a backup. Then delete all but your source files and start in a
> fresh directory.
> 
> Petter

In my tests, every time I start a new p&r, I put the project files
(.edf, .vhd, .quartus, .psf, .csf, .ssf, .esf) in a new empty
directory, so that the new compilation can't be based on previous
compilations.
Furthermore "normal" compilation is enabled.

Giuseppe



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search