Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hallo to all. While I'm designing a new component in a block diagram view, I have to instantiate another component and have to edit the generic value of this instantiated component. If I want to edit it directly in the view, the status line tells me "cannot edit read-only text". If I call the Object Proberties window, I also cannot edit the generic values. At all other machines were we use the HDL-Designer too, there is no problem to edit it. There is no write-protect in the directory-structure and files of the libraries, I'm working with. I tried the following with no result: - I took another .hdsprefs from a machine were the HDL-Designer works correctly - I newly installed the HDL-Designer with previously uninstalling it - I created a new project, mapping new libraries in another directory, creating a new component with generics and tried to instantiate it. Is there anyone who can help me to solve this problem? Thanks to all have a nice day PeterArticle: 63226
Hi Allan, Have you looked at Symphony EDA? It is 10% of Aldec's cost. I use Aldec, but Symphony looks promising to me (I started using it a week ago). It's interface is very similar, but it does not have all the bells and whistles of Active-HDL. -- Pete Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<g62jrvopslpsj5tpdfmi978imnp7cuo9s2@4ax.com>... > On Mon, 17 Nov 2003 19:27:22 -0500, rickman <spamgoeshere4@yahoo.com> > wrote: > > >Have you looked at any of the open source tools? Is that what Icarus > >is? I am not familiar with them, but I know they exist. > > Yes, I am looking at commercial software because I am currently using > an open source tool (Icarus). > > My experience is that "open source" isn't necessarily the same as > "good quality" when applied to EDA tools - both the developer and the > user communities are just too small to achieve quality comparable with > commercial EDA tools (or Linux, for that matter). > > I wish that someone could prove me wrong! > > Regards, > Allan.Article: 63227
Oops, looking through the thread I see you want a Verilog sim. Symphony is only VHDL. -- Pete Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in message news:<g62jrvopslpsj5tpdfmi978imnp7cuo9s2@4ax.com>... > On Mon, 17 Nov 2003 19:27:22 -0500, rickman <spamgoeshere4@yahoo.com> > wrote: > > >Have you looked at any of the open source tools? Is that what Icarus > >is? I am not familiar with them, but I know they exist. > > Yes, I am looking at commercial software because I am currently using > an open source tool (Icarus). > > My experience is that "open source" isn't necessarily the same as > "good quality" when applied to EDA tools - both the developer and the > user communities are just too small to achieve quality comparable with > commercial EDA tools (or Linux, for that matter). > > I wish that someone could prove me wrong! > > Regards, > Allan.Article: 63228
Has Anyone used the SPI 4.2 Core? How well is it implemented? Any idea of the power consumption? I'm wondering if the 2W specs on the web site are valid. Thanks, DanArticle: 63229
I need to build a PCI interface - could be 64 bytes of write-only latches and 1 byte of status readback. Then I want to implement the rest of my logic, not to complex, in a PLD. I'd LIKE it all to be in one device, but I don't want to spend any time debugging PCI implementations. Anyone got any recommendations for where to go get my IP? DavidArticle: 63230
Hi, You will need some code to run on Microblaze that implements the FAT filesystem. At the hardware level, you can read sectors from the CF through the SystemACE. However, you will need to then interpret the contents of the sectors as a FAT formatted disk, so that you can retrieve files. You can buy commercial libraries to do this, or you can look around on Google to find how others have done it. Here's an example: http://www.ethernut.de/en/ide/index.html Eric #YU WEI# wrote: > > Thanks. I read this manual but I didn't find how > to visit CF card to get the data there. I don't mean > to generate a system ACE file which can boot up > the FPGA. I wonder whether microblaze can get the > data in CF card after FPGA is configured and how > to prepare the data in the CF card. Have you met > this problem? > > Regards, > YUWEIArticle: 63231
Hi, There are any number of vendors -- both Xilinx and Altera have PCI interface IP you can purchase. If you like, you can also find some FPGAs with integrated PCI interfaces in them... Or you can buy IP from a wide variety of IP vendors, just look at the third party vendor lists on the Xilinx or Altera websites. You could also try using the PCI interface available on the Opencores website. And then there are always products from PLX, etc... if you don't mind using a 2-chip solution. Is this a commercial development project, or a hobby project? Eric David Collier wrote: > > I need to build a PCI interface - could be 64 bytes of write-only > latches and 1 byte of status readback. Then I want to implement > the rest of my logic, not to complex, in a PLD. > > I'd LIKE it all to be in one device, but I don't want to spend any > time debugging PCI implementations. > > Anyone got any recommendations for where to go get my IP? > > DavidArticle: 63232
The timing analyzer explains nothing about the gain-bandwidth product in the latch feedback loop (the only thing that matters for metastable recovery). Peter Alfke ====== Hans-Juergen Dorn wrote: > Thanks John, I have to admit that the timing analyzer output is still > mostly obscure to me. I'm doing FPGAs more on a hobbyist level > in my spare time. > > BTW. If you use s2 rather heavily, then XST might replicate it. > > - HansArticle: 63233
Peter Schmand wrote:
> There is no write-protect in the directory-structure and files of the
> libraries, I'm working with.
Are you sure?
Did you grep for the generic to find the file?
then
chmod guo+r file.vhd
?
> I tried the following with no result:
> - I took another .hdsprefs from a machine were the HDL-Designer works
> correctly
> - I newly installed the HDL-Designer with previously uninstalling it
> - I created a new project, mapping new libraries in another directory,
> creating a new component with generics and tried to instantiate it.
In that much time, you could have loaded
emacs and vhdl-mode :)
-- Mike Treseler
Article: 63234
Mike Treseler wrote:
> chmod guo+r file.vhd
chmod guo+rw file.vhd
-- Mike Treseler
Article: 63235
"JoeG" <JoeG@spam.net> wrote in message
news:x0kub.3977$bf5.1267@newssvr13.news.prodigy.com...
> Symon wrote:
>
> > Hi Dan,
> > Have you considered that this is maybe the opportunity you've been
> > waiting for to change to a HDL?!
> > cheers, Symon.
> >
> > "Dan DeConinck" <pixelsmart@sympatico.ca> wrote in message
> > news:Pvdub.4913$ZF1.567826@news20.bellglobal.com...
> >
> >>Hello,
> >>
> >>The newest Xilinx tools will not work on Win98. My Viewdraw schematic
> >>capture win not work on XP so I will need to find a new schematic
capture
> >>tool. I know that Xilinx has one but it is not powerful or user
friendly.
> >>
> >>What 3rd party schematic capture tools work with the latest Xilinx tools
?
> >>
> >>Thanks
> >>Dan
>
> Nice try -- but HDL will not help me here --- I have XC4000 devices
> fielded -- hence I'm stuck with the XACT 5.2.1/6.0.1 tools for place and
> route -- Anyways I'm not going to migrate several gate level designs to
> HDL, as it doesn't buy me anything.
>
Dan, Joe, Whoever,
I googled and found references to EDIF2XNF and XNF2EDIF. Would these
tools help you? I presume you have to re-enter your design anyway if you
change editor? So, could you translate it to HDL, synthesise an EDIF, run
EDIF2XNF?
You have my sympathies, these legacy things are harder and harder to
support. You should set up in business doing it!
cheers, Syms.
Article: 63236Josh Pfrimmer wrote: > The first issue I came up against was that they now have to use CoreGen to > make memories (program, data, stack), where we used to use LogicBlox. > Specifying memory contents in LogicBlox used a .mem file. In Coregen, you > have to use a .coe file. Easy enough, and when I go all the way through > implementation, I have no problems at all. > > When I want to do a functional simulation, however, the program memory is > all zeroes. How best to go about getting the .coe data into the Foundation > functional simulator? The VHDL and verilog files reference a .mif file. > The simulator allows one to "load contents" via a hex file. Consider using a vector array to infer rom or ram and eliminate the coregen simulation hassles. -- Mike TreselerArticle: 63237
David Collier <from_usenet_comp_arch_fpga@dexdyne.com> wrote: : I need to build a PCI interface - could be 64 bytes of write-only latches : and 1 byte of status readback. : Then I want to implement the rest of my logic, not to complex, in a PLD. : I'd LIKE it all to be in one device, but I don't want to spend any time : debugging PCI implementations. : Anyone got any recommendations for where to go get my IP? Lattice has free IP for their CPLDs. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de ======================================================= Free software means: Contribute nothing, expect nothing =======================================================Article: 63238
On a sunny day (Tue, 18 Nov 2003 02:52:59 -0000) it happened hmurray@suespammers.org (Hal Murray) wrote in <vrj2cbc1s36e44@corp.supernews.com>: >>hehe, I am using Vref as video input, trying to use the thing as AD. >>On the other input of the comparator is an r2r ladder. > >Have you tried LVDS or other differential input modes? Tried them all, very little difference I see. I got rid of the instability using Austin Lesea's suggestion, no more spikes. Also changed some delay half a clock... so it is sampled a bit later, to make sure the DA ladder has settled. Seems fine on audio now, but with real fast clock still strange things happen in video. Timing is everything.... Also added nice sample and hold with a dual gate MOSFET, most problems I have with webpack, unexpected things happen not sure it is creating the same circuit I intended every time. This is the biggest time factor getting this to work perhaps. For example I changed some timing by going from an @posedge to an @negedge trigger in verilog, then it stopped working altogether, then I brought out that pin to be able to scope what happens, and then it worked, so something changed..... These thing are for me a hurdle to take to use FPGA. JanArticle: 63239
On a sunny day (Tue, 18 Nov 2003 09:28:27 -0000) it happened "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in <bpcoob$o62$1$8302bc10@news.demon.co.uk>: >"Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message >news:1069103320.807101@evisp-news-01.ops.asmr-01.energis-idc.net... >> hehe, I am using Vref as video input, trying to use the thing as AD. >> On the other input of the comparator is an r2r ladder. > >Hi Jan, > >All this discussion about how tough it is to do stuff >with Vref just gave me an idea... > >How about doing the SA A/D just a little differently... >Instead of putting video on comparator Vref and DAC output >on Vin, why not ADD video+DAC (analogue summation) and >apply it to Vin, and leave Vref at a constant level? >(Yes, I realise there are some AC coupling issues to >worry about. But you already know all about clamping >on sync tips, so that should not be too hard.) >Obviously the successive approximation will "go >the wrong way" and finally give you an inverted result, >but that's easy to deal with. And your input comparator >is always working about the same Vref so you can apply >lots of bypass caps. Analogue addition is trivially >achieved by connecting the "tail" of the R2R ladder to >video instead of ground. Make sure you bypass Vref to >the same ground that's used by the DAC output buffers. > >Just a thought. >-- >Jonathan Bromley, Consultant Ooops this feels like a thousand questions in 4 minutes, just got a load of complicated email questions about something. Let's see, if you add video + the da, yes, you need to substract in the verilog the two, is theoretically the same thing. Clever idea, I will try this (weekend hey). JanArticle: 63240
Hi Manfred, Thanks for your response. I am using the dedicated clock pin 79. I had a look at other threads for optimizing the speed. Some one mentioned that by increasing the seed in the fitter setting might increase the speed, but, they also mentioned that there will only be a slight improvement, and I saw a slight increase in the speed(not good enough). Any other suggestions? Thanks for your time. Thanks, Kumaran "Manfred Balik" <e8825130@stud4.tuwien.ac.at> wrote in message news:<3fb9d94f$0$18702$3b214f66@tunews.univie.ac.at>... > It looks like you didn't use the internal Clock-Network. > Use the dedicated Clock Pins 79 or 183 (and maybe the internal PLL) to have > the same delays of clock signal to each gate. > Manfred > > > "Kumaran" <kumaran@trlabs.ca> schrieb im Newsbeitrag > news:40f2d3e9.0311171247.ab73d04@posting.google.com... > > Hi all, > > I am targeting my design on Acex EP1K100QC208-3 FPGA. I did most of my > > development using Leonardo Spectrum synthesizer(2002) and Max +2. My > > license for leonardo expired, and I decided to use Quartus II(v3.0). > > When I compile using Quartus, Iam getting a negative slack time for > > one of my clock. when I compiled the same FPGA code using LS and Max > > +2, I did not have any timing issues . In the compiler settings, I > > have enabled the "optimize i/o cell register placement for timing" > > option. I also tried different synthesis tool in quartus (FPGA > > express, LS,..) but I could not get the timing right. Can anyone help > > me? > > > > Thanks, > > > > KumaranArticle: 63241
But the timing analyzer does provide a message to the user that the fmax is limited by the SRL (or CLB SelectRAM) write pulse width. I mentioned, Hans-Juergen Dorn responded. He saw earlier that he'd "get an Fmax of 561Mhz on a XC2S50e-7" which I wanted to make sure he wouldn't try to rely on. I'd be ecstatic with that kind of SRL performance, but I'm designing with registers for my own 260 MHz elements within a 2S150E. But thanks for clearing up that the timing analyzer doesn't give additional information that was pertinent to the earlier part of this thread. "Peter Alfke" <peter@xilinx.com> wrote in message news:3FBA5D7D.F7C79720@xilinx.com... > The timing analyzer explains nothing about the gain-bandwidth product in > the latch feedback loop (the only thing that matters for metastable recovery). > Peter Alfke > ====== > Hans-Juergen Dorn wrote: > > > Thanks John, I have to admit that the timing analyzer output is still > > mostly obscure to me. I'm doing FPGAs more on a hobbyist level > > in my spare time. > > > > BTW. If you use s2 rather heavily, then XST might replicate it. > > > > - HansArticle: 63242
Downlad a trial from Altec. This prevents you from ascking stupd questions.Article: 63243
could do. How are the Xilinx 4.2 tools at inferring BlockRAM vs. Distributed RAM? Are they efficient? In the interest of fully exploring the issue, though (though I may very well take your suggestion) How do people cope with the problem below, when CoreGen _is_ used? JP "Mike Treseler" <mike.treseler@flukenetworks.com> wrote in message news:3FBA645E.6040804@flukenetworks.com... > Josh Pfrimmer wrote: > > > The first issue I came up against was that they now have to use CoreGen to > > make memories (program, data, stack), where we used to use LogicBlox. > > Specifying memory contents in LogicBlox used a .mem file. In Coregen, you > > have to use a .coe file. Easy enough, and when I go all the way through > > implementation, I have no problems at all. > > > > When I want to do a functional simulation, however, the program memory is > > all zeroes. How best to go about getting the .coe data into the Foundation > > functional simulator? The VHDL and verilog files reference a .mif file. > > The simulator allows one to "load contents" via a hex file. > > Consider using a vector array to infer rom or ram > and eliminate the coregen simulation hassles. > > -- Mike Treseler >Article: 63245
I have been following several tutorials to build a simple system that only prints a string by the serial port. My system includes a Microblaze, Bram Block, UART Lite, and bram controllers for instructions and data. When I build the example I don't have problems, I generate libraries, compile the sources, generate the netlist, generate the bitstream obtening the file system.bit. Finally I update the bitstream to merge data and design into the download.bit file. But when I try to configure into a Virtex 2 (RC200 board XC2V1000FG456-4) the device never ends the configuration process, it looks as if something were missing, like the end of file or anything else. Somebody has experienced this? I hope that somebody can help me with this. Thanks in advanceArticle: 63246
On a sunny day (Tue, 18 Nov 2003 09:28:27 -0000) it happened "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in <bpcoob$o62$1$8302bc10@news.demon.co.uk>: > >Just a thought. >-- >Jonathan Bromley, Consultant Your system has also an other advantage, because the comparator always works at the same volatage level, any non-linearity due to moving within the common mode range is eliminated. JanArticle: 63247
Active reset is high. In passive state (nRESET) I pull signal to GND with 130k resistor. Pushing a button connects signal to 3.3vcc with 10R in series. Signal is filtered with 0.1uF capasitor. This circuit works well in the absence of CPLD. After plugging power, signal is low (as expected). Pressing the button activates reset. But RESET signal remains ~2.3v after releasing the button. What inside CPLD prevents signal from going down? Seems that 100k-pullup emerges at the input. CPLD is 9572XL.Article: 63248
Article: 63249
1. Once RESET signal is stuck at 2.3v I disconnect Reset input from signal
line (make pin floating). Voltage at the in rises to 2.4 volts. It is
strange cos core voltage is 3.3v, I do not have 2.4v in my system! Where
Xilinx CPLD generates this voltage from?
Intermediate input data for the puzzle:
That is, with RESET pin disconnected from corresponding signal I have 2.4v
at reset pin and 0.0v at reset line.
Question:
What resulting voltage do I get connecting back 0v reset (13k pull-down to
GND) 2.4v at RESET input of CPLD?
2. Connecting 0v output to 2.4v input results in the following constants:
- 0v; or
- 2.3v;
with equal probability.
Im I crazy?
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z