Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I am using ISE 6.1i, I have also installed the 6.1i service pack. I am getting the following error when I am trying to synthesize one of my designs. FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com What do I do? SwarnaArticle: 63276
I am using ISE 6.1i, I have also installed the 6.1i service pack. I am getting the following error when I am trying to synthesize one of my designs. FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com What do I do? SwarnaArticle: 63277
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3FBA6021.4090404@flukenetworks.com>... > Mike Treseler wrote: > > > chmod guo+r file.vhd > > chmod guo+rw file.vhd > > > -- Mike Treseler Thank you for your help. The problem solved. It is a bug in the HDL-Designer. After I installed the update-version, I can now edit the generic. Peter SchmandArticle: 63278
Hi, Does any one know where and How to get Nvidia Geforce 5600 public desigh graph include the PCB and parts list? thanks HuiArticle: 63279
Hi all, How do I compile components created with CoreGenerator in XPS. Thanks, Arkaitz.Article: 63280
"praveen" <praveen@cg-coreel.com> wrote in message news:2dfdd359.0311182226.32bcbd3@posting.google.com... > i have no of D flip flops cascaded now > there are two ways clock can be routed. > > 1) in the direction of the data flow. > 2) opposite to the direction of the data flow. > > which of the above is good?? Opposite direction will maximise hold time, which is probably what you need. But this is not an FPGA question. In an FPGA you probably have no choice about clock routing - it's done for you by the dedicated clock networks. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 63281
Simone Winkler wrote: > > Hello! > > Is anyone of you familiar with the Xilinx Application Note XAPP134? > (downloadable at http://direct.xilinx.com/bvdocs/appnotes/xapp134.pdf , > ftp://ftp.xilinx.com/pub/applications/xapp/xapp134_vhdl.zip) > > My questions are: > * From the system, you can control the SDRAM with commands that are defined > through data_addr_n, we_rn and AD[29:28]. > When I set one command, does it have to be set back to zero afterwards and > when? > E.g. when I write, I first set the addr_wr command and the address, then the > data_wr command and the data, but afterwards, do I have to set everything > (including the AD-bus) back to zero? (because, also zeros stand for a > command). Well, the answer is yes and no. All command lines at zero is a command, but it is a NOP command. That is what you send when you don't have any other command to send. Timing is very important on SDRAMs. There are clock cycle timings such as setup and hold, but there are also timings that affect how many clock cycles you have to wait between commands. Read the spec sheet very carefully. IIRC, one command line (perhaps CS) can be set to zero regardless of what the others are doing and this is a NOP as well. > * I am wondering what I have to do at the very beginning: > At first, I put a reset, and it takes some time until I can perform any > action. > Then I precharge and load the controller mode register (this has to be done > before anything else can be done, right?) > But then....? Do I have to load the SDRAM mode register before I can > read/write/auto refresh/... There are a very specific set of operations you must do at startup. Again all this is spelled out in the data sheet. There are differences between manufacturers, but according to the data I read when I did my design (some 5 years ago...) there is a subset (or is it superset?) that will work with most if not all. Micron used to have a very clear app note on initialization. > * And did I understand right, that I still have to do the refresh by hand, > so every 64ms? By issueing the command AUTO REFRESH? Or does the controller > already do this for me? Hmmmm. Now you are testing my memory. I think you have to tell the chip when to do a refresh, but you don't have to provide an address since an internal counter does that for you. > * But now, finally the last question: > In the future, I need a 16-bit-wide-data-bus-design for a 32mb module > instead of the 32-bit-design that is given here. The data destination should > then be masked by the DQMs. How can I easily convert this? If I were you, I would use the DQMs to mask writes (which is what I think they are for) and aren't there byte enables as well for the reads? If so, you can tie the two 16 halves together to form one 16 bit bus and alternate enables on page boundaries. It would seem to me if you try to alternate enables on each word, the burst feature can not be used. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 63282
In message <memo.20031118172109.1108B@DavidC.zen.co.uk>, David Collier <from_usenet_comp_arch_fpga@dexdyne.com> writes >I need to build a PCI interface - could be 64 bytes of write-only latches >and 1 byte of status readback. > >Then I want to implement the rest of my logic, not to complex, in a PLD. > >I'd LIKE it all to be in one device, but I don't want to spend any time >debugging PCI implementations. > >Anyone got any recommendations for where to go get my IP? David, You didn't say if this was a one-off or for production, though your desire for single chip suggests the latter. Hence apologies if this is inappropriate... Swimming perhaps against the current tide, I chose the Quicklogic fusible-link devices to design a fairly complex multi channel DMA/PCI interface for my video compression products. Thanks mainly to the (free) simulation tools provided, it all worked first time. Compared to that, your PCI target requirements sound pretty straightforward. Note that I'm certainly no FPGA specialist, although I did have prior PCI experience. Pro: True single chip design, can't be copied, comparatively easy to use tools, hard PCI core guarantees PCI timings which you can't mess up, can get pre-programmed/labelled straight from factory (in quantity but not ridiculous). Con: being fuse-link, you only get one go at it. Arguably this is a Good Thing because it disciplines you to do it right first time, OTOH your application may mandate the flexibility to change it after assembly. There's none of the "smarts" you tend to get on current mainstream chips. You may need to buy a programmer, although you can get some programmed samples from them via the web. Not really for hobby or one-off jobs, unless you're already a user. [Just a very satisfied customer.] -- Alan Hall PC and Embedded Systems Design Databuzz, Ipswich, UK Digital Video Specialist Tel: +44 1473 652301 "Tsunami" Wavelet Compression ProductsArticle: 63283
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag : Well, the answer is yes and no. All command lines at zero is a command, : but it is a NOP command. That is what you send when you don't have any : other command to send. Timing is very important on SDRAMs. There are : clock cycle timings such as setup and hold, but there are also timings : that affect how many clock cycles you have to wait between commands. : Read the spec sheet very carefully. : : IIRC, one command line (perhaps CS) can be set to zero regardless of : what the others are doing and this is a NOP as well. : Yes - I read the spec of the SDRAM. But in the Xilinx Application Note there's a design of a SDRAM controller that does a lot of things for me. I just tell the controller by 4 signals (data_addr_n, we_rn, AD[29:28]) which operation I want to do (PRECHARGE+LOAD CONTROLLER MODE REGISTER, AUTO REFRESH, LOAD SDRAM MODE REGISTER, WRITE, READ). In the end, this controller produces the CAS, RAS, WE,... signals for me. So my question is about the control signals of the controller: all the possible combinations of the control signals (data_addr_n, we_rn, AD[29:28]) exist, I don't know if i have to reset them in a special manner after I perform any operation (PRECHARGE+LOAD CONTROLLER MODE REGISTER, AUTO REFRESH, LOAD SDRAM MODE REGISTER, WRITE, READ). : There are a very specific set of operations you must do at startup. : Again all this is spelled out in the data sheet. There are differences : between manufacturers, but according to the data I read when I did my : design (some 5 years ago...) there is a subset (or is it superset?) that : will work with most if not all. Micron used to have a very clear app : note on initialization. : Again I read the specification. :-) But also this is done by the controller that Xilinx designed in its XAPP134. When you do a PRECHARGE command, also the LOAD CONTROLLER MODE REGISTER command is done. I think i still have got to load the SDRAM MODE REGISTER (also a command that you can tell to the controller), but i'm not sure. : Hmmmm. Now you are testing my memory. I think you have to tell the : chip when to do a refresh, but you don't have to provide an address : since an internal counter does that for you. Yes...I think that's it. But I am not sure if the Xilinx Controller already does refreshing for me (so that I never have to refresh), because there exists a refresh counter in the Controller Mode register. I'm sorry that I ask so many questions - but the documentation of the Xilinx SDRAM is not too long - I miss a lot of things there, and I need to know the exact interfacing procedure for being able to apply it to my system. Thank you very much!! SimoneArticle: 63284
Hi, We have made our own opb slave which has an interrupt signal to the opb interrupt controller. In the mpd file you have to specify this signal with the options "level" or "edge" and "sigis=interrupt". In that way you can connect the signal to the interrupt controller. But when assigning an interrupt handler for this handler I get the error: ERROR:MDT - monitor.mss:70 - Property interrupt_handler is not found Software System not created .. make: *** [mblaze/lib/libxil.a] Error 2 I have in the mss file the following: BEGIN DRIVER PARAMETER HW_INSTANCE = opb_my_device PARAMETER DRIVER_NAME = generic PARAMETER INT_HANDLER = my_opb_device_handler, INT_PORT = Intr END What do I forget? TIA, FrankArticle: 63285
I was always considering VHDL as behaviur/logic (netlist on functional gates) specification language. There are no means to add more detales required at PCB layout abstraction layer. VHDL has no means to describe placement, traces and device packages. I'm I missing missing something?Article: 63286
Hello, I am working with xilinx microblaze and I am trying to set up my microblaze to communicate with a 128 KB asynchronous SRAM chip (IS63LV1024). So far I have been able to set up the opb_emc (External Memory Controller) to communicate with the SRAM chip. However, I can only write to the SRAM in 4 bytes words. I cannot write byte by byte. Example: If I try to write to byte 0x0F10_0001, the whole word at 0x0F10_0000 gets updated instead. ================================== Before 0x0F10_0000: 00000000 0x0F10_0004: 00000000 Write 0x31 to 0x0F10_0001 After 0x0F10_0000: 00000031 0x0F10_0004: 00000000 ================================== Now, I am trying to load my program to run in the external memory by setting the program start address in the compiler options. I cannot get the program to run in external memory and it keeps crashing. Is that related to the fact that I cannot write byte by byte in the external memory, or are there some additional settings I need to do in the linker and compiler in order to get my program to run in external memory. I am using Xilinx Platform Studio (XPS) to configure my system. Are there any special parameters that I need to set in the opb_emc to enable byte by byte access ? I could not find any such parameters. Thanks RichardArticle: 63287
"Valentin Tihomirov" <valentin@abelectron.com> wrote in message news:bpfn15$1nv2n7$1@ID-212430.news.uni-berlin.de... > I was always considering VHDL as behaviur/logic (netlist on functional > gates) specification language. There are no means to add more detales > required at PCB layout abstraction layer. VHDL has no means to describe > placement, traces and device packages. I'm I missing missing something? In principle, all this information could be stored in VHDL attributes. Attributes were designed for precisely this reason - attaching information to a VHDL object that makes no sense in VHDL, but must be passed to other tools. In practice, however, the result would be a disgusting mess. Stick with a decent schematic package that can generate a VHDL netlist. Use that VHDL netlist for your pre-layout functional simulations, and use the conventional schematic-to-PCB tools for layout. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 63288
Matt wrote: > I tend to agree with your opinions. I just wanted to add that PCB layout > tools that generate VHDL/Verilog netlists are very useful for system level > simulation. Obviously this is not the information the original post was > attempting to obtain but I wanted to throw it out there for others to > contemplate. Matt, it is true that they are useful for system level simulation. But the way of the development is IMO just the opposite: _first_ you do a simulation, also on system level, _after this_ you design your chips and board. For the system level simulation you need a HDL entity, like ¨Board¨ that connects the HDL Units representing the chips. You can do this by the Testbench unit, but IMO it is a better approach to separate the testbench and board functions. And you are there: you have a ¨Board¨ HDL that contains all inter-chip connections, it would be perfect to use this for PCB Netlist generation. I made already a try with this, but did not succeed. Janos EroArticle: 63289
How can I measure the performance when I run a program in microblaze. Would it be possible for me to find a reference design on using timer to calculate performance of a program for embedded development kit? ThanksArticle: 63290
You can try the Parallel Cable III to connect to the JTAG port in order to config the board You need to use XPS together with a download script for IMPACT as well as the relevent bsd file Hoping that would be usefulArticle: 63291
We are building a new radio telescope called PAST (http://astrophysics.phys.cmu.edu/~jbp/past6.pdf) which we will install at the South Pole or in Western China. To make this work, will need to sample (6 to 8 bit precision) dozens of analog voltages at 400 Msample/sec and feed these data streams into PCs. One PC per sampler. The flash ADCs we need are available (Maxim), but we are finding it difficult to get the data into the PC. One simple way would be to use SCSI ultra640, but so far I have not found any 640 adapters on the market. Is any 640 adapter available? anything coming soon? or we could go right into a PCI-X bus. has anyone out there done this at 400 Mb/s? is this hard to do? FPGA core liscense for this seems expensive ($9K), with no guarentee of 400 mByte rates. is there a better way? thanks -Jeff PetersonArticle: 63292
hi ... I have a question for the experts , I am doing a post mortem of my last project , it was a communication processor that was basicly a lot of dataflow paths controlled by several rather complex state machines ( 100-200 states ) , I did the design by thinking out the control and drawing the state diagrams and then coding them into VHDL for Quartus and into a Stratix .. it worked , after handing over the design to the test department they loaded a board and signed off on the design within a week. My fellow engineers were rather impressed since they knew how complex the control was. The downside here was the state machines became complex and took quite a while to figure out ... then transcibing them into VHDL and also drawing a pretty state chart for documenting the design took a while. Yes I know some say start right with typing VHDL but I find that hard to comceptualize. Since this is a small company big $$ tools are out of the question. So my question ... are there tools out there that can make this process faster ? like drawing the state charts on the screen and outputing VHDL ? or other suggestions ??? again if these are $5-10K tools I won't be getting them in this company so shareware or <$1K tools are preferred even if they lack in some areas. The bigger downside here is that since the state machines took longer than I expected ( I scheduled 3 weeks of design, project took 6 weeks ) my manager has warned me to find another job ( fat chance ) as he has handed in a review requesting a 20% pay cut ... but my real question is about the tools so I may do better next time thanks for any constructive feedback , stanArticle: 63293
Jeff Peterson wrote: > We are building a new radio telescope called PAST > (http://astrophysics.phys.cmu.edu/~jbp/past6.pdf) > which we will install at the South Pole or in Western China. > > To make this work, will need to sample (6 to 8 bit precision) dozens > of analog voltages at 400 Msample/sec and feed these data streams into > PCs. One PC per sampler. How big is a sample? > > The flash ADCs we need are available (Maxim), but we are finding it > difficult to get the data into the PC. > > One simple way would be to use SCSI ultra640, but so far I have not > found any 640 adapters on the market. Is any 640 adapter available? > anything coming soon? > > or we could go right into a PCI-X bus. has anyone out there > done this at 400 Mb/s? is this hard to do? FPGA core liscense > for this seems expensive ($9K), with no guarentee of 400 mByte rates. > > is there a better way? Not clear from this whether you mean Mbit/s or MBytes/sec. If you mean Mbit/s then obviously that's not a hard problem to solve. If as I suspect you do mean Mbytes/sec then a PC (by the conventional definition) isn't going to cut it because typical PC motherboards don't support PCI-X at any frequency, they are still limited to 33MHz/32bit PCI which just isn't good enough. So the first step will be identifying a motherboard (probably with a workstation or server classification) that supports PCI-X at least 100MHz, which gives a peak theoretical throughput of 800MB/s, but a sustain probably closer to 400MB/s. Then you need to define what you are doing with the data, for example you could be: 1. Just capturing the data performing some operation on it, storing the results and throwing away the sample 2. You might be actually planning to capture to disk 400MB/s for a sustained period which has some pretty hairy implications for storage capacity. I do know of one site doing something on a similar scale, and that's a US Airforce project called Starfire Optical Range (http://www.sor.plk.af.mil/SOR/) at Kirkland AFB. I don't believe this project is heavily classified (I certainly didn't have to sign anything before helping them on the storage subsystem in 2000) so it might be worth contacting them to see if they can help you spec out a system. -- Nik SimpsonArticle: 63294
> The bigger downside here is that since the state machines took longer > than I expected ( I scheduled 3 weeks of design, project took 6 weeks > ) my manager has warned me to find another job ( fat chance ) as he > has handed in a review requesting a 20% pay cut ... but my real > question is about the tools so I may do better next time I think you do need to find another job with a better manager! An error in scheduling made by an engineer doesn't deserve a pay cut. If anyone deserves a pay cut, it's a manager who didn't know a basic management rule: take an engineer's estimate, multiply it by 2 and then use the next available unit :) If he knew the rule he would celebrate the work finished way faster than expected! /MikhailArticle: 63295
Do you really need to transfer raw data? Can you do some front-end processing to bring the speed down? If answers are 'yes' and 'no' respectively, think of repacking. You can pack 8 bytes into one 64-bit word. This brings the speed down to 50 MW/s, which should fit into regular 64/66 PCI. /Mikhail "Jeff Peterson" <jbp@cmu.edu> wrote in message news:369b6e8b.0311190715.4d66f38f@posting.google.com... > We are building a new radio telescope called PAST > (http://astrophysics.phys.cmu.edu/~jbp/past6.pdf) > which we will install at the South Pole or in Western China. > > To make this work, will need to sample (6 to 8 bit precision) dozens > of analog voltages at 400 Msample/sec and feed these data streams into > PCs. One PC per sampler. > > The flash ADCs we need are available (Maxim), but we are finding it > difficult to get the data into the PC. > > One simple way would be to use SCSI ultra640, but so far I have not > found any 640 adapters on the market. Is any 640 adapter available? > anything coming soon? > > or we could go right into a PCI-X bus. has anyone out there > done this at 400 Mb/s? is this hard to do? FPGA core liscense > for this seems expensive ($9K), with no guarentee of 400 mByte rates. > > is there a better way? > > thanks > > -Jeff PetersonArticle: 63296
"stan" <stanandsue2000@yahooREMOVE.com> wrote in message news:3fbb8795.3574357@news.compuserve.com... [...] > lot of dataflow paths controlled by several rather complex state > machines ( 100-200 states ) , I did the design by thinking out the > control and drawing the state diagrams and then coding them into VHDL > for Quartus and into a Stratix .. it worked , after handing over the > design to the test department they loaded a board and signed off on > the design within a week. My fellow engineers were rather impressed > since they knew how complex the control was. > > The downside here was the state machines became complex and took quite > a while to figure out ... then transcibing them into VHDL and also > drawing a pretty state chart for documenting the design took a while. > Yes I know some say start right with typing VHDL but I find that hard > to comceptualize. Since this is a small company big $$ tools are out > of the question. I don't know of any really free tools, but isn't there still a state chart editor in the Xilinx tools? However... Obviously I don't know the insides of your application, but 100-200 states sounds like a real behemoth. Isn't there some way you could partition it and make it hierarchical? Alternatively, it might make sense to think in terms of a microcoded solution - a custom state sequencer engine, and a little ROM containing the sequence information. Way back in the bad old days of the late 80s there was a nifty little thing from AMD called the 29PL141 that would probably have helped. One of my "must do one of these fine days" jobs is to write an HDL implementation of that - I still have all the original AMD docs on one of my bookshelves at home. Anyhow, here's my main point: state diagrams are supposed to be clear and self-evident; if they're too big to be clear and self-evident, then perhaps they are the wrong tool for the problem at hand. Similarly, if you have a state diagram of modest size, converting it into VHDL or Verilog is pretty much a no-brainer. Now, if you managed to get this leviathan to work first time, you obviously know what you're doing and I'm sure you thought of these things for yourself. So, can you offer a clue about *why* your state machines needed to be so huge? and *why* you couldn't make them hierarchical? It would be very interesting to hear your experiences. Cheers -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 63297
Hello folks, I am implementing a filter on a -5 Virtex-II part (3000) and the critical path is one of the longest adder carry chains in the design (28 bits). I have noticed that the minimum period of my design is being clobbered by the carry chain of the longest adder changing CLB column half-way through instead of carrying on up the carry chain in the column it started in... So, I would like to be able to put in my VHDL code an RLOC constraint (or something) that would inform Synplify Pro not to do any clever optimisation that will prevent Xilinx ISE 5.2.03i from keeping the carry chain in one column (an old Ray Andraka post has led me to believe this is what is happening). Googling about has yielded some discussions on it but I cannot see exactly how I would specify this in my VHDL to ensure that the carry chain remains in one column. Can someone give me some pointers please (ideally a quick code snippet to demonstrate :-) )? Thanks in advance for your time, Ken -- To reply by email, please remove the _MENOWANTSPAM from my email address.Article: 63298
On Wed, 19 Nov 2003 15:33:46 GMT, stanandsue2000@yahooREMOVE.com (stan) wrote: <<good state machine story snipped>> I've tried Statecad, which I believe is the progenitor of today's Xilinx state machine graphical entry tool. Rather than saving me time, the tool made me guess as to just what I'd have to do to get what I wanted in hardware. Maybe if you spent more time at it than I did it'd be worth it, but I find it easier to design in Verilog. The fewer tools between you and the hardware, the better. I'd have to agree with others who said that you probably should have given more thought to decomposing your FSMs into smaller ones. This is more art than science, and I don't know of any good references that explain how to do this; most people learn from someone else, or from experiences such as yours, after which they vow, "No more huge state machines." You're to be congratulated on doing a thorough enough job on design that debug went smoothly. Perhaps you deserve a better manager. Bob Perlman Cambrian Design WorksArticle: 63299
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z