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stan wrote: > hi ... I have a question for the experts , I am doing a post mortem of > my last project , it was a communication processor that was basicly a > lot of dataflow paths controlled by several rather complex state > machines ( 100-200 states ) , I did the design by thinking out the > control and drawing the state diagrams and then coding them into VHDL > for Quartus and into a Stratix .. it worked , after handing over the > design to the test department they loaded a board and signed off on > the design within a week. My fellow engineers were rather impressed > since they knew how complex the control was. > > The downside here was the state machines became complex and took quite > a while to figure out ... then transcibing them into VHDL and also > drawing a pretty state chart for documenting the design took a while. > Yes I know some say start right with typing VHDL but I find that hard > to comceptualize. Since this is a small company big $$ tools are out > of the question. > > So my question ... are there tools out there that can make this > process faster ? like drawing the state charts on the screen and > outputing VHDL ? or other suggestions ??? again if these are $5-10K > tools I won't be getting them in this company so shareware or <$1K > tools are preferred even if they lack in some areas. > > The bigger downside here is that since the state machines took longer > than I expected ( I scheduled 3 weeks of design, project took 6 weeks > ) my manager has warned me to find another job ( fat chance ) as he > has handed in a review requesting a 20% pay cut ... but my real > question is about the tools so I may do better next time > > thanks for any constructive feedback , stan My first rules, when describing a complex fsm, is to try to minimize the number of signal generated by one fsm, and to write many concurrent fsm. One process for one generated signal, and multiply the process. Normal fsm construction can have two or three process. Then for one fsm do not generate more than 3-5 signals (or vector). If you have to generate 100 signals, I will write 20 concurrent fsm. Laurent www.amontec.comArticle: 63301
Stan - I agree with Jonathan that 200 states is nuts. Very error prone and probably very difficult to maintain/modify. Were you parsing the incoming data stream and making state decisions based on that? If so, a programmable communications processor or an embedded processor (like Nios for Altera) is a much better and more flexible choice. Some tasks just aren't meant to be done in hardware, and parsing data streams is one of them. Nice reward for delivering a working design. I hope you find a way to exit that situation. Robert "stan" <stanandsue2000@yahooREMOVE.com> wrote in message news:3fbb8795.3574357@news.compuserve.com... > hi ... I have a question for the experts , I am doing a post mortem of > my last project , it was a communication processor that was basicly a > lot of dataflow paths controlled by several rather complex state > machines ( 100-200 states ) , I did the design by thinking out the > control and drawing the state diagrams and then coding them into VHDL > for Quartus and into a Stratix .. it worked , after handing over the > design to the test department they loaded a board and signed off on > the design within a week. My fellow engineers were rather impressed > since they knew how complex the control was. > > The downside here was the state machines became complex and took quite > a while to figure out ... then transcibing them into VHDL and also > drawing a pretty state chart for documenting the design took a while. > Yes I know some say start right with typing VHDL but I find that hard > to comceptualize. Since this is a small company big $$ tools are out > of the question. > > So my question ... are there tools out there that can make this > process faster ? like drawing the state charts on the screen and > outputing VHDL ? or other suggestions ??? again if these are $5-10K > tools I won't be getting them in this company so shareware or <$1K > tools are preferred even if they lack in some areas. > > The bigger downside here is that since the state machines took longer > than I expected ( I scheduled 3 weeks of design, project took 6 weeks > ) my manager has warned me to find another job ( fat chance ) as he > has handed in a review requesting a 20% pay cut ... but my real > question is about the tools so I may do better next time > > thanks for any constructive feedback , stanArticle: 63302
Valentin Tihomirov wrote: > I was always considering VHDL as behaviur/logic (netlist on functional > gates) specification language. There are no means to add more detales > required at PCB layout abstraction layer. VHDL has no means to describe > placement, traces and device packages. I'm I missing missing something? I think the part you are missing is that Symon wants to replace the schematic portion of the PCB layout software. I does not look to me like he was talking about replacing the layout portion. Maybe some people put layout info on the schematic, but I think most do not. -- My real email is akamail.com@dclark (or something like that).Article: 63303
Hello all, I'm trying to find the max power consumption of an Apex20ke240 with 3.3v vccio and 1.8v vccint. I've tried the power calculator : http://www.altera.com/products/devices/apex/utilities/apx-20kec_calc/apx-20kec_power_calc.jsp but it will not let me go past step 1. Has this been discontinued ? any suggestions DaveArticle: 63304
"Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in
message news:o0plrvk7kvd3mm2evhd0fr6nd1kdu26d3e@4ax.com...
> On Tue, 18 Nov 2003 17:49:24 -0800, "Symon" <symon_brewer@hotmail.com>
> wrote:
>
> >Hi,
> > Does anyone out there in usenet-land know of tools to let you design
> >Printed Circuit Boards with VHDL? I'm ready to switch from schematic
entry,
> >I want portability! (And all the other good reasons I switched from
> >schematic entry for my FPGA designs) Anyone use a PCB layout tool that
> >accepts EDIF files? I see there are translator tools. Anyone ready to
share
> >their experiences, pitfalls et cetera?
>
> Features like pin swapping, gate swapping and cross probing will only
> work with a tightly integrated pcb and "source" toolset.
>
> I suspect you would lose this with an HDL front end, although they do
> seem possible in theory.
>
>
> Frankly, the thought of designing a switchmode power supply using an
> HDL scares me. Designing a microstrip filter using an HDL seems nigh
> on impossible.
> (Hint: both these applications require careful layout, which is
> something that can be more easily expressed with a graphical entry
> tool.)
>
> Regards,
> Allan.
Hi Allen,
Thanks for the reply! The tool I use at the moment, ORCAD, has separate
layout and schematic entry bits. So, I agree that layout, i.e. drawing the
traces, makes no sense in VHDL. However, the schematic entry is a pain in
the @rse, after all it's just wiring up components to each other. You end up
typing in lots of attributes anyway, part numbers, value, package size, pcb
footprint. Seems to me that the physical wiring of the parts is perfectly
feasible in HDL, and I can use Perl scripts to speed things along, like I do
with VHDL for my FPGA innards designs. Maybe for some things like a SMPS, a
diagram is very useful, perhaps necessary. However, for connecting a DRAM to
a FPGA, the picture adds very little if anything. Some kind of hybrid is
called for, like we already can do with logic inside FPGAs.
Also, I would expect a HDL to be just as good at pin-swapping / gate
swapping, but, once again, I agree that layout remains inherently graphical.
As you point out the geometry of the traces is vital, and often forms part
of the circuit.
Anyway, back to ORCAD!
cheers, Syms.
Article: 63305We have been using Max EPM3032 and EPM3064 devices for several of our designs. The features I like with these devices is as follows: 1. Very Cheap - $1.30 for 3032 devices in small quantities 2. Easy tools with 74 style schematic capture entry. 3. 3.3V operation with 5V tolerant I/O The MAX 3000 is also a power hog which is the main reason I am searching for alternatives. I looked at the Xilinx CoolRunner and CoolRunner 2 parts. Here were my impressions based from their web site. I would appreciate comments. CoolRunner: 1. Although they have these parts on their web site, they seem to be deemphasised. This suggested to me that maybe this line is on the way out. 2. I like the 3.3V supply with the 5V tolerance. 3. Power is lower than Altera, prices are higher. CoolRunner 2: 1. Xilinx wants to sell these parts. 2. They use 1.8V supplies which is just about the only supply I don't already need in my design. 3. They are not 5V tolerant which may or may not be important (but often is) 4. They cost more than Altera Max 3000 or CoolRunner. Are the tools as easy as Altera? What's a good In-Circuit-Programmer? Are there gotchas? What other players or parts should I consider? 1. I want schematic entry, reasonably small size in QFP, low power and low cost. -- Al Clark Danville Signal Processing, Inc. -------------------------------------------------------------------- Purveyors of Fine DSP Hardware and other Cool Stuff Available at http://www.danvillesignal.comArticle: 63306
I bet the default for Inputs is either pullup or weak keeper (you have to specifically tell the software that you don't want this or it gives it to you). One easy way to find out if this is the problem is to put a 10k or 5k pullup in place of the 130k. I would never use a 130k resistor anyway. It is so weak it is almost 'not there' in the sense that any system noise can overcome it and reset your system.Article: 63307
"Ken" <aeu96186_MENOWANTSPAM@yahoo.co.uk> wrote in message
news:bpg5k3$4a$1@dennis.cc.strath.ac.uk...
>
> Hello folks,
>
> I am implementing a filter on a -5 Virtex-II part (3000) and the critical
> path is one of the longest adder carry chains in the design (28 bits).
>
> I have noticed that the minimum period of my design is being clobbered by
> the carry chain of the longest adder changing CLB column half-way through
> instead of carrying on up the carry chain in the column it started in...
>
> So, I would like to be able to put in my VHDL code an RLOC constraint (or
> something) that would inform Synplify Pro not to do any clever
optimisation
> that will prevent Xilinx ISE 5.2.03i from keeping the carry chain in one
> column (an old Ray Andraka post has led me to believe this is what is
> happening).
>
> Googling about has yielded some discussions on it but I cannot see exactly
> how I would specify this in my VHDL to ensure that the carry chain remains
> in one column.
>
> Can someone give me some pointers please (ideally a quick code snippet to
> demonstrate :-) )?
>
> Thanks in advance for your time,
>
> Ken
>
>
Ken,
Have you read the constraints guide in the Xilinx software manuals? Look
for the RLOC section. You end up with stuff in your UCF like :-
INST "*un6_burp_cry_0" RLOC = "X6Y4";
INST "*un6_burp_cry_1" RLOC = "X6Y4";
INST "*un6_burp_cry_2" RLOC = "X6Y5";
INST "*un6_burp_cry_3" RLOC = "X6Y5";
INST "*un6_burp_cry_4" RLOC = "X6Y8";
etc...
I used the floorplanner to get the names of things I want to RLOC. For
your problem, you could place the carry chain with floorplanner and send the
output to a temporary UCF to give you a start on your RLOC stuff. Hope that
makes sense! Read about H_SETs, HU_SETs and U_SETs too.
good luck, Syms.
Article: 63308Mea culpa. I was the one who misinterpreted Jonathan's tongue-in-cheek remarks and complained to him. Call me paranoid, but I don't like the label "conventional". Big misunderstanding. 'nough said. Peter Alfke ==================== Martin Euredjian wrote: > > I can't agree with you on this. I fail to see how what you wrote could be > offensive, nor do I see how anyone who's in the FPGA world could conclude or > extrapolate that something is being said about the quality of Xilinx's app > notes. But, then again, I'm biased, I use their chips and love them. > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in message > news:bpcpim$5v3$1$8300dec7@news.demon.co.uk... > > I owe some folk an apology. > > > > "Jonathan Bromley" <jonathan.bromley@doulos.com> wrote in > > message news:bovsnb$6o5$1$830fa7b3@news.demon.co.uk... > > > > > Don't be silly; if it's in a Xilinx appnote, it's _ipso facto_ > > > conventional :-) > > > > When I wrote that, my intent was only to poke mild fun at > > the fact that Xilinx appnotes are such a pervasive part > > of the FPGA design culture that they almost *define* what's > > conventional. But I didn't write it very well, and it was > > misunderstood as a slur on the quality of Xilinx material. > > That would have been quite absurd and I unreservedly > > apologise for any offence. > > > > Xilinx apps people have done us all a great service over > > the years by sharing a huge variety of tips and techniques > > (some conventional, some highly creative). I've had many > > occasions to be grateful for that. > > -- > > Jonathan Bromley, Consultant > > > > DOULOS - Developing Design Know-how > > VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services > > > > Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, > UK > > Tel: +44 (0)1425 471223 mail: > jonathan.bromley@doulos.com > > Fax: +44 (0)1425 471573 Web: > http://www.doulos.com > > > > The contents of this message may contain personal views which > > are not the views of Doulos Ltd., unless specifically stated. > > > > > >Article: 63309
Simone - My guess is that the "data_read" command is the idle state. If you haven't issued a prior "addr_read" command then there will be no data for you to read anyway. To be sure, though, you should create a simple test bench and simulate it. I agree that the XAPP134 documentation is poor, and the code is just as cryptic. Have fun. Robert "Simone Winkler" <simone.winkler@gmx.at> wrote in message news:1069227037.669594@news.liwest.at... > Hello! > > Is anyone of you familiar with the Xilinx Application Note XAPP134? > (downloadable at http://direct.xilinx.com/bvdocs/appnotes/xapp134.pdf , > ftp://ftp.xilinx.com/pub/applications/xapp/xapp134_vhdl.zip) > > My questions are: > * From the system, you can control the SDRAM with commands that are defined > through data_addr_n, we_rn and AD[29:28]. > When I set one command, does it have to be set back to zero afterwards and > when? > E.g. when I write, I first set the addr_wr command and the address, then the > data_wr command and the data, but afterwards, do I have to set everything > (including the AD-bus) back to zero? (because, also zeros stand for a > command). > > * I am wondering what I have to do at the very beginning: > At first, I put a reset, and it takes some time until I can perform any > action. > Then I precharge and load the controller mode register (this has to be done > before anything else can be done, right?) > But then....? Do I have to load the SDRAM mode register before I can > read/write/auto refresh/... > > * And did I understand right, that I still have to do the refresh by hand, > so every 64ms? By issueing the command AUTO REFRESH? Or does the controller > already do this for me? > > * But now, finally the last question: > In the future, I need a 16-bit-wide-data-bus-design for a 32mb module > instead of the 32-bit-design that is given here. The data destination should > then be masked by the DQMs. How can I easily convert this? > > Thank you VERY MUCH! :-) > > Simone Winkler >Article: 63310
"Duane Clark" <junkmail@junkmail.com> wrote in message news:bpg6gk02qv@enews2.newsguy.com... > Valentin Tihomirov wrote: > > I was always considering VHDL as behaviur/logic (netlist on functional > > gates) specification language. There are no means to add more detales > > required at PCB layout abstraction layer. VHDL has no means to describe > > placement, traces and device packages. I'm I missing missing something? > > I think the part you are missing is that Symon wants to replace the > schematic portion of the PCB layout software. I does not look to me like > he was talking about replacing the layout portion. Maybe some people put > layout info on the schematic, but I think most do not. > > -- > My real email is akamail.com@dclark (or something like that). Thanks Duane, you've got it exactly! I re-read my OP and can see I wasn't too clear! (Ah, the perils of posting at the end of a busy and frustrating day!!) I've posted again to try to clarify what I'm banging on about. Cheers, Syms.Article: 63311
Dan writes - > >We have been using Max EPM3032 and EPM3064 devices for several of our >designs. > >The features I like with these devices is as follows: > >1. Very Cheap - $1.30 for 3032 devices in small quantities >2. Easy tools with 74 style schematic capture entry. >3. 3.3V operation with 5V tolerant I/O > >The MAX 3000 is also a power hog which is the main reason I am searching >for alternatives. > >I looked at the Xilinx CoolRunner and CoolRunner 2 parts. Here were my >impressions based from their web site. I would appreciate comments. > >CoolRunner: > >1. Although they have these parts on their web site, they seem to be >deemphasised. This suggested to me that maybe this line is on the way >out. > >2. I like the 3.3V supply with the 5V tolerance. > >3. Power is lower than Altera, prices are higher. > >CoolRunner 2: > >1. Xilinx wants to sell these parts. >2. They use 1.8V supplies which is just about the only supply I don't >already need in my design. >3. They are not 5V tolerant which may or may not be important (but often >is) >4. They cost more than Altera Max 3000 or CoolRunner. > >Are the tools as easy as Altera? What's a good In-Circuit-Programmer? >Are there gotchas? > >What other players or parts should I consider? > >1. I want schematic entry, reasonably small size in QFP, low power and >low cost. > > >-- >Al Clark >Danville Signal Processing, Inc. >-------------------------------------------------------------------- >Purveyors of Fine DSP Hardware and other Cool Stuff >Available at http://www.danvillesignal.com > you might want to also consider Lattice Mach4000 family - the 4KZ is the lowest power device family available anywhere presently - tools are free from the web, cost is "competitive" - I know, I had to say it tho! Schematic, ABEL, VHDL,VERILOG all in the free tool. Device is offered with 3.3v supply, 2.5v supply, or 1.8v supply. I/O is 5v tolerant with no external components required. Give your local Lattice rep or FAE a call - Michael Thomas LSC SFAE New York/New Jersey 631-874-4968 fax 631-874-4977 michael.thomas@latticesemi.com for the latest info on Lattice products - http://www.latticesemi.com LATTICE - BRINGING THE BEST TOGETHERArticle: 63312
praveen wrote: > i have no of D flip flops cascaded now there are two ways clock can be routed. > > 1) in the direction of the data flow. > 2) opposite to the direction of the data flow. > > which of the above is good?? Good question, Praveen. Since 1988, every young engineer that I interviewed for employment here at Xilinx ( i.e. a couple of hundred) had to come up with an answer to that question. If you have a choice ( in an FPGA you should use global clocks, so you have no measurable delay difference anyhow) there is a trade-off: Running the clock against the data flow sacrifices performance by increasing the set-up time, but it is the safeest method, and therefore recommended. Running the clock in the direction of the data flow reduces set-up time and thus alllows a higher clock rate, but changes the input requirements in the direction of a positive (or more positive) hold time. If overdone, this can create a race condition, and "failure at any clock speed". Therefore not recommended. Peter Alfke, Xilinx ApplicationsArticle: 63313
Symon wrote: > > "Allan Herriman" <allan.herriman.hates.spam@ctam.com.au.invalid> wrote in > message news:o0plrvk7kvd3mm2evhd0fr6nd1kdu26d3e@4ax.com... > > On Tue, 18 Nov 2003 17:49:24 -0800, "Symon" <symon_brewer@hotmail.com> > > wrote: > > > > >Hi, > > > Does anyone out there in usenet-land know of tools to let you design > > >Printed Circuit Boards with VHDL? I'm ready to switch from schematic > entry, > > >I want portability! (And all the other good reasons I switched from > > >schematic entry for my FPGA designs) Anyone use a PCB layout tool that > > >accepts EDIF files? I see there are translator tools. Anyone ready to > share > > >their experiences, pitfalls et cetera? > > > > Features like pin swapping, gate swapping and cross probing will only > > work with a tightly integrated pcb and "source" toolset. > > > > I suspect you would lose this with an HDL front end, although they do > > seem possible in theory. > > > > > > Frankly, the thought of designing a switchmode power supply using an > > HDL scares me. Designing a microstrip filter using an HDL seems nigh > > on impossible. > > (Hint: both these applications require careful layout, which is > > something that can be more easily expressed with a graphical entry > > tool.) > > > > Regards, > > Allan. > Hi Allen, > Thanks for the reply! The tool I use at the moment, ORCAD, has separate > layout and schematic entry bits. So, I agree that layout, i.e. drawing the > traces, makes no sense in VHDL. However, the schematic entry is a pain in > the @rse, after all it's just wiring up components to each other. You end up > typing in lots of attributes anyway, part numbers, value, package size, pcb > footprint. Seems to me that the physical wiring of the parts is perfectly > feasible in HDL, and I can use Perl scripts to speed things along, like I do > with VHDL for my FPGA innards designs. Maybe for some things like a SMPS, a > diagram is very useful, perhaps necessary. However, for connecting a DRAM to > a FPGA, the picture adds very little if anything. Some kind of hybrid is > called for, like we already can do with logic inside FPGAs. > Also, I would expect a HDL to be just as good at pin-swapping / gate > swapping, but, once again, I agree that layout remains inherently graphical. > As you point out the geometry of the traces is vital, and often forms part > of the circuit. I agree completely with you about the advantage of HDL for "schematic capture". Typically when you design a digital circuit you are making lists of bus names that connect to pin names or numbers... you just do this graphically rather than in an editor. This is actually more work of course, than just making the list as text. But most people are "comfortable" with schematics. The advantages of using schematic with layout really comes from the shared library rather than any inherent feature of schematic capture. I remember a coworker who was telling me about a project from "hell" he had worked on at his last job. He inherited the work from a designer who had left and the docs were text lists of pins to nets, NO schematic! This guy could not work that way and ended up doing very poorly on that project. Besides, isn't a schematic a nice thing to look at? Well, maybe not... Would you be willing to write your design in a PCB program's netlist format? If you pick one that is popular (like PADS), it is portable in that most packages will import it. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 63314
In article <bpg7em$1krhvn$1@ID-212844.news.uni-berlin.de>, Symon wrote:
> However, the [circuit board] schematic entry is a pain in
> the @rse, after all it's just wiring up components to each other. You end up
> typing in lots of attributes anyway, part numbers, value, package size, pcb
> footprint. Seems to me that the physical wiring of the parts is perfectly
> feasible in HDL, and I can use Perl scripts to speed things along, like I do
> with VHDL for my FPGA innards designs. Maybe for some things like a SMPS, a
> diagram is very useful, perhaps necessary. However, for connecting a DRAM to
> a FPGA, the picture adds very little if anything. Some kind of hybrid is
> called for, like we already can do with logic inside FPGAs.
I agree completely. Keeping track of 300+ FPGA user I/O pins is hard
enough in a spreadsheet or HDL. It's pretty much impossible on a schematic.
Integrating the FPGA design and board design also has to be a Good Thing.
- Larry [who would s/VHDL/Verilog/g in the above]
Article: 63315Al Clark wrote: > > We have been using Max EPM3032 and EPM3064 devices for several of our > designs. > > The features I like with these devices is as follows: > > 1. Very Cheap - $1.30 for 3032 devices in small quantities > 2. Easy tools with 74 style schematic capture entry. > 3. 3.3V operation with 5V tolerant I/O > > The MAX 3000 is also a power hog which is the main reason I am searching > for alternatives. > > I looked at the Xilinx CoolRunner and CoolRunner 2 parts. Here were my > impressions based from their web site. I would appreciate comments. > > CoolRunner: > > 1. Although they have these parts on their web site, they seem to be > deemphasised. This suggested to me that maybe this line is on the way > out. > > 2. I like the 3.3V supply with the 5V tolerance. > > 3. Power is lower than Altera, prices are higher. > > CoolRunner 2: > > 1. Xilinx wants to sell these parts. > 2. They use 1.8V supplies which is just about the only supply I don't > already need in my design. > 3. They are not 5V tolerant which may or may not be important (but often > is) > 4. They cost more than Altera Max 3000 or CoolRunner. > > Are the tools as easy as Altera? What's a good In-Circuit-Programmer? > Are there gotchas? > > What other players or parts should I consider? > > 1. I want schematic entry, reasonably small size in QFP, low power and > low cost. Xilinx, and most other vendors, always ephasize the latest and greatest parts they have. The Coolrunner parts are really only a year or two old and so they will be around a long time to come. You can also get very competitive pricing if you discuss this with your distributor. They love to give you what you need to get a design win since they get paid for every part sold to that socket even if they done sell the parts! They will go to bat for you with the manufacturer on price. I know this from experience. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 63316
> Active reset is high. In passive state (nRESET) I pull signal to GND with > 130k resistor. Pushing a button connects signal to 3.3vcc with 10R in > series. Signal is filtered with 0.1uF capasitor. This circuit works well in > the absence of CPLD. Save money, board space and headaches while gaining reliability with a reset supervisor chip: http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1195 BPArticle: 63317
"King" <feb_20@sinaman.com> wrote... > How can I measure the performance when I run a program in microblaze. Put a GPIO module (or an equivalent) in your design. Hook up the IO pin to an oscilloscope. At the beginning of the routine write a '1' to the GPIO, at the end write a '0'. Regards, Erik Widding. --- Birger Engineering, Inc. -------------------------------- 617.695.9233 100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.comArticle: 63318
If your schedule is such that you won't go into production for 6 months you may want to contact Altera about MAX 2 , the next generation of product that will be available mid 2004. This just provides the option of staying with the same toolset for a much lower power device ... but they aren't 5V tolerant. I also have a power issue with the current MAX parts but since the other logic parts on my boards are Altera I really prefer to keep one development tool for the board and thus will wait for MAX 2 for the power reduction. Lattice also makes some great parts with good power characteristics .. I used to be a loyal Lattice guy until my local FAE quit and support stopped ... but no more. On Wed, 19 Nov 2003 16:55:49 GMT, Al Clark <dsp@danvillesignal.com> wrote: >We have been using Max EPM3032 and EPM3064 devices for several of our >designs. > >The features I like with these devices is as follows: > >1. Very Cheap - $1.30 for 3032 devices in small quantities >2. Easy tools with 74 style schematic capture entry. >3. 3.3V operation with 5V tolerant I/O > >The MAX 3000 is also a power hog which is the main reason I am searching >for alternatives. > >I looked at the Xilinx CoolRunner and CoolRunner 2 parts. Here were my >impressions based from their web site. I would appreciate comments. > >CoolRunner: > >1. Although they have these parts on their web site, they seem to be >deemphasised. This suggested to me that maybe this line is on the way >out. > >2. I like the 3.3V supply with the 5V tolerance. > >3. Power is lower than Altera, prices are higher. > >CoolRunner 2: > >1. Xilinx wants to sell these parts. >2. They use 1.8V supplies which is just about the only supply I don't >already need in my design. >3. They are not 5V tolerant which may or may not be important (but often >is) >4. They cost more than Altera Max 3000 or CoolRunner. > >Are the tools as easy as Altera? What's a good In-Circuit-Programmer? >Are there gotchas? > >What other players or parts should I consider? > >1. I want schematic entry, reasonably small size in QFP, low power and >low cost. > > >-- >Al Clark >Danville Signal Processing, Inc. >-------------------------------------------------------------------- >Purveyors of Fine DSP Hardware and other Cool Stuff >Available at http://www.danvillesignal.comArticle: 63319
There is an April 2001 TechXclusives "Using leftover multipliers and BlockRAMs" that describes a surprisingly simple structure for a state machine with up to 256 states. I never got any feedback on this idea. There is no software tool, but it's pretty straightforward, and "pencil and paper" might suffice... http://support.xilinx.com/xlnx/xweb/xil_tx_home.jsp Peter Alfke, Xilinx Applications ============================= Robert Sefton wrote: > > Stan - > > I agree with Jonathan that 200 states is nuts. Very error prone and > probably very difficult to maintain/modify. Were you parsing the > incoming data stream and making state decisions based on that? If so, a > programmable communications processor or an embedded processor (like > Nios for Altera) is a much better and more flexible choice. Some tasks > just aren't meant to be done in hardware, and parsing data streams is > one of them. > > Nice reward for delivering a working design. I hope you find a way to > exit that situation. > > Robert > > "stan" <stanandsue2000@yahooREMOVE.com> wrote in message > news:3fbb8795.3574357@news.compuserve.com... > > hi ... I have a question for the experts , I am doing a post mortem of > > my last project , it was a communication processor that was basicly a > > lot of dataflow paths controlled by several rather complex state > > machines ( 100-200 states ) , I did the design by thinking out the > > control and drawing the state diagrams and then coding them into VHDL > > for Quartus and into a Stratix .. it worked , after handing over the > > design to the test department they loaded a board and signed off on > > the design within a week. My fellow engineers were rather impressed > > since they knew how complex the control was. > > > > The downside here was the state machines became complex and took quite > > a while to figure out ... then transcibing them into VHDL and also > > drawing a pretty state chart for documenting the design took a while. > > Yes I know some say start right with typing VHDL but I find that hard > > to comceptualize. Since this is a small company big $$ tools are out > > of the question. > > > > So my question ... are there tools out there that can make this > > process faster ? like drawing the state charts on the screen and > > outputing VHDL ? or other suggestions ??? again if these are $5-10K > > tools I won't be getting them in this company so shareware or <$1K > > tools are preferred even if they lack in some areas. > > > > The bigger downside here is that since the state machines took longer > > than I expected ( I scheduled 3 weeks of design, project took 6 weeks > > ) my manager has warned me to find another job ( fat chance ) as he > > has handed in a review requesting a 20% pay cut ... but my real > > question is about the tools so I may do better next time > > > > thanks for any constructive feedback , stanArticle: 63320
Jeff Peterson wrote: > We are building a new radio telescope called PAST > (http://astrophysics.phys.cmu.edu/~jbp/past6.pdf) > which we will install at the South Pole or in Western China. > > To make this work, will need to sample (6 to 8 bit precision) dozens > of analog voltages at 400 Msample/sec and feed these data streams into > PCs. One PC per sampler. > > The flash ADCs we need are available (Maxim), but we are finding it > difficult to get the data into the PC. > > One simple way would be to use SCSI ultra640, but so far I have not > found any 640 adapters on the market. Is any 640 adapter available? > anything coming soon? > > or we could go right into a PCI-X bus. has anyone out there > done this at 400 Mb/s? is this hard to do? FPGA core liscense > for this seems expensive ($9K), with no guarentee of 400 mByte rates. The first thing I would think of would be to buffer it and then read it later. You don't say how long this data stream will be, or if this is a peak rate with a much lower average rate. Does it have to go to disk at that rate? You could collect the samples into 64 bit words and write then into SDRAM at 40 or 50 MHz. If it has to go to disk at that rate, I would work on the hardware to get it onto the disk without a processor in between. -- glenArticle: 63321
sdatta@altera.com (Subroto Datta) wrote in message news:<ca4d800d.0311171211.14b76e97@posting.google.com>... > petersommerfeld@hotmail.com (Peter Sommerfeld) wrote in message news:<5c4d983.0311170541.5bd0c1db@posting.google.com>... > > What does this generic means? > > > > I am wondering if I am missing out on a possible memory optimization. > > > > Altera's docs are decidedly vague and a search on their website brings up nothing. > > > > -- Pete > > MAXIMUM_DEPTH controls the underlying RAM block size that will be used > to construct the user's altsyncram memory. By default, the altsyncram > megafunction will round up the memory depth to the next power-of-2, > and use that as a RAM block size. For example, if you ask for a > 3K-word memory, altsyncram will normally construct it from 4K RAM > blocks, because this gives the best performance. If you are running > short of RAM blocks, you could specify MAXIMUM_DEPTH=1024 for this > example, and the altsyncram megafunction will construct the 3K memory > from 1K-word RAM blocks, which might potentially use 1/4 fewer RAM > blocks. The penalty for doing this is that the 3K-word memory > constructed from 1K-word RAM blocks will need LEs to mux and de-mux > the data, and will also run slower as a result. > > In summary, MAXIMUM_DEPTH is a control to increase memory efficiency > for non-power-of-2 memory depths, but at a cost of lower memory > performance, and a few LEs to stitch the smaller RAM blocks together. > MAXIMUM_DEPTH can only take power-of-2 values, with 32 being the > smallest meaningful value, since it corresponds to the shallowest M512 > memory block configuration. > > - Subroto Datta > Altera Corp. Hi Manfred, Peter, The MAXIMUM_DEPTH description that was posted in my previous reply applies to the altsyncram megafunction, and indirectly to scfifo and dcfifo megafunctions. The FIFO megafunctions do not support non-power-of-2 depths, so the memory example I gave does not apply. In Quartus II 4.0, the FIFO MegaWizard plug-in will not allow you to enter non-power-of-2 depths. The only reason for specifying a MAXIMUM_DEPTH parameter in a FIFO megafunction in pre-4.0 versions of Quartus would be to enforce a smaller RAM block size to give added freedom to the fitter. MAXIMUM_DEPTH values of 128, 256, and 512 can fit in either M512 blocks or M4K blocks. A MAXIMUM_DEPTH value of 4096 can fit in either an M4K block or an M-RAM. Here's an example: I have a 2K word FIFO, and I don't care if it goes into M4K blocks or M512 blocks. If I set MAXIMUM_DEPTH=512, the FIFO will be constructed from 512-word RAM slices, which gives the fitter the flexibility to place the FIFOs in either M512 blocks or M4K blocks. - Subroto Datta Altera Corp.Article: 63322
iamtung@sinaman.com (Tony) wrote in message news:<be913553.0311190708.507c2b43@posting.google.com>... > You can try the Parallel Cable III to connect to the JTAG port in > order to config the board > > You need to use XPS together with a download script for IMPACT as well > as the relevent bsd file > > Hoping that would be useful Thanks Tony, I think that the cable isn't the problem, because I have several examples running in the RC200 board that has been configurated and work without problems. Obviously I used the program that celoxica provides to download and configurate the bitstream into the FPGA. The problem is that the configuration process never ends. Thanks again.Article: 63324
"Nik Simpson" <n_simpson@bellsouth.net> wrote in message news:<DiMub.3510$gU2.827@bignews6.bellsouth.net>... > Jeff Peterson wrote: > > We are building a new radio telescope called PAST > > (http://astrophysics.phys.cmu.edu/~jbp/past6.pdf) > > which we will install at the South Pole or in Western China. > > > > To make this work, will need to sample (6 to 8 bit precision) dozens > > of analog voltages at 400 Msample/sec and feed these data streams into > > PCs. One PC per sampler. > > How big is a sample? 8 bits. > > > > > The flash ADCs we need are available (Maxim), but we are finding it > > difficult to get the data into the PC. > > > > One simple way would be to use SCSI ultra640, but so far I have not > > found any 640 adapters on the market. Is any 640 adapter available? > > anything coming soon? > > > > or we could go right into a PCI-X bus. has anyone out there > > done this at 400 Mb/s? is this hard to do? FPGA core liscense > > for this seems expensive ($9K), with no guarentee of 400 mByte rates. > > > > is there a better way? > > > Not clear from this whether you mean Mbit/s or MBytes/sec. If you mean > Mbit/s then obviously that's not a hard problem to solve. If as I suspect > you do mean Mbytes/sec then a PC (by the conventional definition) isn't > going to cut it because typical PC motherboards don't support PCI-X at any > frequency, they are still limited to 33MHz/32bit PCI which just isn't good > enough. i do mean 400Mbytes/sec. and yeah, PCI 33/32 wont cut it. > > So the first step will be identifying a motherboard (probably with a > workstation or server classification) that supports PCI-X at least 100MHz, > which gives a peak theoretical throughput of 800MB/s, but a sustain probably > closer to 400MB/s. Then you need to define what you are doing with the data, > for example you could be: > > 1. Just capturing the data performing some operation on it, storing the > results and throwing away the sample we accumualte averages (of cross products of fourier tranforms) > > 2. You might be actually planning to capture to disk 400MB/s for a sustained > period which has some pretty hairy implications for storage capacity. > we wont store the raw data, just a very much reduced set. > I do know of one site doing something on a similar scale, and that's a US > Airforce project called Starfire Optical Range > (http://www.sor.plk.af.mil/SOR/) at Kirkland AFB. I don't believe this > project is heavily classified (I certainly didn't have to sign anything > before helping them on the storage subsystem in 2000) so it might be worth > contacting them to see if they can help you spec out a system.
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