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David Dye <davidd@xilinx.com> wrote in message news:<405F47BA.9040903@xilinx.com>... > Marc Randolph wrote: > > > Nahum Barnea wrote: > > > >> Hi. > >> How can I run Xilinx map with -timing option through the ise gui ? > >> Currently I am using command line, but I wish to use the ise gui. > >> > >> ThankX, > >> NAHUM > > > > > > Howdy Nahum, > > > > If it doesn't show up in Map -> Properties, you need to turn on > > advanced mode... which is under Edit -> Preferences -> Processes. > > Obvious, ain't it? :-) > > > > Have fun, > > > > Marc > > > > P.S. If you are an experienced command line user, you may find > > yourself disappointed with the flexibility that the GUI provides. The > > check boxes and help screens are nice, but if any of your input files > > (either .ucf or your real source) change, even if you are just adding > > a comment, the gui will try to re-run everything - not a big deal if > > your builds are 5 minutes, but some of our designs take something on > > the order of half a workday to run through (on a 3.2 GHz machine). > > > This is done to keep everything in your project in sync, but there is a > way to avoid the automatic recompilation. Most processes and report > files have a local menu pick called "Open Without Updating". This will > immediately open the result file or tool (like FPGA Editor) without > "pulling" the current design though to that point. Howdy David, I was actually referring to rerunning a process (PAR or MAP are the obvious big ones, but bitgen and translate are also one) rather than just a result file or tool. This happened to me just yesterday in 6.2.1i Someone was working on a different part of the design than I was (he was actually doing iterative floorplanning runs) and I changed the names of some CONSTANTs in the .vhd source files to be more descriptive. Project Nav insisted the he re-run synthesis and translate, wasting nearly and hour of his time while he waited. Said another way, just because the source has changed doesn't mean that we want the tool to automatically recompile everything (there are ways to graphically show that the eariler files are not in sync if that is your worry). If you know of a way around this, please do let us know! Best regards, MarcArticle: 68101
Amaury Anciaux wrote: > Yes, but in this case, even in the final assembly, this signal stays > unrouted. > I attach some example files: the NCD routed designs of the two modules, and > the final assembly. > The signals conerned are controlL<3> and controlL<7> (in module 1 and final > assembly). Other unrouted signals in the modules are normal. Try the following at the command prompt: xdl -ncd2xdl bm_v2p_4b.nmc This converts the bus macro to an XDL-description. Have a look at the .XDL-file this generates. For each net, there should be a section where it specifies which PIPs to use and such. For each net there should be an attribute like this: cfg "_NET_PROP::IS_BUS_MACRO:" , If there isn't, par sometimes doesn't route the corresponding output net. I have no idea why that is... In case this attribute is not set for the fourth bit of your bus macro, it could help to insert it manually in the .XDL-file and convert that back to ncd-format: xdl -xdl2ncd bm_v2p_4b.xdl This gives you an .ncd-file which you have to rename to .nmc to be able to use it as a macro. Don't know if this will help you, but I always had to manually insert the above attribute for all nets in the macros I did myself in FPGA Editor. FPGA Editor always seems to "forget" that, for whatever reason. BTW, I'm not sure if all of this works satisfactory with ISE6.1/6.2... When using XDL in ISE6, I always get a warning that "this is a new revision ncd, some features might be lost" or something. > As you can see, they are connected to the same TBUF in both bus macros. > BTW, do you know if the T input of a TBUF has to be "1" or "0" to be in high > impedance? "1" disables the tristate buffer, so "1" for high impedance. -- Best regards, Sean DurkinArticle: 68102
I certainly wouldn't agree with that ratio and there is a long history of argument about gate metrics and their comparison. Utilisation of the Virtex2 family is usually fairly good. In the olden days using something like a 4000 family you would be lucky to use 70-80% of the logic available. Occasionally we have pushed modern families to 99.5 % of logic in systems with low clock rates (< 40 MHz). Virtex2 uses active routing which is fairly fast and is part of the reason why Virtex2 is fast. The XC6000 p&r can very slow. Part of the reason can be memory usage. If you don't have enough physical memory you will start to page to disk and the p&r time goes out to forever. You may hit the WIN2K and NT4 workstation limits of 2 GB. I think XP will go to 4 GB. Server versions of these OS will go higher as will Linux. I personally run with 2 GB for large designs and employ other techniques to keep memory usage down. I would suggest using floorplanning to help the tools with a large device such as XC2V6000. Also look at the number clock nets used within sectors. If there are a large number of clocks they will be competing for low skew resource. Attempt to deconstrain paths that don't run at full clock rate. The extra timing slack may make the difference. Also use incremental synthesis and incremental place and route to cut down iteration time. Our website still has an article on increment synthesis if you care to look at it. Also try different placement tables. You will find a lot of variation in performance between tables. -- John Adair Enterpoint Ltd. http://www.enterpoint.co.uk This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted. "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:4063cccf@news.starhub.net.sg... > I am compiling a 400K gate design with XC2V6000...but ISE-6 failed to route > it in 3 days... > and it hang arround 500+ wires not routed, the slice usage is 60%... > > May I assume a system gate of N kilogates in Xilinx's datasheet can only > hold an ASIC > design of up to N/15 kilogates? > > Kelvin > > >Article: 68103
"Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message news:<4063cccf@news.starhub.net.sg>... > I am compiling a 400K gate design with XC2V6000...but ISE-6 failed to route > it in 3 days... > and it hang arround 500+ wires not routed, the slice usage is 60%... > > May I assume a system gate of N kilogates in Xilinx's datasheet can only > hold an ASIC > design of up to N/15 kilogates? > > Kelvin I would ignore any ASIC equiv estimates from the tool. If your code is in RTL form you should be able to do a better estimate yourself in terms of FFs, 4.1Muxes, ram bits etc. The synth report gives you the itemized macro useage so you could scale that yourself to ASIC libs. Why not put the RTL code through ASIC synthesis for a proper estimate? When targeting a part just big enough to hold a design, I do the work on a part that is 2x or bigger to avoid P/R problems. At some point if you can do floorplanning of the datapaths, you can usually push up the density of related logic quite a bit by selective manual pairing of muxes, rams, adders with FFs but there are so many constraints. When you can see islands of blocks you can then arrange them better in the final part. regards johnjakson_usa_comArticle: 68104
Rudi, I think you might be using old simulation models with a new netlist. You mentioned you are using 6.2i but that message no longer exists in the 6.2i models and has been reworded to make more sense (at least I think it makes more sense). Even though you might be using older models, I think this message is likely still a valid warning. What it is actually trying to tell you is that you are having a memory collision error on that instance of Dual Port Block RAM. A collision is anytime you write to one port of the RAM and you perform either a READ or WRITE to the same address on the other port within a specified timing window. In the case of writing to both ports, the contents written to that address in the memory become unknown. In the case of a WRITE-READ, The WRITE is successful and the READ value is unknown (it could be the old value, could be the new value or could be something in between). The new messages for this in the most recent models should look like the following: Memory Collision Error on X_RAMB16_S2_S2:test.soc2.\i_sram/mem_l.I_2 .display_zero at simulation time 53678.100 ns A read was performed on address 0000 (hex) of Port A while a write was requested to the same address on Port B. The write will be successful however the read value on Port A is unknown until the next CLKA cycle. or Memory Collision Error on X_RAMB16_S2_S2:test.soc2.\i_sram/mem_l.I_2 .display_zero at simulation time 53678.100 ns A write was requested to the same address simultaneously at both Port A and Port B of the RAM. The contents written to the RAM at address location 0000 (hex) of Port A and address location 0000 (hex) of Port B are unknown. Hopefully this updated messaging would make it more clear what has occurred and this is something that should generally be investigated. A memory collision is a timing violation and one that can not be detected or checked by static timing analysis. This is one of the reasons why I cringe every time I hear someone say you do not need to do a timing simulation if you have done a diligent static timing analysis as. Not all timing and design issues can be discovered in a static environment and this is a prime example of this. I have heard of horror stories of people who did not perform a timing simulation and thus this situation slipped by them until some boards failed during production and could have been easily detected during a simple timing simulation. My suggestion to you is to first recompile the simulation libraries making sure to use the same version of software that generated the netlist. I would then re-run simulation however I suspect you will likely see the new warnings above if you are using 6.2i. From that you must either modify your design to avoid this situation or else make sure that you do not rely on that data and it is truly discarded and will have no ill effects on your design. Since the contents and/or outputs of the RAM go X when this occurs, you can likely see if you are truly discarding that data as those X's will not have an ill effect on your design if you do not use that data in any way. If you find those X's propagate through and effect other portions of the design, then likely you will need to redesign the interface to the dual-port RAMs to avoid this situation. Hopefully this information will help you prevent a possible problem with your design down the road. -- Brian Rudolf Usselmann wrote: > erojr wrote: > > >>Rudolf Usselmann wrote: >> >> >>>Timing Violation Error : Setup time 0.000 ns violated on >>>X_RAMB16_S2_S2 instance test.soc2.\i_sram/mem_l.I_2 .display_zero >>>on CLKA port at simulation time 53678.100 ns with respect to >>>CLKB port at simulation time 53678.100 ns. Expected setup >>>time is 0.284 ns >> >>I think it is normal for Gate Level Chip simulations that you get a >>bunch of error messages for the time 0.000ns. >> >>Janos Ero >>CERN Div. EP > > > > Actually simulation time in that specific case is 53678.1 ns. > This is not a one time message it appears over and over > again. > > Regards, > rudi > ======================================================== > ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: > ..............::: FPGAs * Full Custom ICs * IP Cores ::: > FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 68105
"paris" <malaka@email.it> wrote in message news:c3vtbb$1n1a$1@avanie.enst.fr... > well i cant go into deep math details to prove it cause as i said, i did > that a long time ago, and im sure you can find the maths in the internet, > like in the link i posted (ok, the link is not so detailed, but it was one > of the first results of google) [enormous snip] I was trying to point out that your approach was fundamentally flawed. I was hoping that - when looking to answer me - you'd realize that the duty cycle is formed with even harmonics of the 500MHz signal in addition to the center frequency and odd harmonics typically associated with clocks. The baseband that's mixed back down to 50 MHz will contain phase, amplitude, and frequency variations of the center frequency translated to the 50MHz; unfortunately, the duty cycle is none of these factors. Duty cycle modulation (without considering a fixed duty cycle) will show up mostly as modulation of the harmonics, not as modulation of the 500 MHz "carrier." The 1000 MHz second harmonic will not translate to 100 MHz. The 1500 MHz third harmonic will not translate to 150 MHz. The analog techniques that can deal with duty cycle measurement could include 1) a charge pump with the imbalance in the current source and sink controlled to reach equilibrium - the imbalance gives a measure of the duty cycle and can be matched with the same imbalance on the regenerated clock, and 2) detection of phase crossing with I/Q sampling of the center signal allowing the phase of the clock edges to be determined relative to a sinusoid reference (the filtered 1st harmonic from the clock). The DC levels from the two clocks were suggested by others and is similar to the charge pump idea with errors introduced by the very fast 500 MHz input clock. The I/Q method can deliver accurate results to some pretty high frequencies.Article: 68106
Chao wrote: > Hi, everybody. > > I am using Memec Spartan-3 3s400pq208-4 device. Now I want to route > own system reset signal to Pin 207 which is available on board. But > the ISE 6.1i mapping process failed and gave me this message: > "ERROR:MapLib:681 - LOC constraint P207 on PROGRAMn_IP is invalid: No > such site on the device. To bypass this error set the environment > variable 'XIL_MAP_LOCWARN'." I do not know whether someone has idea > how to solve it. Thanks in advance. > > yours: CC Looks to me that P207 on the Spartan-3 parts is the dedicated PROGRAM pin for the FPGA and thus a user signal can not be assigned to that pin. It is and always will be the pin to reset configuration and thus the software can not do anything to change that pin and does not even really know of its existance because of this. That pin should be properly connected to the board as said in the documentation for Spartan-3 but nothing should be done with that pin from within the software. -- BrianArticle: 68107
Hi everybody, A quick question on implementing deserialization logic in Xilinx and Altera. I know Altera has SERDES circuitry built in their Stratix devices where the max factor is 10. Xilinx doesn't have dedicated circuitry. Has anybody used Altera for deserialization with a factor more than 10 using logic cells ? If so at what speed were using it ? How well does it work ? What about Xilinx ? Any help appreciated here. ThanksArticle: 68108
Hello- I'd like to package a few Xilinx modules with a particular product. They would be somewhat similar to Core Generator cores. However, Core Generator cores require Core Generator to be instantiated in any end-user design. Is there a way to package a Verilog or VHDL module so that it does not require Core Generator for the user to use it? Basically, I want folks using the WebPack to be able to use the modules. The obvious solution is to just include the Verilog/VHDL source and let the user add it to their project, but I'd prefer not to do that. Can an EDIF netlist be generated and used in a design somehow? Cheers, JakeArticle: 68109
hi there, we are final year engineering students from india. we are currently working on a fpga project and are stuck at a counter design. if any of you could help us out, it would be great. we have to design an increment decrement counter. it is more of a divider though. the ports are as follws: input: inc,dec,clock,reset output: f0 the counter is synchronous with an asynchronous reset.it should start from producing a pulse for every 8 input clock pulses. it has 2 other inputs, "inc" and "dec". on recieving a pulse at the inc port, on the falling edge of pulse, it should start producing higher frequency, ie divide by lesser.similiarly on reciving a pulse at the dec port, it should decrement output frequency, i.e. increase the limit for count. the highest frequency divide should be 16 and lowest as 1. we have been trying to get this done using VHDL, but have run into multiple driver problem etc. we are unfamiliar with verilog but are now learning it. if any of you could spare some time for us, please mail us at the above address with any sugestions or code(either VHDL or verilog). we thank all for their interest.Article: 68110
jeff_n_moz, A better forum for student support is: http://xup.msu.edu/ They have forums to answer questions exactly like yours (for Xilinx product). Students are always welcome here, but the concern is that Xilinx must attend to the paying customer first, and in doing so, does not want the learning student to suffer (who will be next years paying customer). In order to fufill both objectives, we form alliances. In this case, developed and maintained by Michigan State University to support students word-wide. Look on it as the support hot line for universities and schools. The working engineers in this forum are less likely to help you with your homework, as they have more pressing problems of their own! Those that do respond should be congratulated for taking their valuable time for your assignments. As a former student, author, and professor, I also would not appreciate my students using an outside professional forum to do their homework..... But using another University would be "fair game." Austin jeff_n_moz wrote: > hi there, > > we are final year engineering students from india. we are currently > working on a fpga project and are stuck at a counter design. if any of > you could help us out, it would be great. > > we have to design an increment decrement counter. it is more of a > divider though. the ports are as follws: > input: inc,dec,clock,reset > output: f0 > > the counter is synchronous with an asynchronous reset.it should start > from producing a pulse for every 8 input clock pulses. it has 2 other > inputs, "inc" and "dec". on recieving a pulse at the inc port, on the > falling edge of pulse, it should start producing higher frequency, ie > divide by lesser.similiarly on reciving a pulse at the dec port, it > should decrement output frequency, i.e. increase the limit for count. > the highest frequency divide should be 16 and lowest as 1. > > we have been trying to get this done using VHDL, but have run into > multiple driver problem etc. we are unfamiliar with verilog but are > now learning it. > if any of you could spare some time for us, please mail us at the > above address with any sugestions or code(either VHDL or verilog). > > we thank all for their interest.Article: 68111
Jake,
You can supply just the edif netlist and an instantiation template. The
user then instantiates your core as a black box, and the Xilinx tools will
put it all together. The only hitch with that is that the user can't do a
pre-map simulation of the design with your macro in it. You can get
around if you use Synplicity by turning on the mapped vhdl or mapped
verilog output and supplying that as the simulation model. That mapped
output will be a netlist of unisim primitives and will simulate. It will
retain the internal signal names, but will lose the comments and any user
attributes, so it does at least obfuscate the source a little bit. You
might also be able to run an obfuscator on that to scramble the internal
signal names to make it a little harder to reverse engineer.
Jake Janovetz wrote:
> Hello-
>
> I'd like to package a few Xilinx modules with a particular product.
> They would be somewhat similar to Core Generator cores. However, Core
> Generator cores require Core Generator to be instantiated in any
> end-user design.
>
> Is there a way to package a Verilog or VHDL module so that it does not
> require Core Generator for the user to use it? Basically, I want
> folks using the WebPack to be able to use the modules. The obvious
> solution is to just include the Verilog/VHDL source and let the user
> add it to their project, but I'd prefer not to do that.
>
> Can an EDIF netlist be generated and used in a design somehow?
>
> Cheers,
> Jake
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68112ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0403250055.5f246cb3@posting.google.com>... > Dear Sir or Madam, > > I am using Cyclone FPGAs from Altera. > [...] > My question: > Is it possible to switch the clock in the "receiver"-FPGA in the case > of loss to an alternative "security" clock in the "receiver"-FPGA > so that some basic functions can still be performed in the > "receiver"-FPGA ? > > My processes in the VHDL modules of course have only one clock in the > sensitivity list. > > So what I am asking for is a kind of clock multiplexing within the > global > clock tree within the "receiver"-FPGA in the case of cable loss. > > Is somethning like that practicable ? Howdy Andrés, I see that the Stratix II supports dynamic clock switching (which chooses between a PLL output and a dedicated clock input pin), but I do not see it mentioned for the Cyclone, so I'm guessing you're out of luck for that concept, although you might check with Altera to make sure. You didn't describe the nature of the data on your cable, but the standard operating procedure (SOP) where I work is to use a FIFO for interfaces like this. The clock received from the cable would clock data into the FIFO, and a local clock would remove the data from the FIFO. This works well for the any of following situations: 1. You can remove "stuff" bits/bytes to make up for any difference in the clock rates (this method is strongly dependant on the difference in rates of the read and write clocks). 2. You know enough about the data being transmitted that you can be certain it won't overflow the FIFO by transmitting continuously (FIFO may have to be large, depending on the data pattern). 3. If you can insure that the local clock always runs faster than the cable clock. SONET uses #1. Ethernet more or less uses #2, although you can play tricks with the interpacket gap to make it look like #1 (or if you had real good control of your clock rates, you could set up the transmitter to run slightly slow, making it like #3). Good luck, MarcArticle: 68113
Brian Philofsky wrote: > > Rudi, > > I think you might be using old simulation models with a new netlist. > You mentioned you are using 6.2i but that message no longer exists in > the 6.2i models and has been reworded to make more sense (at least I Hi Brian ! First of all thanks a lot for your extensive reply ! I really appreciate it ! Now, the simulation models I use are the once that came with ISE 6.2i. I double checked my Makefile and it is using: XIL_LIB = +libext+.v -y /tools/ise/verilog/src/simprims where ise is the root installation directory for ise 6.2i. ... > Memory Collision Error on X_RAMB16_S2_S2:test.soc2.\i_sram/mem_l.I_2 > .display_zero at simulation time 53678.100 ns > A read was performed on address 0000 (hex) of Port A while a write was > requested to the same address on Port B. The write will be successful > however the read value on Port A is unknown until the next CLKA cycle. > > or > > Memory Collision Error on X_RAMB16_S2_S2:test.soc2.\i_sram/mem_l.I_2 > .display_zero at simulation time 53678.100 ns > A write was requested to the same address simultaneously at both Port A > and Port B of the RAM. The contents written to the RAM at address > location 0000 (hex) of Port A and address location 0000 (hex) of Port B > are unknown. > > Hopefully this updated messaging would make it more clear what has > occurred and this is something that should generally be investigated. Yes, these messages make more sense ! But still confuse the heck out of me, as my memories are instantiated from verilog: =================================================================== ... reg [15:0] mem[mem_size:0] /*synthesis syn_ramstyle="block_ram"*/; always @(posedge clk) if(en) addr_r <= addr; assign dout = mem[ addr_r[aw-1:0] ]; always @(posedge clk) if(we && en) mem[ addr[aw-1:0] ] <= din; ==================================================================== The way the memory is used it can be written OR read, but not both at the same time. I only use ONE address bus. So collisions are impossible ! May be I should qualify the read (dout assignment) with "!we" ?! Again, it all works, there are NO X'es propagating anywhere, it's just that message that is popping out all the time ! I literally get thousands of them. Even thought it all appears to work I would like to understand what it means before ignoring it and shipping a product that might fail in the field ! I know I can specify Read before write and write before read or something like that. Do you think it would help to force write before read ? Since when I'm writing I don't care about read data ? > My suggestion to you is to first recompile the simulation libraries > making sure to use the same version of software that generated the > netlist. I would then re-run simulation however I suspect you will How do I recompile the libraries ? I do have SP 01 installed as well, so I am a bit surprised that the models you are describing are having the "old messages". > Hopefully this information will help you prevent a possible problem with > your design down the road. > > -- Brian > Again, thanks a lot for your help ! Best Regards, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 68114
So, I'm trying to use these fancy DCMs that everybody is talking about ! Looking at the data sheet, these are some damn impressive pieces of work. So I have a design that uses two clocks. Neither one is available on my development PCB. Lets throw in some numbers to make it a bit simpler: I need 60 and 75 MHz, my development board only has a 100MHz oscillator. Hmm, sounds like a simple problem to solve. Pull up Arch. Gen., configure two DCMs, one fo 60 the other for 75 MHz. edit the files to pull out the IBUFG to serve both of the DCMs, done, right ?! wrong ! Now the fight with the tools begins. First Synplify, had to learn I had to put the clock in to separate groups so it will constrain them independently. So far so good. No I want for ISE to treat them separate as well. But it just refuses. It will accept the input clock as 100MHz, and one of the other once (either 60 or 75) as an independent clock, but the other one it will make dependent on the input clock, and come up with cycle times of 22++ nS. Now I did do a trial synthesis and P&R without the DCMs and know that theoretically there should be no problems whatsoever to meet the required timing. But ISE starts of the timing report with some 10 ns as the first entry: Slack: -9.417ns (requirement - (data path - clock path skew + uncertainty)) I have no idea where it is taking this from ! How do I tell ISE to treat ALL clocks separate, even though some of them are used in the same module ? Thanks, rudi ======================================================== ASICS.ws ::: Solutions for your ASIC/FPGA needs ::: ..............::: FPGAs * Full Custom ICs * IP Cores ::: FREE IP Cores -> http://www.asics.ws/ <- FREE EDA ToolsArticle: 68115
Rudolf Usselmann wrote: <snip> > Now, the simulation models I use are the once that came with ISE 6.2i. > I double checked my Makefile and it is using: > XIL_LIB = +libext+.v -y /tools/ise/verilog/src/simprims > > where ise is the root installation directory for ise 6.2i. I almost forgot you said you were using NC-Verilog. If you are using the Project Navigator GUI to create the netlist, there is a bug in that when you select NC-Verilog, it enables the switch to add a `uselib to the netlist. That was not intended and is scheduled to be changed in the next major version of the software. Really it does no big harm but would likely yield your -y switch useless. If you want, you could simply turn that off. It just turns it on when you change the simulator to NC-Verilog but you can turn it back off yourself if you prefer not to have the `uselib in there. Personally, I just pre-compile the library using compxlib and do not use `uselib or the -y switch. If the library is already compiled and mapped in your hdl.var/cds.lib files, then the design should compile faster and those libraries should automatically link in when you elaborate the design. I guess I can not explain why you have different libraries from me as even if you have the `uselib, it should point to the same area I would assume. It should have the new messaging. Perhaps the old libraries are referenced in your hdl.var or cds.lib files? Perhaps that has prescedence for linking over the -y or `uselib? I don't know. <snip> >> >>Hopefully this updated messaging would make it more clear what has >>occurred and this is something that should generally be investigated. > > > Yes, these messages make more sense ! But still confuse the heck > out of me, as my memories are instantiated from verilog: > > =================================================================== > ... > reg [15:0] mem[mem_size:0] /*synthesis syn_ramstyle="block_ram"*/; > > always @(posedge clk) if(en) addr_r <= addr; > > assign dout = mem[ addr_r[aw-1:0] ]; > > always @(posedge clk) if(we && en) mem[ addr[aw-1:0] ] <= din; > ==================================================================== > > The way the memory is used it can be written OR read, but not both > at the same time. I only use ONE address bus. So collisions are > impossible ! May be I should qualify the read (dout assignment) > with "!we" ?! You are definitly getting Dual-Port RAMs as that is what the X_RAM16_S2_S2 is. Perhaps you should look at your synthesis docs to make sure you are using the correct code to infer what you want. I would also double check your code to make sure you are not accessing the mem array elsewhere but I would guess that you may need to slightly adjust the code above to get it back to a single-port. I generally instantiate RAMs since I am a bit of a control freak when it comes to this stuff but I am now starting to infer RAMs as well but what really matters is how your synthesis tool inteprets the code so you have to get it right for that to happen. > > Again, it all works, there are NO X'es propagating anywhere, it's > just that message that is popping out all the time ! I literally > get thousands of them. Even thought it all appears to work I would > like to understand what it means before ignoring it and shipping a > product that might fail in the field ! You can disable the collisison checking and the messages will go away but it is a somewhat dangerous thing to do as if it does cause problems later (perhaps due to a change in your code) you will not be notified of the problem. It is almost always better to fix the problem than to shut it off. > > I know I can specify Read before write and write before read or > something like that. Do you think it would help to force write > before read ? Since when I'm writing I don't care about read data ? Those modes of the BlockRAM will not change this problem. This is commonly mis-understood. Those modes on the BlockRAM effect the outputs of the same port as the write is performed but does not effect the other port. If you get this back to a single-port which is what it sounds like you intended in the first place, it would fix this problem. That is what I would suggest unless you really did intend to create a dual-port. Single-port RAMs are definitly a bit easier to deal with unless you need simultaneous access. <snip> > How do I recompile the libraries ? I do have SP 01 installed as > well, so I am a bit surprised that the models you are describing > are having the "old messages". I kind of explained this above. You can use compxlib or if you are in Project Navigator, look in the online help under "compiling simulation libraries" (or something to that effect). Once the libraries are compiled and properly mapped in the hdl.var and cds.lib file, you do not need the -y switch or the `uselib for library refernce. You can also just continue to use the -y and not pre-compile. Or you can use the `uselib and not the -y switch. It is really up to you but in general, precompilation is more efficient. The Xilinx Synthesis and Verification Design Guide is the main doc for simulation and explains how to compile and use the simulator to more detail if you want to take a look at that. -- BrianArticle: 68116
Hi Jake, Instead of giving out the Verilog or VHDL source code, what you can do is to synthesize the Verilog or VHDL, and the synthesis tool will generate an EDIF netlist of the design (If you are using XST since ISE 4.1, instead XST will generate an NGC file, which is encrypted.). Then let the user instantiate the EDIF from their design. If you feel like EDIF is not a secure enough file format, you can run edif2ngd to convert the EDIF netlist to an NGO file, which is more secure. One thing to note about an NGO file is that, the NGO file generated by a newer version of the software like ISE 6.1 cannot be read by the older version of an software like ISE 3.3, so if you care about users still using older version of the software, you should generate an NGO file with an older version of the software. A a simulation model of the core can be generated by ngd2ver or ngd2vhdl after you run your design through ngdbuild Here is the script that will do everything I mentioned here. _______________________________________________________________________ edif2ngd Mydesign Mydesign.ngo ngdbuild -i Mydesign.ngo Mydesign.ngd ngd2ver -r -verbose -w Mydesign.ngd Mydesign_Simulation_Netlist.v ngd2vhdl -r -verbose -w Mydesign.ngd Mydesign_Simulation_Netlist.vhd _______________________________________________________________________ Kevin Brace P.S. Remove the weird numbers from my E-mail address when contacting me. Jake Janovetz wrote: > > Hello- > > I'd like to package a few Xilinx modules with a particular product. > They would be somewhat similar to Core Generator cores. However, Core > Generator cores require Core Generator to be instantiated in any > end-user design. > > Is there a way to package a Verilog or VHDL module so that it does not > require Core Generator for the user to use it? Basically, I want > folks using the WebPack to be able to use the modules. The obvious > solution is to just include the Verilog/VHDL source and let the user > add it to their project, but I'd prefer not to do that. > > Can an EDIF netlist be generated and used in a design somehow? > > Cheers, > JakeArticle: 68117
rrr@ieee.org (Rajeev) wrote in message
[snip]
>
> > I put a basic language comparison on-line. Note that some of the CF
> > component names are a bit out of date:
> >
> > http://www.launchbird.com/cgi-bin/language.py
>
> This is fascinating information. Thanks for taking the trouble to put
> together
> the comparison.
>
> A few questions,
>
> 1. The 4-bit register (for example) in Confluence did not show any
> clock or
> reset signals. How big a headache is it to deal with situations where
> different
> portions in a design use different clock or reset ?
In Confluence clocks, resets, and enables are implicit. You have the
power to clock, reset, or enable entire subsystems in one statement:
{reset reset_signal my_sub_system}
>
> 2. I presently use Quartus + VHDL => Stratix, and am trying out the
> Simulink
> + Altera DSP Builder design flow. I can see using Confluence to
> generate
> modules in a design, then export VHDL to build into the complete chip
> design
> in Quartus. Would this be a reasonable way to go ?
Yes. The generated HDL is FPGA synthesis friendly.
>
> 3. Any comments on high-level test and simulation vs Vector Waveform
> simulation ? I personally find the waveforms intuitive.
I like waveforms too. The generated C models and the executable
simulation models produce VCD dump files. So you can:
1. Write a high-level testbench an your favorite language.
2. Then inspect the results in a waveform viewer.
>
> 4. Have you any experience with how well FPGA tools are able to infer
> from the Confluence-generated VHDL ?
Pretty good. In the past, the only problems have been block rams, but
now the coding styles are aligned well with Synplicity.
>
> 5. Where can one see an example of a Confluence component and the
> corresponding
> exported VHDL ? Did you make the VHDL and Verilog portions of your
> table
> by hand, or are they output from the Confluence tool ?
Those were by hand. I would recommend using the tool to see for
yourself. The following will get you started:
(* CF test file. *)
is
{reg 8 {input "in" 1 8 $} {output "out" 2 $}}
{set "BuildName" "my_reg"}
{set "FileName" "my_reg"}
{set "GenVhdl" true}
{set "GenVerilog" true}
{set "GenC" true}
{set "CompileC" true}
Regards,
Tom
Article: 68118
the speed is in the data sheet in the form of set up times and clock to Q times
(the max clock is faster than these times will support, so it is not an issue),
and depends on the speed grade. There are two limiting speeds that if worked
around can help out a bunch: First is the write enable and output enable have
significantly longer set up times than the address or data. If you can work
your design so that these are hardwired to a '1', you'll not be limited by the
set-up times on these slower signals. The second limitation is the clock to Q
on the data outputs is pretty long compared to the rest of the fabric. In
order to get the best performance, you need to put pipeline registers on the
outputs of the BRAMs, and then place those registers so that they are
physically located immediately adjacent to the BRAM. Automatic placement will
NOT put them there.
Steve wrote:
> Hello,
>
> I plan to use the RAM_B4 of the SPARTAN IIE FPGA in my design. Does anyone
> know how fast it is? In particular I was wandering whats the fastest I can
> run the clock of the RAM?
>
> Thanks,
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 68119Wouldn't this be dependent on the USB implementation ? Are you implementing a USB core? I have used the FTDI 245BM usb module which is interfaced as a FIFO for all the fpga cares, with a couple of control signals. The data comes out of the chip through a bidirectional 8-bit bus. Phillips has some other chips that you use through I2C I guess the question is if you wanting to simulate the data after the it's been processed by a USB chip or core? Or, if the data is itself the USB packets for the USB core? ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0403260134.34c71a14@posting.google.com>... > Hi, > > I am searching for a VHDL package which I can use to generate USB traffic > for my VHDL testbench simulation in Modelsim. > That is some kind of Test Pattern which I can convert to VHDL test pattern > or maybe there exists some USB patterns in VHDL yet ? > > I would appreciate your information. > > Thank you in advance > > Andrés Vázquez > G & D > System DevelopmentArticle: 68120
I'm still mad at Xilinx for not putting built-in registers on the BRAMs. You don't have time to do anything with the BRAM output before registering it, so why burn up CLBs for that? Such registers are needed for the multipliers too. I did notice that the Tbcko of the slowest V2Pro part is listed as 1.68ns in the datasheet, so that does leave a lot of time to get to the registers if you are operating at, say 200MHz, and makes placement less critical. I don't know if the numbers are real though. -Kevin "Ray Andraka" <ray@andraka.com> wrote in message news:4064AB75.333670C0@andraka.com... > the speed is in the data sheet in the form of set up times and clock to Q times > (the max clock is faster than these times will support, so it is not an issue), > and depends on the speed grade. There are two limiting speeds that if worked > around can help out a bunch: First is the write enable and output enable have > significantly longer set up times than the address or data. If you can work > your design so that these are hardwired to a '1', you'll not be limited by the > set-up times on these slower signals. The second limitation is the clock to Q > on the data outputs is pretty long compared to the rest of the fabric. In > order to get the best performance, you need to put pipeline registers on the > outputs of the BRAMs, and then place those registers so that they are > physically located immediately adjacent to the BRAM. Automatic placement will > NOT put them there. > > Steve wrote: > > > Hello, > > > > I plan to use the RAM_B4 of the SPARTAN IIE FPGA in my design. Does anyone > > know how fast it is? In particular I was wandering whats the fastest I can > > run the clock of the RAM? > > > > Thanks, > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 68121
Austin Lesea wrote: (snip) > As a former student, author, and professor, I also would not appreciate > my students using an outside professional forum to do their homework..... I think most newsgroups will provide appropriate help if told they are homework problems. Also, the student should be expected to cite the newsgroup as a source of help. When a homework-like question is asked without stating it is homework, a variety of different answers tend to appear. -- glenArticle: 68122
If Spartan 3 delivery issues are still a problem for you, Altera can help. Any customer with a pending Spartan 3 order can get a quick delivery of 5 free Cyclone samples, 5 free serial config parts, and free Quartus II web edition software. Please refer to following url for details: http://www.altera.com/products/devices/cyclone/features/cyc-free_samples.html. Reminds me of one of the over 2700 Cyclone customers to date asking: Can I get more Cyclone parts? Yes. Really. Yes. Dave Greenfield Altera Corp "John_H" <johnhandwork@mail.com> wrote in message news:<B2L6c.21$Lf5.537@news-west.eli.net>... > groups.google.com had a sponsored link from http://www.4starelectronics.com/ > for Altera parts. I clicked for a quick check on this "Obsolete > Semiconductors" website and found Spartan-3s! Small quantities of ES and > non-ES parts. I didn't see any pricing because it seems they hide that > info. Request a quote and verify their stock numbers are real! Qty 25 > XC3S400-4PQ208CES are showing. > > "Brad Eckert" <nospaambrad1@tinyboot.com> wrote in message > news:7d4cc56.0403170952.6724372d@posting.google.com... > > I know this subject has been kicked around a lot here, but here we go > > again. > > > > Where can one get a small quantity of XC3S400s? I already have some on > > indefinite back order at Avnet. Maybe there is another source? > > > > Reminds me of John Cleese in the cheese shop: > > "Do you in fact have _any_ Spartan IIIs?" > > "Yes." > > "Really?" > > "No."Article: 68123
A few notes: Systemverilog is getting adopted very fast (not 'in 6 years'). Most of it is already in Synopsys's simulator, and will be in the next release of Mentor's. Cadence has also anounced support (I'm not sure of the schedule). Systemverilog has built in Vera--a nice assertion based test language. More is coming. Why is everyone saying that VHDL is used more by FPGA designers? Everyone I know (and I know a LOT of FPGA designers) is doing Verilog, with the exception of the aerospace industry (because of military contract requirements). Synopsys's CEO all but admitted that because of Systemverilog, they will not be doing add-on work with VHDL in the future. This is HUGE. And last, but not least, is ease of development. If I had to work somewhere where I had to learn Swahili, I could learn the language and get work done, but not nearly as efficiently as if I could work using English. Verilog has a lot in common with C. If you already are familiar with C, then learning Verilog will go much faster.Article: 68124
(tbiggs) wrote: > If you already are familiar with C, then learning Verilog will > go much faster. It's easier to write bugs in Verilog. Mastering VHDL will come sooner. -- Phil Hays Phil_hays at posting domain should work for email
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