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Does Leon have a step by step illustration on how to build instruction set, how to implement, how to write an assembler? it seems V8 is 35K meaning too tight for a xc2s100...not to mention adding in peripherals...But it is worth having a look at it... Kelvin "Marc Le Roy" <invalide@invalide.com> wrote in message news:c3jldt$o98$1@news-reader4.wanadoo.fr... > Kelvin wrote: > > Yeah, source code is there... > > It's a good example to study a microprocessor design. > > If you want to do that, have a look to this SPARC V8 processor under GPL > license : > http://www.gaisler.com/leonmain.html > > > Marc > > -- > Réponse par email http://cerbermail.com/?C9OVeUlzPc > Answer by email http://cerbermail.com/?C9OVeUlzPc >Article: 67851
wow...that is too complicated...it will take weeks to study Leon... "Kelvin" <kelvin8157@hotmail.com> wrote in message news:c3jqvg$8n4$1@mawar.singnet.com.sg... > Does Leon have a step by step illustration on how to build instruction set, > how to implement, how to write an assembler? it seems V8 is 35K meaning > too tight for a xc2s100...not to mention adding in peripherals...But it is > worth > having a look at it... > > Kelvin > > > > > > > "Marc Le Roy" <invalide@invalide.com> wrote in message > news:c3jldt$o98$1@news-reader4.wanadoo.fr... > > Kelvin wrote: > > > Yeah, source code is there... > > > It's a good example to study a microprocessor design. > > > > If you want to do that, have a look to this SPARC V8 processor under GPL > > license : > > http://www.gaisler.com/leonmain.html > > > > > > Marc > > > > -- > > Réponse par email http://cerbermail.com/?C9OVeUlzPc > > Answer by email http://cerbermail.com/?C9OVeUlzPc > > > >Article: 67852
> A simple fix is to change your boolean declaration to std_logic.
Yes, I bring example in my last post in another branch of this thread
demonstrating that std_logic sets immediately to HIGH as opposed to boolean
register. Another poster in lang.vhdl group proposed that the problem relies
in the fact that std_logic is multivalue signal initializing to 'U'. He
recommended to initialize a signal during declaration:
signal FINISHED : boolean := true;
.. and this does the trick! That is, the statement that the default values
are for simulation only in VHDL is wrong; synthezier uses them as well.
Seems that Xilinx tools incorrectly extract information about the initial
state of boolean register that should be asserted durig reset and the
internal reset logic incorrectly resets register to False instead of True.
Article: 67853
Hi, there:
These are the contents of my block RAM, in simulator I inject 00~FF into
i_addr on ever negative edge of clock...
How come I got 0000/3530/3031/3130/6632/3030...instead of the numbers I put
in INIT? What is the document
to look for INIT values?
Best Regards,
Kelvin
RAMB4_S16_S16 ram( .DOA(do_a), .DOB(do_b), .ADDRA(i_addr[7:0]), .CLKA(clk),
.DIA(16'b0),
.ENA(1'b1), .RSTA(1'b0), .WEA(1'b0), .ADDRB(d_addr[7:0]), .CLKB(~clk),
.DIB(d_in), .ENB(1'b1), .RSTB(1'b0), .WEB(we_b));
// synthesis attribute INIT_00 of ram is
"81f124203440241473f572fc71f6000a0908070600050403020100f210015000"
// synthesis attribute INIT_01 of ram is
"a2f183f10cf810042401243472f573fc70f01e007efe101f06f81001a3f182f1"
// synthesis attribute INIT_02 of ram is
"00000000000000000000080006fc1004b7f0a8f177f4100100f0100306f41003"
// synthesis attribute INIT_03 of ram is
"0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_04 of ram is
"0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_05 of ram is
"0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_06 of ram is
"0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_07 of ram is
"0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_08 of ram is
"0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_09 of ram is
"0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0A of ram is
"0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0B of ram is
"0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0C of ram is
"0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0D of ram is
"0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0E of ram is
"0000000000000000000000000000000000000000000000000000000000000000"
// synthesis attribute INIT_0F of ram is
"0000000000000000000000000000000000000000000000000000000000000000"
Article: 67854For simulation, you need to use "defparam" to intialize the ram. e.g defparam ram.INIT_00 = 256'h81f124203440241473f572fc71f6000a0908070600050403020100f210015000; HTH, Jim jimwu88NOOOSPAM@yahoo.com (remove capital letters) http://www.geocities.com/jimwu88/chips "Kelvin" <kelvin8157@hotmail.com> wrote in message news:c3k67m$aft$1@mawar.singnet.com.sg... > Hi, there: > > These are the contents of my block RAM, in simulator I inject 00~FF into > i_addr on ever negative edge of clock... > How come I got 0000/3530/3031/3130/6632/3030...instead of the numbers I put > in INIT? What is the document > to look for INIT values? > > Best Regards, > Kelvin > > > > RAMB4_S16_S16 ram( .DOA(do_a), .DOB(do_b), .ADDRA(i_addr[7:0]), .CLKA(clk), > .DIA(16'b0), > .ENA(1'b1), .RSTA(1'b0), .WEA(1'b0), .ADDRB(d_addr[7:0]), .CLKB(~clk), > .DIB(d_in), .ENB(1'b1), .RSTB(1'b0), .WEB(we_b)); > // synthesis attribute INIT_00 of ram is > "81f124203440241473f572fc71f6000a0908070600050403020100f210015000" > // synthesis attribute INIT_01 of ram is > "a2f183f10cf810042401243472f573fc70f01e007efe101f06f81001a3f182f1" > // synthesis attribute INIT_02 of ram is > "00000000000000000000080006fc1004b7f0a8f177f4100100f0100306f41003" > // synthesis attribute INIT_03 of ram is > "0000000000000000000000000000000000000000000000000000000000000000" > // synthesis attribute INIT_04 of ram is > "0000000000000000000000000000000000000000000000000000000000000000" > // synthesis attribute INIT_05 of ram is > "0000000000000000000000000000000000000000000000000000000000000000" > // synthesis attribute INIT_06 of ram is > "0000000000000000000000000000000000000000000000000000000000000000" > // synthesis attribute INIT_07 of ram is > "0000000000000000000000000000000000000000000000000000000000000000" > // synthesis attribute INIT_08 of ram is > "0000000000000000000000000000000000000000000000000000000000000000" > // synthesis attribute INIT_09 of ram is > "0000000000000000000000000000000000000000000000000000000000000000" > // synthesis attribute INIT_0A of ram is > "0000000000000000000000000000000000000000000000000000000000000000" > // synthesis attribute INIT_0B of ram is > "0000000000000000000000000000000000000000000000000000000000000000" > // synthesis attribute INIT_0C of ram is > "0000000000000000000000000000000000000000000000000000000000000000" > // synthesis attribute INIT_0D of ram is > "0000000000000000000000000000000000000000000000000000000000000000" > // synthesis attribute INIT_0E of ram is > "0000000000000000000000000000000000000000000000000000000000000000" > // synthesis attribute INIT_0F of ram is > "0000000000000000000000000000000000000000000000000000000000000000" > >Article: 67855
Nahum Barnea wrote:
> Hi.
> How can I run Xilinx map with -timing option through the ise gui ?
> Currently I am using command line, but I wish to use the ise gui.
>
> ThankX,
> NAHUM
Howdy Nahum,
If it doesn't show up in Map -> Properties, you need to turn on advanced
mode... which is under Edit -> Preferences -> Processes. Obvious, ain't
it? :-)
Have fun,
Marc
P.S. If you are an experienced command line user, you may find yourself
disappointed with the flexibility that the GUI provides. The check
boxes and help screens are nice, but if any of your input files (either
.ucf or your real source) change, even if you are just adding a comment,
the gui will try to re-run everything - not a big deal if your builds
are 5 minutes, but some of our designs take something on the order of
half a workday to run through (on a 3.2 GHz machine).
Article: 67856
The same problem (internal after-configuration reset to incorrect value)
occures not only to booleans but with integers as well. XST resets integers
to 0 and booleans to false by default, dispite of the asynchronous reset
expressin in VHDL code:
if RESET = '1' then
B <= True; -- resets to false
INT <= 9; -- resets to 0
elsif CLK ...
In fact, XST extracts default values not from the reset expression but from
signal declaration:
signal B: boolean:= true; -- resets to True
signal INT : integer := 9; -- resets to 9
Article: 67857
Hello,
i have a problem with a reset condition of a state machine i have written in
ABEL.
Source is like the following:
status state_register;
wst, ls1, ls2,... state; // line is shortened, much more states !
xilinx property 'Initialstate status wst';
status.clk = MY_CLK;
STATE_DIAGRAM status
STATE wst:
TEST_OUT_1 = 1;
TEST_OUT_1 = 1;
TEST_OUT_1 = 1;
Article: 67858I am developing a small circuit with XC95288 and I am wondering whether it is easy to read the content out. I guess since CPLDs are just a bunch of GALs, and GALs are easy to crack, it might be as easy to crack an XC95288. Am I right? Thank you. vax, 3900Article: 67859
Again (continued), sending was too early, sorry:
Hello,
i have a problem with a reset condition of a state machine i have written in
ABEL.
Source is like the following (cutted out the relevant parts):
status state_register;
wst, ls1, ls2, ls3, ls4... state; // line is shortened, much more
states !
xilinx property 'Initialstate status wst';
status.clk = MY_CLK;
STATE_DIAGRAM status
STATE wst:
TEST_OUT_1 = 1;
TEST_OUT_2 = 0;
TEST_OUT_3 = 0;
IF !MY_CMD THEN ls1 ELSE wst;
STATE ls1:
TEST_OUT_1 = 0;
TEST_OUT_2 = 1;
TEST_OUT_3 = 0;
goto ls2;
STATE ls2:
TEST_OUT_1 = 0;
TEST_OUT_2 = 0;
TEST_OUT_3 = 1;
goto ls3;
STATE ls3:
goto ls4;
and so on. Last state jumps back to wst. No other conditions, all like ls3.
So for every state i reach i think i should see one of my testoutputs at
high level, the other two on low level. It sometimes works fine, but often i
get a low level on all of the three line. In my opinion i should not reach
this condition, because in every state one of these output are set and ls3
and upwards, should not touch TEST_OUT_x, so level of ls2 is at the outputs
? Conclusion on my side was, that the state machine is not running. I tried
to manually reset the state machine with status.ar = !RESET, but still no
success. I have redirected a input PIN to an output PIN, feeding some clock
to the input and output is toggling. So i think the chip at all is running,
but my state machine not.
Can someone help me ?
Regards,
Martin
Article: 67860you might want to look into the documentation of SVF and XSVF documentation to get to know the details of what Sys ACE is actually doing. The xilinx application note : XAPP503 and XAPP058 might help you. Ram John Black <black@eed.com> wrote in message news:<405B6D6D.D203F236@eed.com>... > Hi, > I am amazed at how SysAce handles the hardware and software: the ACE > file should have 2 parts, FPGA programming bit file and the ELF file > which will be loaded into external memory. I know the trick is JTAG, but > I want to get a closer look what the underneath flow is. SysAce load the > bit file to program the FPGA, and then it ask PowerPC to load the ELF to > the external memory? What exactly happens? > I check out the data sheet of SysAce CF, but it does not mention this > flow. I wonder if somewhere else has this? > > Thanks.Article: 67861
Ulrich programmed a cpu on a Xilinx and you can download the VHDL code. http://www.it-effektiv.de/Download2/downloads2.php GNU License!Article: 67862
And then Jan Losansky wrote: > Hi, > > did anyone receive a Spartan-3 DSL-KIT from Memec yet? > > Jan I got mine a week ago. -- ************************************************ To reply, remove >.spam< and >.fake<Article: 67863
Hi, There is distinction between what you CAN do, and what you WANT to do. You CAN do this. You do not WANT to. Most PCI designs will need to use the PCI bus clock as a global clock input on the FPGA. I do not think any of the I/O on the D2E are connected to the global clock inputs of the FPGA. That aside, you could probably make it work, but it would be violating some of the PCI specification (in terms of the length of the signals from the edge connector to the FPGA). Would that be an issue? I don't know. If I were doing serious development work, I don't want to find out, either! Eric Hendra Gunawan wrote: > > I am sorry to interrupt but if you already have your own > non-PCI development board, such as D2E board from digilent, > is it possible that you can just use an adapter to connect > your board to the PCI slot? > > Thanks! > HendraArticle: 67864
"Eric Crabill" <eric.crabill@xilinx.com> skrev i meddelandet news:405B96DC.6E48295A@xilinx.com... > > Hi, > > For that board, specifically, the smaller chip is a Xilinx > ISP PROM that contains the bitstream. There are also some > jumpers to which you may attach a download cable, which can > send the bitstream to the device directly. That is only > useful for prototyping and debug. > > > Also, What kind of PCI cards have you developed with the > > help of this card? > > I've done a number of designs with it; one was a RAMDisk that > used the SDRAM as storage, another was a video peripheral to > drive a VGA monitor. I haven't had any problems with this > card. All the designs I did used the v3.0 PCI LogiCORE from > Xilinx, and I didn't have any problems with that, either. :) > > Eric What kind of ISP PROM do you use? and is the name of the programmer you use? How much did it all cost for you? (I had problems reaching the webite now not sure if the are rebooting the server or something...) //SPikeArticle: 67865
"Hal Murray" <hmurray@suespammers.org> wrote in message news:105qhjp3rdt8g71@corp.supernews.com... > > And combinational logic is subject to > >glitches. So, if you are going to use a latch, you have to make sure that > >during the entire time when the enable of your latch is asserted, the output > >from your combinational logic will never have any glitches. > > That's not obvious to me. Am I missing something? > > You do have to make sure that glitches don't get connected to clock > inputs or any other place where they might cause troubles. All clock inputs have to be synchronous. So, all your clock inputs have to be driven directly by an oscillator or by dedicated clock multiplier/divider/shifter such as Xilinx Digital Clock Manager (DCM). > But they > don't cause any trouble going into the data input of the latch. They > will flow through the latch so you have to check the other side of the > latch. During the entire time when your latch enable is asserted, your combinational logic is still processing data. During that time, there could be some glitches at the output of your combinational logic. And when that happens, the output of your latch will see the glitches, which can cause subsequent glitches for the rest of the system.Article: 67866
My design, which uses two cascaded DCMs, will only work intermittently; it seems the DCMs don't always start up. I've now put two dividers in the chip, one on the input clock & one on the DCMs output. At power up, I see the DCM output appear as a nice clock, then either collapse to a '1' or '0', or on the odd occasion, continue to work just fine. The board has 4 off 0.01 uF decouplers on the VCC_AUX supply, but the supply is common with the VCC I/O supply. Is this the reason I'm having problems?, e.g. is the AUX supply too noisy & does it need more decoupling? Any [constructive] suggestions welcome. TIA, Niv.Article: 67867
Do you have a delayed reset on the second DCM? You can't let the second DCM come out of reset until the first is locked. There is some appnote that explains this. -Kevin "Niv" <niv@ntlworld.com> wrote in message news:Ogo7c.801$w63.785@newsfe1-win... > My design, which uses two cascaded DCMs, will only work intermittently; > it seems the DCMs don't always start up. I've now put two dividers in the > chip, one on > the input clock & one on the DCMs output. At power up, I see the DCM output > appear > as a nice clock, then either collapse to a '1' or '0', or on the odd > occasion, continue to > work just fine. > > The board has 4 off 0.01 uF decouplers on the VCC_AUX supply, but the supply > is common with > the VCC I/O supply. Is this the reason I'm having problems?, e.g. is the > AUX supply too noisy > & does it need more decoupling? > > Any [constructive] suggestions welcome. > TIA, Niv. > > > > > >Article: 67868
I do have a reset delay circuit, but it does the same for both DCMs. I'll try & use DCM 1 lock as the reset for the 2nd, is that the sort of thing? Niv, (Also a Kevin really, backwards & truncated, in fact). "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:Kio7c.54744$1p.903420@attbi_s54... > Do you have a delayed reset on the second DCM? You can't let the second DCM > come out of reset until the first is locked. There is some appnote that > explains this. > -KevinArticle: 67869
Hi Niv, Niv wrote: > I do have a reset delay circuit, but it does the same for both DCMs. > > I'll try & use DCM 1 lock as the reset for the 2nd, is that the sort of > thing? Yes, cascading the lock/reset pairs works will in the designs I use with DCMs. Regards, JohnArticle: 67870
Nivek, you should actually delay the lock to use as the reset for the second; see Fig. 13 in XAPP132. -Kevin "Niv" <niv.nospam.goaway@ntlworld.com> wrote in message news:5po7c.47$Kn2.16@newsfe1-win... > I do have a reset delay circuit, but it does the same for both DCMs. > > I'll try & use DCM 1 lock as the reset for the 2nd, is that the sort of > thing? > > Niv, (Also a Kevin really, backwards & truncated, in fact). > > "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message > news:Kio7c.54744$1p.903420@attbi_s54... > > Do you have a delayed reset on the second DCM? You can't let the second > DCM > > come out of reset until the first is locked. There is some appnote that > > explains this. > > -Kevin > >Article: 67871
Thanks for your reply...I did put the defparam...but the problem is i can't correlate the numbers on simulator with the RAM contents... Kelvin // synthesis translate_off defparam ram.INIT_00 = "81f124203440241473f572fc71f6000a0908070600050403020100f210015000"; defparam ram.INIT_01 = "a2f183f10cf810042401243472f573fc70f01e007efe101f06f81001a3f182f1"; defparam ram.INIT_02 = "00000000000000000000080006fc1004b7f0a8f177f4100100f0100306f41003"; defparam ram.INIT_03 = "0000000000000000000000000000000000000000000000000000000000000000"; defparam ram.INIT_04 = "0000000000000000000000000000000000000000000000000000000000000000"; defparam ram.INIT_05 = "0000000000000000000000000000000000000000000000000000000000000000"; defparam ram.INIT_06 = "0000000000000000000000000000000000000000000000000000000000000000"; defparam ram.INIT_07 = "0000000000000000000000000000000000000000000000000000000000000000"; defparam ram.INIT_08 = "0000000000000000000000000000000000000000000000000000000000000000"; defparam ram.INIT_09 = "0000000000000000000000000000000000000000000000000000000000000000"; defparam ram.INIT_0A = "0000000000000000000000000000000000000000000000000000000000000000"; defparam ram.INIT_0B = "0000000000000000000000000000000000000000000000000000000000000000"; defparam ram.INIT_0C = "0000000000000000000000000000000000000000000000000000000000000000"; defparam ram.INIT_0D = "0000000000000000000000000000000000000000000000000000000000000000"; defparam ram.INIT_0E = "0000000000000000000000000000000000000000000000000000000000000000"; defparam ram.INIT_0F = "0000000000000000000000000000000000000000000000000000000000000000"; // synthesis translate_on "Jim Wu" <jimwu88NOOOSPAM@yahoo.com> wrote in message news:Buh7c.3517$vC.63@nwrdny03.gnilink.net... > For simulation, you need to use "defparam" to intialize the ram. e.g > > defparam ram.INIT_00 = > 256'h81f124203440241473f572fc71f6000a0908070600050403020100f210015000; > > HTH, > Jim > jimwu88NOOOSPAM@yahoo.com (remove capital letters) > http://www.geocities.com/jimwu88/chips > > > "Kelvin" <kelvin8157@hotmail.com> wrote in message > news:c3k67m$aft$1@mawar.singnet.com.sg... > > Hi, there: > > > > These are the contents of my block RAM, in simulator I inject 00~FF into > > i_addr on ever negative edge of clock... > > How come I got 0000/3530/3031/3130/6632/3030...instead of the numbers I > put > > in INIT? What is the document > > to look for INIT values? > > > > Best Regards, > > Kelvin > > > > > > > > RAMB4_S16_S16 ram( .DOA(do_a), .DOB(do_b), .ADDRA(i_addr[7:0]), > .CLKA(clk), > > .DIA(16'b0), > > .ENA(1'b1), .RSTA(1'b0), .WEA(1'b0), .ADDRB(d_addr[7:0]), > .CLKB(~clk), > > .DIB(d_in), .ENB(1'b1), .RSTB(1'b0), .WEB(we_b)); > > // synthesis attribute INIT_00 of ram is > > "81f124203440241473f572fc71f6000a0908070600050403020100f210015000" > > // synthesis attribute INIT_01 of ram is > > "a2f183f10cf810042401243472f573fc70f01e007efe101f06f81001a3f182f1" > > // synthesis attribute INIT_02 of ram is > > "00000000000000000000080006fc1004b7f0a8f177f4100100f0100306f41003" > > // synthesis attribute INIT_03 of ram is > > "0000000000000000000000000000000000000000000000000000000000000000" > > // synthesis attribute INIT_04 of ram is > > "0000000000000000000000000000000000000000000000000000000000000000" > > // synthesis attribute INIT_05 of ram is > > "0000000000000000000000000000000000000000000000000000000000000000" > > // synthesis attribute INIT_06 of ram is > > "0000000000000000000000000000000000000000000000000000000000000000" > > // synthesis attribute INIT_07 of ram is > > "0000000000000000000000000000000000000000000000000000000000000000" > > // synthesis attribute INIT_08 of ram is > > "0000000000000000000000000000000000000000000000000000000000000000" > > // synthesis attribute INIT_09 of ram is > > "0000000000000000000000000000000000000000000000000000000000000000" > > // synthesis attribute INIT_0A of ram is > > "0000000000000000000000000000000000000000000000000000000000000000" > > // synthesis attribute INIT_0B of ram is > > "0000000000000000000000000000000000000000000000000000000000000000" > > // synthesis attribute INIT_0C of ram is > > "0000000000000000000000000000000000000000000000000000000000000000" > > // synthesis attribute INIT_0D of ram is > > "0000000000000000000000000000000000000000000000000000000000000000" > > // synthesis attribute INIT_0E of ram is > > "0000000000000000000000000000000000000000000000000000000000000000" > > // synthesis attribute INIT_0F of ram is > > "0000000000000000000000000000000000000000000000000000000000000000" > > > > > >Article: 67872
Hal Murray wrote: >>Nonsense. I'll grant that it's harder to do a static timing analysis on a >>latch based design but it's perfectly doable. In an ASIC a latch design >>has a lot of advantages, > > > Thanks for the long explaination. I think I've worked with people > who built latched based CPUs back in the TTL/ECL days but I've > never worked on that sort of beast. (I know what a 373 is, but > my junk box only has 374s.) Using a LATCH can have its place: the 373 is a good example, where they are used by the ship load on ALE signals, and there, a LATCH extends the access time for the memory. > > My half-wiseass response would have been because the hardware > prefers FFs and the software (basically) doesn't support latches. > > Has anybody done a classic latched based two-phase clock design > in a FPGA? How do you distribute the clock? What sort of speed > did it run at, relative to a similar design using FFs. Can you > trick the software into doing a sensible timing report? I doubt it - but Philips do claim to be shipping a fully ASYNC 80C51 processor, into power critical telecom applications. http://www.semiconductors.philips.com/pip/P87CL888T_000_2.html I believe they had to develop/procure special tools themselves, to design this chip. -jgArticle: 67873
>All clock inputs have to be synchronous. So, all your clock inputs have to >be driven directly by an oscillator or by dedicated clock >multiplier/divider/shifter such as Xilinx Digital Clock Manager (DCM). Nonsense, on two levels. First, not all clock inputs have to be synchronous. If that was true we would only have one clock in the world. You do have to pay attention when crossing clock domains. Even if all your clocks are synchronous, it's possible (but generally unwise) to have several copies that are skewed from eachother. The simple example is clocking on the other edge. Some software can handle that case. You can also shift the clock a tiny bit in order to trade off setup time for hold time. (Of course, that skews the output too so analyzing timings gets more complicated.) Second, you don't need a direct or dedicated connection to the clock source. In many systems, it's common to gate the clock with an AND/NAND gate fairly high up the clock tree. The idea is to save power, both in the logic and in the clock tree, when that chunk of logic isn't needed. That's probably a (very) bad idea on today's FPGAs. They tend to have a clock-enable input at each local FF rather than anything higher up the clock tree. (I think that's generally a mux rather than a true clock enable.) But there is no fundamental requirement for a direct or dedicated connection. The general rule is that you have to meet setup/hold times, even when you consider clock skew. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 67874
On Sat, 20 Mar 2004 11:03:55 +0000 (UTC), buchty@atbode100.informatik.tu-muenchen.de (Rainer Buchty) wrote: >In article <slrnc5mm2o.7e0.ldoolitt@recycle.lbl.gov>, > Larry Doolittle <ldoolitt@recycle.lbl.gov> writes: >|> Infer flip-flops instead. In Verilog: >|> >|> reg foo; >|> always @(posedge clk) foo <= some_expression; >|> >|> or the more verbose and not necessarily more useful: >|> >|> reg foo; >|> always @(posedge clk or posedge rst) if (rst) begin >|> foo <= 0; >|> end else begin >|> foo <= some_expression; >|> end >|> >|> I'll leave the VHDL versions to someone else. >|> My fingers get tired too quickly. ;-) > >As if > > if rst='0' then > foo<='0'; > elsif clk'event and clk='1' then > foo<=some_expression; > end if; Can also be written as: if rst='0' then foo<='0'; elsif rising_edge(clk) then foo<=some_expression; end if; >would be any more typing than your Verilog example... (Just for curiosity: Any >reason for triggering on the reset's rising edge instead of its level?) This is a quirk of Verilog. Regards, Allan.
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