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Subroto Datta wrote: > ... snip ... > > A free version of the Tool can be downloaded at: > http://www.altera.com/education/univ/software/unv-software.html No it can't. That page says, in part: "Contact your University Program liaison to obtain copies of these programs and a license to use them. You must be a student, professor, or university staff member of a university that is a member of the Altera University program." and please do not toppost. -- Chuck F (cbfalconer@yahoo.com) (cbfalconer@worldnet.att.net) Available for consulting/temporary embedded and systems. <http://cbfalconer.home.att.net> USE worldnet address!Article: 67651
Just tried the design of XC2VP40-FF1152 with 40% full.Article: 67652
"Kevin Neilson" wrote: > The best of both worlds is to do all the design in HDL, and then use a tool > like Synplify's "HDL Analyst" to look at a schematic version of the > synthesized code. Using Synplify one can see either the RTL or structural > schematic. I agree with Kevin. It is a good thing to look at the rtl/netlist schematics. But let the computer draw them for you. Note that QuartusII ver 4.0 also includes an rtl viewer. -- Mike TreselerArticle: 67653
Pawan wrote: > sir/madam > > have added an ILA and ICON unit to my design ...however when i load it > using the analyser it simply hangs and says "wainting to be uploaded". > Please tell me whether this is due to the trigger. am not exaclty sure > whether this is due to wrong triggering...can u help me in this > regard...does this trigger have to be an externally generated signal.... > Pawan, The "Waiting for upload..." message in the waveform viewer means that a trigger condition has been sent to the FPGA and it is trying to meet the conditions to capture data. If nothing happens, that means either the match conditions never occur, or the clock is not connected or working properly. First, try the Trigger Immediate (T!) option -- this will capture data with no requirements whatsoever. If this still does not return data, verify that a valid clock signal is connected to the ILA clock pin and it is toggling. thanks, david.Article: 67654
Hi, What is the timing for Max II devices? Does it have worst case timing or does it have timing at room temp.? Thanks "Subroto Datta" <sdatta@altera.com> wrote in message news:<j303c.56629$RW7.3319@newssvr33.news.prodigy.com>... > The Quartus II 4.0 Web Edition Software with support for the new Stratix II > (90 nm FPGA's) and Max II (lHigh density, low power CPLD's) device families > is available for download at: > > http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmain.html > > For Max+Plus II users, Quartus II 4.0 (Subscription and Web Edition) > includes a Max+Plus II look and feel option that can be chosen from the > Tools->Customize->General Page. > > ------------------------------------- > > The Quartus II 4.0 Documentation includes the following resources : > > 1. The Quick Start guide covers the basic steps: creating a project, setting > device and timing constraints, compilation, walking through the tutorial. > This is available at > http://www.altera.com/literature/manual/mnl_qts_quick_start.pdf > > 2. If you are new to Quartus II and want a quick description of all the > capabilities present in the Quartus II tool, read the Quartus II Manual > first. The manual is available at: > http://www.altera.com/literature/manual/intro_to_quartus2.pdf > > 3. Before reading the Quartus II Handbook you may want to look at the > Quartus > Online demos. These links will point you to the Flash movie piece (listed > under > the Self running Documentation column for each topic) as well as the > relevant section in the Quartus II handbook (under the Documentation column > for each topic). These are available at: > http://www.altera.com/education/online_demo/onl-index.html?f=dshp&k=g3 > > 4. The Quartus II Handbook addresses, how to use the Quartus II tools for > design entry, synthesis, place and route, simulation, timing analysis, > device programming , and interfacing with other EDA tools like Modelsim, > VCS, > Synplify. Sections 7 and 8 of the Quartus II Handbook should address most of > your questions about Quartus Integrated synthesis for VHDL and Verilog. This > handbook document is located at: > http://www.altera.com/literature/lit-qts.jsp > > 6. The Quartus II Online Help available from the Quartus Help menu or by > clicking F1 inside Quartus on a message or in a dialog box. > > 7. A quick summary of Quartus II and the Xilinx tools is available at: > http://www.altera.com/products/software/pld/design/qts-x2a_migration.html > > 8. Finally if you are familiar with the Xilinx flow, read App Note 307, > about > how to convert a Xilinx design into Altera. It has examples how to convert > designs constraints and with with Coregen modules (e.g. memory, dll's, > multipliers, DDR designs ...). It also covers the command line tools for > synthesis, place and route and timing analysis and their switches for the > equivalent Quartus II tools, quartus_map, quartus_fit, quartus_tan. App Note > 307 is available at: > http://www.altera.com/literature/an/an307.pdf > > > - Subroto Datta > Altera Corp.Article: 67655
> First, you need to do more than just look at web pages. ISI is a > company that you need to talk with to get info on just what they do and > don't have. They have a full line of PGA adapters. It is unlikely that > they can't fit another socket. I got a quote back from them and as I expected the CPU socket route will cost a lot. They don't have anything already made so they say it will have to be cutsom. The price would include: PCB Design, PCB Fabrication, PCB Fabrication Test, Solder Stencils, and Setup. This is especially not cost effective for small quantities. Here are the estimates (based on board complexity): For 2 Boards: $10000-12000 For 50 Boards: $14000-15000 As you can see, this is very expensive (especially for small quantities). > If you plug into the CPU socket, you don't need to build any of the > other stuff at all. I am sure you can get adequate info on socket 7. > Intel had to document it for the chip makers. This would be part of the > chip spec. If not Intel, then AMD likely has a spec. They made parts > for it too, didn't they? Why do you need a socket that will be long > lived? Changing your FPGA design for a different socket should be no > big deal if you need to do that in a couple of years. Are you going to > mass produce this thing? When I mentioned board components I didn't mean the socket interface but the actual chips on the board (memory controller, bus controllers, etc). I wondered how wwell this was documented in terms of interfacing with the processor. I also worried that this would result in getting tied into a specific motherboard because it would only work with that specific chipset. As you can see from the costs mentioned above the cost of moving to a new socket would be very high! I figured that if I used PCI I could design a PCI-SBC that would interface with the other cards on the bus. At minimum it would need an FPGA, memory, support chips (bus, memory, configuration, etc), and a PCI interface. The rest could be on PCI cards that I can get for $20 at any local electronics store. I've seen FPGA PCI (busmaster) cards go for much less than $5000-$6000 each and with those cards I don't have to order more than one at a time (this is just prototyping, not mass production, at least for now). Hopefully I can find something much cheaper than even that. Let me know what you think, Thanks!Article: 67656
Errr, yeah, never mind. Wasn't thinking when I said "I think..."Article: 67657
Hi. I'm looking for any numbers/benchmarks of various FPGA tools (Quartus, ISE, Synplify Pro) on a fast Intel/Linux box vs a 1.2G UltraSparc III running Solaris 2.8. I'm running on the latter now. I've heard lots of stuff about Linux being faster, but I'd like a few number so I can justify setting up a box and trying it. I assume the floating licenses will share across - correct? Any suggestions about hardware/Linux versions would be appreciated too. I'm doing large Stratix (1s80) and Virtex II (xc2v8000) designs. On Solaris, I'm getting about 1 - 2 hour synthesis times and 3-6 hour place/route times. Thanks, DavidArticle: 67658
CBFalconer <cbfalconer@yahoo.com> wrote in message news:<4057371F.6364CB4F@yahoo.com>... > Subroto Datta wrote: > > > ... snip ... > > > > A free version of the Tool can be downloaded at: > > http://www.altera.com/education/univ/software/unv-software.html > > No it can't. That page says, in part: > > "Contact your University Program liaison to obtain copies of these > programs and a license to use them. You must be a student, > professor, or university staff member of a university that is a > member of the Altera University program." > > and please do not toppost. Hello CB, The web page has a link to the Quartus Web Edition which is FREE, and does not require you to be a student, preofessor or university student :-) - Subroto Datta Altera Corp.Article: 67659
foag wrote: > I invoke the Modelsim simulator from ISE Foundation (version 6.1). > After changing one or more vhdl source files in the ISE, how can I > hierarchically read in the modified vhdl sources ? The command modelsim needs to see is "vcom file.vhd" > Background: While invoking Modelsim by double click on "Simulate > Behavioral Model" for the top-level testbench vhdl file, the vhdl > files used for simulation do not correspond to the actual ones. I don't know how ISE works. Maybe that runs a sim on the last compilation. -- Mike TreselerArticle: 67660
Sounds like a neat idea. I've gotten pretty good at snaking wires through existing
walls. Managed to get cat5, video and phone to every room in the house I just sold. Just
starting over with the new house. Anyway, never thought of pulling a UPS line through
too. Instead, I have the answer machines etc plugged in where there are computers.
john jakson wrote:
> Ray Andraka <ray@andraka.com> wrote in message news:<405124C2.90A6538A@andraka.com>...
> > Just plug the darned thing into your computer's UPS and be done with it!
> >
> > Allan Herriman wrote:
> >
>
> Even more fun when tiny fingers reprogram everthing to xxxx state.
>
> When I get to move house next time to a new semi custom design, it
> will be cat5/6 AND 1 ups power line for light loads like vcr/clocks in
> every room if the builder will let me. I just never bothered to learn
> to program anything except proper computers.
>
> johnjakson_usa_com
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 67661Take a look at the new Virtex II Pro board from Insight Memec At about $200 it's seems to be a good buy "jerome" <jm_contact2002@yahoo.fr> wrote in message news:4056deca$0$282$626a14ce@news.free.fr... > Hi everybody, > > I would like to get some dev. board with FPGA. I am now thinking about > the Spartan 3, especially the one provided by Avnet. > > Could you please tell me following infos: > - Are there some troubles by using this board on a 5V or 3.3V PCI bus? > - What is the AvBus? How many pins on this bus? What are the signal > provided (several reset, clk?...). > - One of my aims is to manage video inputs or output with this device, > and I plan to use some daughter boards I would use or design by my own. > Has somebody tried it (including ADC, RAMDAC......)? With this kit or > others? some feedback? > > If somebody has some other advices about development boards? others FPGAS? > > Any feedback is welcome, > Thanks, > > Jerome.Article: 67662
Sandi Posl wrote:
> Hello,
>
> I don't have much experience with RTL and implementing designs, but I
> have encountered a strange problem.
>
> The design I am working on is rather large and I have been forced to
> remove some RTL modules from the design to get the total LUT's used down
> to 85% (during the synthesis phase, I'm using Synplify PRO) for the
> XC2V6000-5FF1152 FPGA. I would prefer to have the complete design
> implemented on the FPGA.
>
> As an experiment, I decided to synthesize my design by defining the
> Xilinx Virtex-E XCV3200E-8FF1156 FPGA in Synplify Pro, and the total
> LUT's used came to 95% (and the Virtex-II is almost twice the size!).
Howdy Sandi,
I think it falls well short of twice the size, but let's check...
XCV3200E: 73k logic cells
XC2V6000: 76k logic cells
Yep, WELL short :-) And just for fun:
XC2VP70 : 74k logic cells
XC2S5000: 75k logic cells
Don't let their numbering system fool you - it appears to be mostly
based upon "system gates", which as you can see above, never means the
same thing twice.
[...]
>
> The hardware platform I already have has the Virtex-II FPGA on it, so I
> have to implement my design on this FPGA.
You should get better results in almost every respect with the Virtex-II
(or ideally, a V2Pro) than with a Virtex-E. If I were you, I'd be very
happy to have it.
Good luck with the large design,
Marc
Article: 67663
Hi,
I am having hard time in understanding the following paragraph,
slave can run both faster and slower than the master, as long as
the rising edges for a specific clock( master as well as slave) aligns
with all rising edges of equal or higher frequency clocks.
How to interprete "aligns" here? If the clock frequencies are
different, how come their rising edges ALL aligning? To me the only case
is one clock is 2^n times faster than the other, but from the larger
context of this paragraph, this is not true.
Article: 67664On Tue, 16 Mar 2004 17:09:06 +0100, "Hur" <jyhur@dutepp0.et.tudelft.nl> wrote: >hello > >Are there any forum (on-line) or newsgoup on channel coding (and its >implementation)? > >If any, please guide me to where it is (web or news).....to exchange >idea...... news:comp.dspArticle: 67665
qlyus wrote:
> Just tried the design of XC2VP40-FF1152 with 40% full.
The design that I'm working on in an XC2VP40-FF1152 is 66% full
currently and PAR takes between 2 and 4 hours (just PAR, not mapping
[another hour] or synthesis [30 minutes]). Times and capacity were the
same for 6.1.3i.
We have other projects that didn't change any either.
Using the same project file, have you gone back and re-tried using
6.1.3i? 10x slower on the newer software is more than a little bizarre.
Good luck,
Marc
Article: 67666Marc Randolph wrote: > qlyus wrote: > >> Just tried the design of XC2VP40-FF1152 with 40% full. > > > The design that I'm working on in an XC2VP40-FF1152 is 66% full > currently and PAR takes between 2 and 4 hours (just PAR, not mapping > [another hour] or synthesis [30 minutes]). Times and capacity were the > same for 6.1.3i. > > We have other projects that didn't change any either. > > Using the same project file, have you gone back and re-tried using > 6.1.3i? 10x slower on the newer software is more than a little bizarre. Unless you just fluked onto some threshold, like a PC_RAM resource ceiling ? -jgArticle: 67667
Jim Granville wrote:
> Marc Randolph wrote:
>
>> qlyus wrote:
>>
>>> Just tried the design of XC2VP40-FF1152 with 40% full.
>>
>>
>>
>> The design that I'm working on in an XC2VP40-FF1152 is 66% full
>> currently and PAR takes between 2 and 4 hours (just PAR, not mapping
>> [another hour] or synthesis [30 minutes]). Times and capacity were
>> the same for 6.1.3i.
>>
>> We have other projects that didn't change any either.
>>
>> Using the same project file, have you gone back and re-tried using
>> 6.1.3i? 10x slower on the newer software is more than a little bizarre.
>
>
> Unless you just fluked onto some threshold, like a PC_RAM resource
> ceiling ?
> -jg
Definitely possible since the tools seem to sometimes do wildly
different things with even the most minor change in source code [I've
gone from meeting timing to failing timing by quite a bit in an
unrelated area to where I inverted a bit going into a FF].
Another data point: my memory usage during PAR went down a very marginal
amount when I went to 6.2.1 (from just above 1.2 GBytes to just below
1.2 GBytes).
Marc
Article: 67668In article <ET0Yb.1$sG5.1036@news.uswest.net>, mygarbagepail@hotmail.com says... > "jrh" <no@spam.com> wrote in message > news:Si_Xb.57494$P17.17621@fed1read03... >> Do you want the Forth to supervise a set of DSPs, or be a DSP? > I want the Forth to direct the operation of a multiply-and-accumulate > module, and to > have access to a fast complex multiply. > -Davka I think there is PLD/FPGA with an array of MACs available, but I don't remember the details. jrhArticle: 67669
david@therogoffs.com (David Rogoff) writes: > I'm looking for any numbers/benchmarks of various FPGA tools (Quartus, > ISE, Synplify Pro) on a fast Intel/Linux box vs a 1.2G UltraSparc III > running Solaris 2.8. I'm running on the latter now. I've heard lots > of stuff about Linux being faster, but I'd like a few number so I can > justify setting up a box and trying it. It's not Linux being faster than Solaris, but the Intel CPU being faster than the UltraSparc III. You would probably get similar result running Windows on the Intel box. > I assume the floating licenses will share across - correct? Any For Linux there's an altera_mainwin_lnx entry in the flex license file. I can't remember if Solaris uses the same or the altera_mainwin. > suggestions about hardware/Linux versions would be appreciated too. > I'm doing large Stratix (1s80) and Virtex II (xc2v8000) designs. On > Solaris, I'm getting about 1 - 2 hour synthesis times and 3-6 hour > place/route times. For Xilinx ISE I get excellent results using AMD Opteron based systems. Unfortunately Quartus does not yet run on the Opterons. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 67670
david@therogoffs.com (David Rogoff) wrote: > I'm looking for any numbers/benchmarks of various FPGA tools (Quartus, > ISE, Synplify Pro) on a fast Intel/Linux box vs a 1.2G UltraSparc III > running Solaris 2.8. I'm running on the latter now. I've heard lots > of stuff about Linux being faster, but I'd like a few number so I can > justify setting up a box and trying it. I can't believe, that Linux is faster than Solaris on the same machine. I think you mean using a multi-GHz processor (with linux) instead of a 1.2 G Sparc. When we switched from Solaris to Linux, we see about three times faster simulations (which is the real time eating stuff in my opinion). But we switched from 350 Mhz Ultra2 to 2Ghz P4. When doing evaluations before, we tested a 800 Mhz P3 against our different Solaris machines, showing clearly that fast and huge memory is very important (maybe more important than faster cpus). I didn't expect a 32bit processesor doing well for _realy_ big designs, because of memory limitations. bye ThomasArticle: 67671
Hi Rajeev, I checked with one of our timing constraint gurus. He can't be quite sure of exactly what the problem is without more information, so he has several suggestions on ways to fix this: - Make sure you are cutting the correct name. It's best to go to the Timing Report and copy the exact name that we are using (Registers in the memory will usually have a "~reg_addr" or "~reg_data" or something like that. You can also try using wildcards to avoid the extra characters: set_instance_assignment -to "my_memory_name*" -name CUT ON - You can try cutting from the source node: set_instance_assignment-from "my_source" -to * -name CUT ON - You can also try cutting all paths from clka to clkb set_instance_assignment-from clka -to clkb -name CUT ON - You can just define both clocks as absolute (not related) to avoid the check (note that this is only a good solution if there are no paths between these clocks you want checked). If this doesn't help, please send the list_path output of the timing path you want to CUT, and it'll help us be more specific. Regards, Vaughn Altera > Hello All, > > I'm doing a Stratix design using Quartus VHDL, I'm using > memory blocks to double-sync signals crossing clock domains > from slow to fast. Clocks are fractional multiples. > > (1) Static timing analysis checks the paths and complains. > > (2) The synthesizer rips up the memory blocks to consolidate > the instances which are in different places. > > I'd like to cut the timing paths, but when I try I get Timing > Constraint Ignored messages saying memory block MMM was removed > by synthesis. I'd like to let the synthesizer combine the > memories (saves device resources), I'd like not to consolidate > the memories by hand (preserves my existing organization), and > I'd like the timing analysis complaints to go away. > > What's the right thing to do ? > > Thanks in advance for your help and suggestions, > -rajeev-Article: 67672
> before, we tested a 800 Mhz P3 against our different Solaris machines, > showing clearly that fast and huge memory is very important (maybe > more important than faster cpus). > I didn't expect a 32bit processesor doing well for _realy_ big > designs, because of memory limitations. I have done some comparisons between 900M UltraIII and 2.5-2.8G P4 Xeons. And the Pentium chips are about 3 times faster almost in all cases (multigigabyte gate level simulations, RTL simulations, synthesis, STA etc.) Only reason to use Sun is the need of bigger than ~3G processes. And even that problem will be solved with Opterons. It seems that almost all the EDA software will be ported to Opteron. And to get >3G processes for gate level simulations, you need ~5-10M real gates of design. At least with current high end simulators. I don't see very bright future for Sun if they try to live with Ultra processors. They are just incredibly slow. --KimArticle: 67673
Marc, Thanks for your reply. Xilinx does have a strange numbering scheme, must be marketing driven..... I am happy to have the Virtex-II, I know that it superior to the Virtex-E, I was just a little disappointed when I compared the two FPGA's. But as you have pointed out, the Virtex-II is not almost twice the size of the Virtex-E. Thanks again. Sandi Marc Randolph wrote: > Sandi Posl wrote: > >> Hello, >> >> I don't have much experience with RTL and implementing designs, but I >> have encountered a strange problem. >> >> The design I am working on is rather large and I have been forced to >> remove some RTL modules from the design to get the total LUT's used >> down to 85% (during the synthesis phase, I'm using Synplify PRO) for >> the XC2V6000-5FF1152 FPGA. I would prefer to have the complete design >> implemented on the FPGA. >> >> As an experiment, I decided to synthesize my design by defining the >> Xilinx Virtex-E XCV3200E-8FF1156 FPGA in Synplify Pro, and the total >> LUT's used came to 95% (and the Virtex-II is almost twice the size!). > > > Howdy Sandi, > > I think it falls well short of twice the size, but let's check... > > XCV3200E: 73k logic cells > XC2V6000: 76k logic cells > > Yep, WELL short :-) And just for fun: > > XC2VP70 : 74k logic cells > XC2S5000: 75k logic cells > > Don't let their numbering system fool you - it appears to be mostly > based upon "system gates", which as you can see above, never means the > same thing twice. > > [...] > >> >> The hardware platform I already have has the Virtex-II FPGA on it, so >> I have to implement my design on this FPGA. > > > You should get better results in almost every respect with the Virtex-II > (or ideally, a V2Pro) than with a Virtex-E. If I were you, I'd be very > happy to have it. > > Good luck with the large design, > > MarcArticle: 67674
Stephan Buchholz wrote: > Take a look at the new Virtex II Pro board from Insight Memec > > At about $200 it's seems to be a good buy > > > "jerome" <jm_contact2002@yahoo.fr> wrote in message > news:4056deca$0$282$626a14ce@news.free.fr... > >>Hi everybody, >> >>I would like to get some dev. board with FPGA. I am now thinking about >>the Spartan 3, especially the one provided by Avnet. >> >>Could you please tell me following infos: >>- Are there some troubles by using this board on a 5V or 3.3V PCI bus? >>- What is the AvBus? How many pins on this bus? What are the signal >>provided (several reset, clk?...). >>- One of my aims is to manage video inputs or output with this device, >>and I plan to use some daughter boards I would use or design by my own. >>Has somebody tried it (including ADC, RAMDAC......)? With this kit or >>others? some feedback? >> >>If somebody has some other advices about development boards? others FPGAS? >> >>Any feedback is welcome, >>Thanks, >> >>Jerome. > > > Thanks for this info. The trouble is that I use only free tools, and the size of the available FPGA is then limited (I don't have access to this kit). I am thinking about image pre-processing, so I am looking for a PCI board. I have seen one with the SPARTAN fpga, but it is not yet available and the company delivers it only to industrial customers, and it is for personal use. I am afraid I could face this trouble several time.
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