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"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:<ZzCob.71991$Fm2.57178@attbi_s04>... > I read an article in "Scientific American" about how much information can be > compressed into a certain volume, and apparently all objects have a Shannon > entropy in addition to the thermodynamic entropy. Also, black holes have a > Shannon entropy that is based on the surface area of the event horizon. I > was totally lost. Can anybody else explain how Shannon's information > theory applies to black holes? > -Kevin I am really curious to know how thermodynamic entropy differs from Shannon's -if both based on "disorderness". Hawking's popular book "brief history of time" has a chapter on "arrow of time" which referred themodynamical entropy and at the same time "orderness" due to expansion of universe- bit abstract! Since we know entrpy of the universe increases - it is interesting what will happen to Shannon's entropy (if it is related!)- does information of the universe increase-big question!!! santoshArticle: 62576
Hello! I've searched Xilinx' knowledge-base and this group to no extend. When I run "Implement Design" on any project (also example-projects) for a XC9500 I get a Mapping a total of 23 equations into 2 function blocks......................... java.lang.RuntimeException: Attempting to format number '0.0' using pattern ''. at org.apache.xalan.xsltc.runtime.BasisLibrary.runTimeError(BasisLibrary.java:1063) at org.apache.xalan.xsltc.runtime.BasisLibrary.runTimeError(BasisLibrary.java:1071) ... from the "Fit" and later the "Generate HTML report"-processes. Obviously, this is a Java-problem. As far as I've seen the Webpack uses it's own version of the JRE in java\nt\jre, so I don't think this is a problem with my JRE-installation. I've got the latest SP installed. Any ideas? Thanks, SebArticle: 62577
> > do you want to say that Cable IV is Cable III backward compatible in > non-ECP mode? > > if it so then it very good information > antti Yes, see also the datasheet of the IV cable. It says that the cable will go to 'compatability' mode if the ECP mode of your parallel port is not enabled. This compatability mode appears to be cable III functionality. Henk van KampenArticle: 62578
on isp synario project navigator i always got this error?can anybody helps me?t y in any case Received process exit status -1 Possible system problem to spawn child process Done: failed with exit code: -001.Article: 62579
"Pete Dudley" <pete.dudley@comcast.net> wrote in message news:<mbudndF0keaqgD6iRVn-sQ@comcast.com>... > Henk > > Thanks for the notice. Is there any chance you will have a C compiler > available for picoblaze? > > > "Henk van Kampen" <henk@mediatronix.com> wrote in message > news:23ecd97d.0310240736.7b08c8dd@posting.google.com... > > Recently I have updated my Picoblaze (tm Xilinx) development tool > > pBlazIDE and added some documentation. Additionally I have published > > some example code and demonstration files. Please feel free to check > > this out. Its all freeware. Check under 'Tools'. > > > > Regards, > > Henk van Kampen > > www.mediatronix.com Not likely since the architecture of Picoblaze is not compiler friendly; it lacks a data stack which needs to be simulated or done by registers but then there are to few of them. A kind of pseudo C with control structures would be possible and can be useful, but this could be done with macro's. May be in a future release. Henk van KampenArticle: 62580
What version of software and what OS do you have? Seb K wrote: > Hello! > > I've searched Xilinx' knowledge-base and this group to no extend. > When I run "Implement Design" on any project (also example-projects) for > a XC9500 I get a > > Mapping a total of 23 equations into 2 function > blocks......................... > java.lang.RuntimeException: Attempting to format number '0.0' using > pattern ''. > at > org.apache.xalan.xsltc.runtime.BasisLibrary.runTimeError(BasisLibrary.java:1063) > > at > org.apache.xalan.xsltc.runtime.BasisLibrary.runTimeError(BasisLibrary.java:1071) > > ... > > from the "Fit" and later the "Generate HTML report"-processes. > > Obviously, this is a Java-problem. As far as I've seen the Webpack uses > it's own version of the JRE in java\nt\jre, so I don't think this is a > problem with my JRE-installation. > > I've got the latest SP installed. > > Any ideas? > > Thanks, > Seb >Article: 62581
Laurent:
Do you have a target date for the release of the USB based JTAG pod?
Also any specs on what it will support?
Steve Buchholz
"Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com> wrote
in message news:3f9e8436$1@news.vsnet.ch...
> Henk van Kampen wrote:
> > Dear Laurent:
> >
> >
> >>Could you explain what we can do with your JTAG option ? Can we do
> >>on-chip PicoBlaze debugging or ROM download ?
> >
> >
> > That is the idea. You can generate an SVF file by including in your
> > source file:
> > SVF "testjtag.svf"
> >
> > It will generate an SVF file based on the specifications in the JTAG
> > tab of the settings dialog and your source. Since this is still in its
> > infance please let me know is this is useful or what to change/add.
> > Since your are an probably an expert on JTAG considering your
> > Chamelion product I welcome your advice.
> >
>
> We are interested to do something in this way.
> I will ask my Team about the idea to do a OCD (On-Chip Debug) solution
> for the PicoBlaze.
>
> We have a relative good knowledge about JTAG on Arm processor.
> For the PicoBlaze, we have to add, in the PicoBlaze, a small register
> bank for On-chip debug solution including breakpoint fsm and to read
> back the PicoBlaze registry. We have naturally to think about the
> possibility to chain multi-PicoBlaze boundary Scan together
>
> Do you know if Xilinx have a support or source for On-chip debug
> machanism on JTAG ... other way we will do that!
>
> Then, we will use our new very low cost pockeTAG POD based USB to play
> the JTAG TAP to accelerate the job.
> And we will give you instructions for upgrade your software with our OCD
> solution, to be able to mark the breakpoint and to execute the on-chip
> debugging step.
>
> Our new POD will be about $89.-, and can run JTAG trace at the same
> speed that Cable IV (for download without verify, we are a better
> datarate on the JTAG !) but it works over USB with the big advantage of
> the power from USB, on MS and Linux. JTAG target can be 1V, 1.2V, 1.8V,
> 2.5V and 3.3V with 5V IOs tolerant! It can be a good solution for this
> JOB too. A low cost On-chip debug solution for a free Picoblaze Processor!
>
> >
> >>Actually, we are working on reconfigurable high speed automat machine.
> >>We will try to use picoblaze as base. One automat will have about 10 to
> >>100 picoblaze. The goal is to keep the speed and true multi-processing
> >>achitechture of sequencial function.
> >
> >
> > Very interesting. You will, however, need a lot of blockrams. And with
> > the JTAG option you can not use two PB's with one blockram. By the
> > way, how do you want to let the PB's communicate? One of my own wishes
> > for pBlazIDE is to be able to simulate several PB's in cooperation.
> > This will need some for of inter I/O port, which needs to be simulated
> > and therefore some how specified. I also have used more than 1 PB in a
> > design and have them communicate but that was by some form of
> > dual-ported RAM. So let me know what your ideas are.
>
> Yes you right, and when I saw the SPARTAN-III architecture, I thinking
> this was not a good idea. The RAM is bigger, but too much regrouped for
> this JOB.
>
> But for the first run we will do the job with 10 Picoblazes.
>
> >
> > Henk van Kampen
> > www.mediatronix.com
> Before, we have to contact Xilinx if they are interested or if that too
> much for this small PicoBlaze.
>
> Laurent Gauch
> www.amontec.com
>
>
>
Article: 62582
I did a VHDL program and now I'm downloading the program into a
Spartan2
XC2S100PQ208 chip . I ran all the programs ( FC2.... ) and now I'm
stucked at the Xilinx FLow Engine .
Below is the ucf file .
>>>>>>>>>>>>>>>>>> Archive manager was going to delete this, but it is way to precious <<<<<<<<<<<<<
-----------------------------------------------------------------------------
NET "clk" LOC = "P43";
NET "pre" LOC = "P41";
NET "seg<20>" LOC = "P37";
NET "seg<19>" LOC = "P36";
NET "seg<18>" LOC = "P35";
NET "seg<17>" LOC = "P34";
NET "seg<16>" LOC = "P33";
NET "seg<15>" LOC = "P30";
NET "seg<14>" LOC = "P29";
NET "seg<13>" LOC = "P23";
NET "seg<12>" LOC = "P22";
NET "seg<11>" LOC = "P21";
NET "seg<10>" LOC = "P18";
NET "seg<9>" LOC = "P17";
NET "seg<8>" LOC = "P16";
NET "seg<7>" LOC = "P15";
NET "seg<6>" LOC = "P14";
NET "seg<5>" LOC = "P10";
NET "seg<4>" LOC = "P8";
NET "seg<3>" LOC = "P7";
NET "seg<2>" LOC = "P5";
NET "seg<1>" LOC = "P4";
NET "seg<0>" LOC = "P3";
I ran the Implementation and I encounted an Error . It stated :
ERROR: MapLib:93 - Illegal LOC on Symbol "clk.PAD"( Pad signal = clk )
or BUFGP Symbol "C123962" (output signal = clk_BUFGPed ), IPAD-IBUFG
should only be LOCed to GCLKIOB site .
What does it mean ? I was wondering if I stated the
outputs ( NET " seg<20>" , NET " seg<19>" , NET " seg<18>") wrongly ?
Can anyone help me ?
Thanks a lot .
Below is my VHDL Electronic Dice ( 3 die ) program .
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity dice is port(
clk,pre : in std_logic; //inputs
seg: out std_logic_vector (20 downto 0)); //outputs
end dice;
architecture archdice of dice is
type dice_states is
(s1,s2,s3,s4,s5,s6,s7,s8,s9,s10,s11,s12,s13,s14,s15,s16,s17,s18,s19,
s20,s21,s22,s23,s24,s25,s26,s27,s28,s29,s30,s31,s32,s33,s34,s35,s36,
s37,s38,s39,s40,s41,s42,s43,s44,s45,s46,s47,s48,s49,s50,s51,s52,s53,
s54,s55,s56,s57,s58,s59,s60,s61,s62,s63,s64,s65,s66,s67,s68,s69,s70,
s71,s72,s73,s74,s75,s76,s77,s78,s79,s80,s81,s82,s83,s84,s85,s86,s87,
s88,s89,s90,s91,s92,s93,s94,s95,s96,s97,s98,s99,s100,s101,s102,s103,
s104,s105,s106,s107,s108,s109,s110,s111,s112,s113,s114,s115,s116,s117,
s118,s119,s120,s121,s122,s123,s124,s125,s126,s127,s128,s129,s130,s131,
s132,s133,s134,s135,s136,s137,s138,s139,s140,s141,s142,s143,s144,s145,
s146,s147,s148,s149,s150,s151,s152,s153,s154,s155,s156,s157,s158,s159,
s160,s161,s162,s163,s164,s165,s166,s167,s168,s169,s170,s171,s172,s173,
s174,s175,s176,s177,s178,s179,s180,s181,s182,s183,s184,s185,s186,s187,
s188,s189,s190,s191,s192,s193,s194,s195,s196,s197,s198,s199,s200,s201,
s202,s203,s204,s205,s206,s207,s208,s209,s210,s211,s212,s213,s214,s215,s216);
signal sm: dice_states;
begin
process (clk,pre)
begin
if pre = '1' then
sm <= s1;
elsif (clk'event and clk = '1' ) then
case sm is
when s1 => sm <= s2;
when s2 => sm <= s3;
when s3 => sm <= s4;
when s4 => sm <= s5;
when s5 => sm <= s6;
when s6 => sm <= s7;
when s7 => sm <= s8;
when s8 => sm <= s9;
when s9 => sm <= s10;
when s10 => sm <= s11;
when s11 => sm <= s12;
when s12 => sm <= s13;
when s13 => sm <= s14;
when s14 => sm <= s15;
when s15 => sm <= s16;
when s16 => sm <= s17;
when s17 => sm <= s18;
when s18 => sm <= s19;
when s19 => sm <= s20;
when s20 => sm <= s21;
when s21 => sm <= s22;
when s22 => sm <= s23;
when s23 => sm <= s24;
when s24 => sm <= s25;
when s25 => sm <= s26;
when s26 => sm <= s27;
when s27 => sm <= s28;
when s28 => sm <= s29;
when s29 => sm <= s30;
when s30 => sm <= s31;
when s31 => sm <= s32;
when s32 => sm <= s33;
when s33 => sm <= s34;
when s34 => sm <= s35;
when s35 => sm <= s36;
when s36 => sm <= s37;
when s37 => sm <= s38;
when s38 => sm <= s39;
when s39 => sm <= s40;
when s40 => sm <= s41;
when s41 => sm <= s42;
when s42 => sm <= s43;
when s43 => sm <= s44;
when s44 => sm <= s45;
when s45 => sm <= s46;
when s46 => sm <= s47;
when s47 => sm <= s48;
when s48 => sm <= s49;
when s49 => sm <= s50;
when s50 => sm <= s51;
when s51 => sm <= s52;
when s52 => sm <= s53;
when s53 => sm <= s54;
when s54 => sm <= s55;
when s55 => sm <= s56;
when s56 => sm <= s57;
when s57 => sm <= s58;
when s58 => sm <= s59;
when s59 => sm <= s60;
when s60 => sm <= s61;
when s61 => sm <= s62;
when s62 => sm <= s63;
when s63 => sm <= s64;
when s64 => sm <= s65;
when s65 => sm <= s66;
when s66 => sm <= s67;
when s67 => sm <= s68;
when s68 => sm <= s69;
when s69 => sm <= s70;
when s70 => sm <= s71;
when s71 => sm <= s72;
when s72 => sm <= s73;
when s73 => sm <= s74;
when s74 => sm <= s75;
when s75 => sm <= s76;
when s76 => sm <= s77;
when s77 => sm <= s78;
when s78 => sm <= s79;
when s79 => sm <= s80;
when s80 => sm <= s81;
when s81 => sm <= s82;
when s82 => sm <= s83;
when s83 => sm <= s84;
when s84 => sm <= s85;
when s85 => sm <= s86;
when s86 => sm <= s87;
when s87 => sm <= s88;
when s88 => sm <= s89;
when s89 => sm <= s90;
when s90 => sm <= s91;
when s91 => sm <= s92;
when s92 => sm <= s93;
when s93 => sm <= s94;
when s94 => sm <= s95;
when s95 => sm <= s96;
when s96 => sm <= s97;
when s97 => sm <= s98;
when s98 => sm <= s99;
when s99 => sm <= s100;
when s100 => sm <= s101;
when s101 => sm <= s102;
when s102 => sm <= s103;
when s103 => sm <= s104;
when s104 => sm <= s105;
when s105 => sm <= s106;
when s106 => sm <= s107;
when s107 => sm <= s108;
when s108 => sm <= s109;
when s109 => sm <= s110;
when s110 => sm <= s111;
when s111 => sm <= s112;
when s112 => sm <= s113;
when s113 => sm <= s114;
when s114 => sm <= s115;
when s115 => sm <= s116;
when s116 => sm <= s117;
when s117 => sm <= s118;
when s118 => sm <= s119;
when s119 => sm <= s120;
when s120 => sm <= s121;
when s121 => sm <= s122;
when s122 => sm <= s123;
when s123 => sm <= s124;
when s124 => sm <= s125;
when s125 => sm <= s126;
when s126 => sm <= s127;
when s127 => sm <= s128;
when s128 => sm <= s129;
when s129 => sm <= s130;
when s130 => sm <= s131;
when s131 => sm <= s132;
when s132 => sm <= s133;
when s133 => sm <= s134;
when s134 => sm <= s135;
when s135 => sm <= s136;
when s136 => sm <= s137;
when s137 => sm <= s138;
when s138 => sm <= s139;
when s139 => sm <= s140;
when s140 => sm <= s141;
when s141 => sm <= s142;
when s142 => sm <= s143;
when s143 => sm <= s144;
when s144 => sm <= s145;
when s145 => sm <= s146;
when s146 => sm <= s147;
when s147 => sm <= s148;
when s148 => sm <= s149;
when s149 => sm <= s150;
when s150 => sm <= s151;
when s151 => sm <= s152;
when s152 => sm <= s153;
when s153 => sm <= s154;
when s154 => sm <= s155;
when s155 => sm <= s156;
when s156 => sm <= s157;
when s157 => sm <= s158;
when s158 => sm <= s159;
when s159 => sm <= s160;
when s160 => sm <= s161;
when s161 => sm <= s162;
when s162 => sm <= s163;
when s163 => sm <= s164;
when s164 => sm <= s165;
when s165 => sm <= s166;
when s166 => sm <= s167;
when s167 => sm <= s168;
when s168 => sm <= s169;
when s169 => sm <= s170;
when s170 => sm <= s171;
when s171 => sm <= s172;
when s172 => sm <= s173;
when s173 => sm <= s174;
when s174 => sm <= s175;
when s175 => sm <= s176;
when s176 => sm <= s177;
when s177 => sm <= s178;
when s178 => sm <= s179;
when s179 => sm <= s180;
when s180 => sm <= s181;
when s181 => sm <= s182;
when s182 => sm <= s183;
when s183 => sm <= s184;
when s184 => sm <= s185;
when s185 => sm <= s186;
when s186 => sm <= s187;
when s187 => sm <= s188;
when s188 => sm <= s189;
when s189 => sm <= s190;
when s190 => sm <= s191;
when s191 => sm <= s192;
when s192 => sm <= s193;
when s193 => sm <= s194;
when s194 => sm <= s195;
when s195 => sm <= s196;
when s196 => sm <= s197;
when s197 => sm <= s198;
when s198 => sm <= s199;
when s199 => sm <= s200;
when s200 => sm <= s201;
when s201 => sm <= s202;
when s202 => sm <= s203;
when s203 => sm <= s204;
when s204 => sm <= s205;
when s205 => sm <= s206;
when s206 => sm <= s207;
when s207 => sm <= s208;
when s208 => sm <= s209;
when s209 => sm <= s210;
when s210 => sm <= s211;
when s211 => sm <= s212;
when s212 => sm <= s213;
when s213 => sm <= s214;
when s214 => sm <= s215;
when s215 => sm <= s216;
when s216 => sm <= s1;
end case;
end if;
end process;
seg <= "011000001100111101101" when sm = s1 else
"011001100111111111001" when sm = s2 else
"001111101100001101101" when sm = s3 else
"001111110110110011111" when sm = s4 else
"110110111110010110000" when sm = s5 else
"111100101100001101101" when sm = s6 else
"011001101100110110000" when sm = s7 else
"011000010110110011111" when sm = s8 else
"001111101100111111001" when sm = s9 else
"011000011011010011111" when sm = s10 else
"110110111011011101101" when sm = s11 else
"101101111110010110011" when sm = s12 else
"111100101100111111001" when sm = s13 else
"001111101100110110000" when sm = s14 else
"011000011110011011011" when sm = s15 else
"101101111011011101101" when sm = s16 else
"001111110110110110000" when sm = s17 else
"111100101100001011011" when sm = s18 else
"101101111110010011111" when sm = s19 else
"011001101100000110000" when sm = s20 else
"101101110110110011111" when sm = s21 else
"111100111011010011111" when sm = s22 else
"110110111110011111001" when sm = s23 else
"011000010110111101101" when sm = s24 else
"011001100111110110011" when sm = s25 else
"011000001100111111001" when sm = s26 else
"110110101100000110011" when sm = s27 else
"001111100111111111001" when sm = s28 else
"110110100111111111001" when sm = s29 else
"111100110110110011111" when sm = s30 else
"011000010110110110000" when sm = s31 else
"110110101100110011111" when sm = s32 else
"001111110110110110011" when sm = s33 else
"111100100111110110011" when sm = s34 else
"011001111110010110000" when sm = s35 else
"111100101100110011111" when sm = s36 else
"101101100111110110011" when sm = s37 else
"101101101100000110000" when sm = s38 else
"001111111011010011111" when sm = s39 else
"110110101100111111001" when sm = s40 else
"110110101100001011011" when sm = s41 else
"101101111110010110000" when sm = s42 else
"011000011011010110011" when sm = s43 else
"001111111011011101101" when sm = s44 else
"011000001100110011111" when sm = s45 else
"011001111011011111001" when sm = s46 else
"011000001100001011011" when sm = s47 else
"111100111110011111001" when sm = s48 else
"111100111011011111001" when sm = s49 else
"011001110110111011011" when sm = s50 else
"110110100111110011111" when sm = s51 else
"101101111110011101101" when sm = s52 else
"011000001100000110000" when sm = s53 else
"111100110110111101101" when sm = s54 else
"011001111110010011111" when sm = s55 else
"110110110110111111001" when sm = s56 else
"101101100111111101101" when sm = s57 else
"011000011011011011011" when sm = s58 else
"101101101100001111001" when sm = s59 else
"011000000111111101101" when sm = s60 else
"101101101100000011111" when sm = s61 else
"111100110110110110000" when sm = s62 else
"001111111110011101101" when sm = s63 else
"011000001100110110011" when sm = s64 else
"011001111011010110000" when sm = s65 else
"110110111110011101101" when sm = s66 else
"111100101100000011111" when sm = s67 else
"101101111110011111001" when sm = s68 else
"111100100111111101101" when sm = s69 else
"011000011110010011111" when sm = s70 else
"011001101100110110011" when sm = s71 else
"101101110110110110000" when sm = s72 else
"111100111110010110000" when sm = s73 else
"101101111011010011111" when sm = s74 else
"110110110110111101101" when sm = s75 else
"011000001100000011111" when sm = s76 else
"001111111011010110011" when sm = s77 else
"101101111110011011011" when sm = s78 else
"111100100111111111001" when sm = s79 else
"110110111110010110011" when sm = s80 else
"001111101100110011111" when sm = s81 else
"011000011011011101101" when sm = s82 else
"011001101100000110011" when sm = s83 else
"101101101100110110000" when sm = s84 else
"011001111110010110011" when sm = s85 else
"001111110110111101101" when sm = s86 else
"011000001100001101101" when sm = s87 else
"110110111110010011111" when sm = s88 else
"011000010110111111001" when sm = s89 else
"011001101100000011111" when sm = s90 else
"110110111110011011011" when sm = s91 else
"111100110110111111001" when sm = s92 else
"001111101100001011011" when sm = s93 else
"110110111011010011111" when sm = s94 else
"001111111110010110011" when sm = s95 else
"011001100111110110000" when sm = s96 else
"110110111011010110011" when sm = s97 else
"111100111110011101101" when sm = s98 else
"111100101100110110011" when sm = s99 else
"101101101100110011111" when sm = s100 else
"011000011110010110000" when sm = s101 else
"011001100111111011011" when sm = s102 else
"111100101100000110011" when sm = s103 else
"101101110110111101101" when sm = s104 else
"011000001100001111001" when sm = s105 else
"001111101100111011011" when sm = s106 else
"111100100111110011111" when sm = s107 else
"101101111011010110011" when sm = s108 else
"110110100111110110000" when sm = s109 else
"111100111110011011011" when sm = s110 else
"001111111011011111001" when sm = s111 else
"011000001100000110011" when sm = s112 else
"101101110110111011011" when sm = s113 else
"111100100111110110000" when sm = s114 else
"101101101100111111001" when sm = s115 else
"110110100111111011011" when sm = s116 else
"001111111110011111001" when sm = s117 else
"011000011011010110000" when sm = s118 else
"101101100111110011111" when sm = s119 else
"001111101100110110011" when sm = s120 else
"011001101100001101101" when sm = s121 else
"111100110110111011011" when sm = s122 else
"001111111110010011111" when sm = s123 else
"101101100111110110000" when sm = s124 else
"011000011011011111001" when sm = s125 else
"110110101100000110000" when sm = s126 else
"101101101100111101101" when sm = s127 else
"111100101100000110000" when sm = s128 else
"001111100111110011111" when sm = s129 else
"110110110110110110011" when sm = s130 else
"001111101100001111001" when sm = s131 else
"011001110110110110000" when sm = s132 else
"101101111011011111001" when sm = s133 else
"111100111110010011111" when sm = s134 else
"001111100111111101101" when sm = s135 else
"011000011110010110011" when sm = s136 else
"011001110110111111001" when sm = s137 else
"001111111011011011011" when sm = s138 else
"011000011110011101101" when sm = s139 else
"111100101100110110000" when sm = s140 else
"111100111011010110011" when sm = s141 else
"011001101100001011011" when sm = s142 else
"110110101100110110000" when sm = s143 else
"011001111011011101101" when sm = s144 else
"001111110110111111001" when sm = s145 else
"011000000111110110011" when sm = s146 else
"110110111011010110000" when sm = s147 else
"011001101100001111001" when sm = s148 else
"001111111110010110000" when sm = s149 else
"110110100111111101101" when sm = s150 else
"001111101100000011111" when sm = s151 else
"111100110110110110011" when sm = s152 else
"011001100111111101101" when sm = s153 else
"101101110110111111001" when sm = s154 else
"110110101100000011111" when sm = s155 else
"011001111110011101101" when sm = s156 else
"011001101100111011011" when sm = s157 else
"101101101100001101101" when sm = s158 else
"011000000111110110000" when sm = s159 else
"011001110110110011111" when sm = s160 else
"101101101100110110011" when sm = s161 else
"111100111011011101101" when sm = s162 else
"001111101100000110011" when sm = s163 else
"001111100111111011011" when sm = s164 else
"110110101100110110011" when sm = s165 else
"011001111011010011111" when sm = s166 else
"001111101100111101101" when sm = s167 else
"111100111011011011011" when sm = s168 else
"011001101100111111001" when sm = s169 else
"110110110110110110000" when sm = s170 else
"011001111110011011011" when sm = s171 else
"101101110110110110011" when sm = s172 else
"001111111110011011011" when sm = s173 else
"110110100111110110011" when sm = s174 else
"101101101100111011011" when sm = s175 else
"011001111110011111001" when sm = s176 else
"011000001100111011011" when sm = s177 else
"101101111011010110000" when sm = s178 else
"111100100111111011011" when sm = s179 else
"110110111011011111001" when sm = s180 else
"001111100111110110011" when sm = s181 else
"011001110110111101101" when sm = s182 else
"101101100111111011011" when sm = s183 else
"111100111011010110000" when sm = s184 else
"001111110110111011011" when sm = s185 else
"101101101100000110011" when sm = s186 else
"011000000111111111001" when sm = s187 else
"110110110110110011111" when sm = s188 else
"011001101100111101101" when sm = s189 else
"101101101100001011011" when sm = s190 else
"001111100111110110000" when sm = s191 else
"111100101100001111001" when sm = s192 else
"011000010110111011011" when sm = s193 else
"001111111011010110000" when sm = s194 else
"011001100111110011111" when sm = s195 else
"110110101100001101101" when sm = s196 else
"011000001100110110000" when sm = s197 else
"110110111011011011011" when sm = s198 else
"101101100111111111001" when sm = s199 else
"110110110110111011011" when sm = s200 else
"111100111110010110011" when sm = s201 else
"110110101100111101101" when sm = s202 else
"011000000111111011011" when sm = s203 else
"111100101100111101101" when sm = s204 else
"011001111011011011011" when sm = s205 else
"011000011110011111001" when sm = s206 else
"011001110110110110011" when sm = s207 else
"111100101100111011011" when sm = s208 else
"110110101100001111001" when sm = s209 else
"101101111011011011011" when sm = s210 else
"011001101100110011111" when sm = s211 else
"011000010110110110011" when sm = s212 else
"001111101100000110000" when sm = s213 else
"110110101100111011011" when sm = s214 else
"011000000111110011111" when sm = s215 else
"011001111011010110011";
end archdice;
Article: 62583Hi - Assign clk to a global clock pin: P77, P80, P182, or P185. Pinouts are listed in the data sheet. Or you could use PACE to assign pins. Bob Perlman Cambrian Design Works On 2 Nov 2003 09:17:36 -0800, lange360@hotmail.com (Amstel) wrote: >>>>>> insane quote removed by archive managerArticle: 62584
XP and the webpack 6.1 with the latest service pack (2 I think). Seb Marc Guardiani wrote: > What version of software and what OS do you have? > > > Seb K wrote: > >> Hello! >> >> I've searched Xilinx' knowledge-base and this group to no extend. >> When I run "Implement Design" on any project (also example-projects) >> for a XC9500 I get a >> >> Mapping a total of 23 equations into 2 function >> blocks......................... >> java.lang.RuntimeException: Attempting to format number '0.0' using >> pattern ''. >> at >> org.apache.xalan.xsltc.runtime.BasisLibrary.runTimeError(BasisLibrary.java:1063) >> >> at >> org.apache.xalan.xsltc.runtime.BasisLibrary.runTimeError(BasisLibrary.java:1071) >> >> ... >> >> from the "Fit" and later the "Generate HTML report"-processes. >> >> Obviously, this is a Java-problem. As far as I've seen the Webpack >> uses it's own version of the JRE in java\nt\jre, so I don't think this >> is a problem with my JRE-installation. >> >> I've got the latest SP installed. >> >> Any ideas? >> >> Thanks, >> Seb >> >Article: 62585
Hi, I am a newbie in the FPGA world, and we have got this Digilab board with Spartan XC2s200, and we are trying to run some test designs. The main problem we are facing is IO communication with the host or any other device such as LCD display, LED etc. I have 2 questions: 1) what program/ dirvers do i need for the host communication with the FPGA via the parallel port. 2) Does anybody have a help/tutorial website for interfacing FPGA with an IO board. Thanks in advance RajeshwaryArticle: 62586
"Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> ha scritto nel messaggio news:bo0pgq$bpr$1@agate.berkeley.edu... > How do you PROTCET the secret in the FPGA. THAT is the > key. You will have the same security problems with a key stored into an internal RAM: -Are you going to do a brute force attack? Then the way the key is stored is irrilevant; -Are you going to open the chip, put a probe after the decrypt circuit and read the unencrypted bitstream? Then the algorithm (as well as the key) is irrilevant; -Are you going to open the chip and reverse-engineer the decrypt circuit? Then it's more easy to read a key stored into a SRAM, rather than figure out how works a decrypt circuit with an hardwired key. The only security problem with the "hardwired private key" is that if someone manages to to steal the secrey key to the manufacturer, he will be able to decrypt all the bitfiles encrypted with its public key. But this is a matter of enterprise security and social engineering, not a technical issue. -- LorenzoArticle: 62587
"Nial Stewart" <nial@spamno.nialstewart.co.uk> wrote... > > Erik, are you not in danger of over charging the battery? > > Don't phone batterys degrade fairly quickly if they're > constantly trickle charged rather than being fully > discharged then re-charged? Are the characteristics > of your batterys different? > Have you done any long term tests with this set up? The battery that we use is a Niobium-Lithium (NBL) from Panasonic. More information: http://www.panasonic.com/industrial/battery/oem/chem/lith/niobium.htm Austin's post that parallels this one, makes the very important point that few engineers bother to understand battery chemistry or even read the data sheets (Nial - this is not directed at you). The major point is Lithium-Ion batteries have a bunch of problems that are a trade off against the extremely high energy per unit volume, and the capability of providing high currents (discharge entire battery in 1 hour), that makes them desireable for cell phones for example. NBL batteries are basically everything that a LiIon battery isn't. Very low self discharge (2%/year), not capable of providing much current (discharge the entire battery in no less than 400 hours) and with probably the crappiest energy per unit volume rating of any commercially viable battery on the market. This is the perfect (or as perfect as was available two years ago when we qualified it for design use) battery chemistry for this application. There are a lot of battery chemistries available. No single chemistry is right for every application. With fuel cells on the way shortly, we will soon have yet another option to understand. Regards, Erik Widding. --- Birger Engineering, Inc. -------------------------------- 617.695.9233 100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.comArticle: 62588
I'd like to use my Virtex2 to generate an off-chip power-on-reset, for other devices on the board. I thought about bringing the internal GSR signal to a pin, but Xilinx support (Case # 503734) said it's impossible. I am thinking about a state machine like that: Start --> POR --> Stop that will remain in "Stop" forever. I am worried about illegal transitions/states creating a mess on the board. Comments ? -- Tullio Grassi ===================================== Univ. of Maryland-Dept. of Physics | College Park, MD 20742 - US | Tel +1 301 405 5970 | Fax +1 301 699 9195 | ======================================Article: 62589
Well, if you initialize the flip-flops through the bitmap you'll know that they'll wake-up in a given state. For example, in Verilog: reg outgoing_rst = 1'b1; You can use FPGA Editor to verify that the FF in question is set to the desired value in the bitfile. This also applies to a counter you may want to use to time the assertion/de-assertion of the signal: reg [11:0] rst_counter = 12'b0; With this you know how that module will start from a fresh bitfile load. The remaining logic isn't very difficult and should be pretty reliable. For example, you could increment the counter with one of the clocks and stop incrementing when the MSB is "1". You'd use a case statement to fire off different events during the power-on reset cycle. You can even add a warm boot feature by having other logic reset the counter during operation. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Tullio Grassi" <tgrassi@cut_here.mail.cern.ch> wrote in message news:Pine.LNX.4.44.0311022103250.23452-100000@lxplus020.cern.ch... > I'd like to use my Virtex2 to generate an off-chip power-on-reset, > for other devices on the board. > I thought about bringing the internal GSR signal to a pin, but > Xilinx support (Case # 503734) said it's impossible. > > I am thinking about a state machine like that: > > Start --> POR --> Stop > > that will remain in "Stop" forever. > I am worried about illegal transitions/states creating a mess > on the board. Comments ? > -- > Tullio Grassi > > ===================================== > Univ. of Maryland-Dept. of Physics | > College Park, MD 20742 - US | > Tel +1 301 405 5970 | > Fax +1 301 699 9195 | > ====================================== >Article: 62590
Hi Josan, Josan wrote: > I am looking for Microblaze ports in Xess XSV800 (www.xess.com) board > platform and a ucLinux (www.uclinux.org) tutorial/experience in that board. As far as I'm aware, nobody has "ported" the microblaze uClinux package to that board. However, ports exist for a variety of Xilinx FPGAs and dev boards, including Spartan devices and so on. Usually, the changes required are simply to the UCF and MHS file, and similarly some trivial changes in the kernel to reflect your peripheral address map and so on. I recommend you subscribe to the microblaze uclinux mailing list and get active there - there are participants who have been through this process before and can assist you. http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux Regards, JohnArticle: 62591
Hi folks, Doing a board design with a 456 pin Xilinx FPGA, I find myself in the laborious and potentially error-prone process of building a symbol, footprint and part model from scratch. I am aware that commercial part libraries are available, but we are a university department and don't have those sort of $$$ to throw around for small-run custom designs. Anyway it seems to me that it would be in vendors' interests (Xilinx in this case) to provide verified symbol and footprint models for major design tools (Mentor, Protel etc)? A quick search of the Xilinx web site didn't turn up anything. Is there some point I'm missing here, or are my expectations unreasonable? Regards, JohnArticle: 62592
>Doing a board design with a 456 pin Xilinx FPGA, I find myself in the >laborious and potentially error-prone process of building a symbol, >footprint and part model from scratch. ... Most people want the schematics to be somewhat readable. That usually means breaking a 456 pin part up into several boxes. So I doubt if a vendor could provide a generic library part that would work for your design. (Yes, they could do the footprint.) It would be nice if there were a script/program that would take an intermediate file and make both the schematic library parts and the pin constraints file for the FPGA. Or something like that - the idea is to make sure they were kept in sync. My suggestion would be to just do it by hand and carefully check things. Then get a couple of friends to help you check it again. It would be worth bribing with beer/pizza and/or offering to trade roles when their design needs checking. What I've done on many occasions is to collect paper copies of all the data sheets and net lists (both by net and by part/pin) and all the other info you think might be interesting, and take over a conference room with a big table and do a check-everything level design review just before the board goes out. And gerber plots and ... Get somebody to check everything you can think of to check. They don't have to know much about your design, just have enough experience and common sense to read the data sheets and schematics and see if the connections make sense. (Double-double check the bubbles/inversions.) There is a lot of regularity in the footprint. Assuming your board level CAD system has some sort of scripting, you can probably write a program/script to generate a script that will make the part. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 62593
"Simon Peacock" <nowhere@to.be.found> wrote in message news:3fa45ff8$1@news.actrix.gen.nz... > I think you will find that you have over committed the pinout of the device. > For some reason this isn't always classified as a fatal error :-) Checked out the chip and there are only 146 I/O pins. Although my user config file only said that only 123 were used, the design still had more I/O blocks than the device could bond to pins. So even though the design could theoretically fit, if the UCF was considered, the place-and router would reject the design. D'oh! So I removed a load of I/O that was just redundant test signals and the software has compiled and fitted the design.Article: 62594
"Hal Murray" wrote: > >Doing a board design with a 456 pin Xilinx FPGA, I find myself in the > >laborious and potentially error-prone process of building a symbol, > >footprint and part model from scratch. ... > > Most people want the schematics to be somewhat readable. That > usually means breaking a 456 pin part up into several boxes. > So I doubt if a vendor could provide a generic library part > that would work for your design. (Yes, they could do the > footprint.) > > It would be nice if there were a script/program that would > take an intermediate file and make both the schematic library > parts and the pin constraints file for the FPGA. Or something > like that - the idea is to make sure they were kept in sync. Well ... about 18 months ago a project I was working on was seriously stalled due to this very issue. An engineer working with me spent no less than 18 hours working on defining schematic symbols and pcb footprints for just ONE large device. Part of the problem was that the EDA tool --maybe I should say "most EDA tools"-- failed miserably at having any intelligence about this process. The real problem, however, was that, if you ever need to edit, modify, re-use the part and, maybe, slice the pin set in a different way, you would be up for another frustrating EDA library maintenance marathon. A typical examplet that I had to face was migrating a design from something like a 2V1000 to a 2V500, where the footprints have a downward migration path. Anyhow, to make a long story (about three months work) short, I wrote a Windows application that allowed me to fully describe any component quickly. From that it's pushbutton to generate footprints, schematic symbols and a constraint file. Once all the IO for a component is entered, it is an easy matter to re-slice it any way you want. You can, for example, slice an FPGA to create separate schematic symbols for each bank, or merge banks, etc. As a benchmark, I can do an 456 pin FPGA in about 20 minutes, starting from scratch and finishing with pcb and schematic symbols. More imporantly, moving pins around or even totaly redoing the assortment of pins on the schematic symbols is a no-brainer after the intial work is done. In general terms, I developed a very low opinion of EDA tools, as it seems that those writing the code seldom have to use it for anything more than the few trivial examples that ship with the tools. I think it's fair to say that, today, you can spend $10K on a tool and fully expect to get unusable libraries and crippled library creation and maintenance tools. Maybe the OP can grab students from the Computer Science department and put them to work on a generalized component creation utility like what we built. I wish I could provide you with this utility, but it cost a lot of money to develop and I now consider it both a proprietary tool and a competitive advantage in many ways. I wish chip vendors would agree upon a component decription language/database format of some sort. These files could be published and CAD data very easily derived from them. That would be very useful. -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 62595
Andrew Steer wrote: > <snip> > It would be nice to have a terminal-like behaviour from the Cyclone > (and enter commands like "R13:240" to set register 13 to value 240). A > terse (and technically simpler) command structure such as "0af8[enter]" > meaning: "set register 0x0a to 0xf8" would be perfectly adequate for > the time being. The simplest would be to use more of the ASCII table, ( which comes for free) and use something like letters 'A..T' as SetAddressPointer and 'X' and 'Y' as read/write tags, then numbers in std HEX (opposite case to the AdrPtr). That way message parsing is much simpler, and very simple state engines/storage can do the job. Syntax is a little RPN : Rules : '0..9,a..f' : DBUf <- (DBuf x 16) + HexVal[RxChar] ( ie always send two nibbles ) 'A..T' : Adr <- AdrVal[RxChar] ( or can use a single char, 'P' to Adr <- DBuf ) 'W' : Regs[Adr] <- DBuf 'X' : Regs[Adr] <- DBuf Adr++ 'Y' : TBuf <- Regs[Adr] 'Z' : TBuf <- Regs[Adr] Adr++ typical strings B33WZ55WZaaWZ loads 33.55.aa into [1][2][3], and reads-back their contents while loading. A00XXXXXXXXXXXXXXX clears all regs to 00. -- etc -- -jgArticle: 62596
Martin Euredjian wrote: > "Hal Murray" wrote: > > >>>Doing a board design with a 456 pin Xilinx FPGA, I find myself in the >>>laborious and potentially error-prone process of building a symbol, >>>footprint and part model from scratch. ... >> >>Most people want the schematics to be somewhat readable. That >>usually means breaking a 456 pin part up into several boxes. >>So I doubt if a vendor could provide a generic library part >>that would work for your design. (Yes, they could do the >>footprint.) Of course - with a Xilinx part, breaking along IO bank lines, plus one for power, and one for config etc, is a pretty sensible approach. But I do take your point. I actually did find a symbol for the part buried deep in the mentor/expedition libraries, however it was monolithic, and the pin layout/ordering was, as best i could tell, random. > maybe I > should say "most EDA tools"-- failed miserably at having any intelligence > about this process. And doesn't the "A" in EDA stand for "automation"?? ... > In general terms, I developed a very low opinion of EDA tools, as it seems > that those writing the code seldom have to use it for anything more than the > few trivial examples that ship with the tools. I think it's fair to say > that, today, you can spend $10K on a tool and fully expect to get unusable > libraries and crippled library creation and maintenance tools. I'm pretty new to PCB design and so on, but have been repeatedly warned by several experienced designers "do not trust the library parts"... > Maybe the OP can grab students from the Computer Science department and put > them to work on a generalized component creation utility like what we built. Ha - student labour! This approach can be a bit hit and miss... > I wish I could provide you with this utility, but it cost a lot of money to > develop and I now consider it both a proprietary tool and a competitive > advantage in many ways. That's cool. It's not looking too bad - I'm about 4 hrs in, have done the schematic symbols, now doing the pin numbering. I should be done by the end of today. Happily my design is cleanly fractured along IO bank lines. > I wish chip vendors would agree upon a component decription > language/database format of some sort. These files could be published and > CAD data very easily derived from them. That would be very useful. Some existing standard like EDIF might be able to support this already. Regards, JohnArticle: 62597
Hello all, Firstly I would like to say that other than knowing what a FPGA is on a most basic level my knowledge about the subject is nil. I am looking at this from an application that needs a solution. I have seen about the place add on boards for PC's that act as co-processors. This is the interesting bit to me. Our research group is looking into building a computer (cluster perhaps) for calculation of particle dynamics, similar to CFD in application. Our programs are in C/C++ running on Linux ( any flavour will do). My questions are a) Will a FPGA co-processor board(s) offer a speed improvement in running our simulation jobs over using a 'traditional' cluster (mosix/Bewoulf)? Bearing in mind that ours will be the only job on the machine so can we reconfigure our FPGA boards to speed calculation? b) Can anyone recommend a good book that I can read and hopefully be able to ask more informed questions? Cheers MikeArticle: 62598
> I'm pretty new to PCB design and so on, but have been repeatedly warned > by several experienced designers "do not trust the library parts"... Yup. I relax a bit after I have successfully used a part on a design. It helps to check the raw gerber files to verify that they make sense. (The idea is to catch pin numbering errors and/or right/left top/bottom mirroring errors.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 62599
In article <c2cpb.85603$vO5.3153434@twister1.libero.it>, Lorenzo Lutti <lorenzol@despammed.com> wrote: >-Are you going to do a brute force attack? Then the way the key is >stored is irrilevant; Barring a MAJOR breakthrough in cryptanalysis, you CAN'T brute force 3DES or AES. A 112/128 bit keysize (3DES, AES 128-bit) is so large that anything short of lots of sci-fi nanotech are not gonna cut it. -- Nicholas C. Weaver nweaver@cs.berkeley.edu
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