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On Tue, 21 Oct 2003 07:23:25 -0700, Carl wrote: > Hi, > > My apologies if this is not the most appropriate group for this query. > > I am starting to have great difficulty sourcing some 74 logic parts from > my design in SMD (at least in small volumes). As I now have the chance > to make a new PCB revision I am wondeing if I couldn't do away with the > logic all together and use a PLD (CPLD). > > So for those who know the learning curve well, > > I have never used PLD's before, but have used PIC's (asm) and was > wondering if it is realistic for me to grasp enough of PLD design (not > necessarily VHDL) to implement some simple logic functions within a > month or so? > > Or is this likely to take far longer? > > I was playing with the Altera Quartus II software and it seems that by > using existing blocks this could be fairly straight forward. > > What do you think and what would be a good entry level device? > > Any comments would be greatly appreciated.! Verilog is much easier to learn and use than VHDL, unless someone is forcing you to use VHDL choose Verilog. If you know any C you should be able to learn enough Verilog to do a simple 74xx conversion in a week. BTW how old is this design? except for some bus transceivers I haven't used any 74xx stuff for 20 years.Article: 62176
"Zak" <chippa11@hotmail.com> wrote in message news:3f9537c8$0$21651$afc38c87@news.optusnet.com.au... > Am I correct in thinking that a design lab that was simuated and implemented > onto a demo board with Xilinx Foundation 3.1, can have its bitstream used > with another version such as Xilinx Foundation 4.2i? The *.bit file can be used with any version of the tools that supports the device it was originally generated for. /MikhailArticle: 62177
Jan De Ceuster <jandc@elis.ugent.be> writes: > And now it works... Maybe Altera should write a cleaner script that > first checks if it's a Red Hat distribution... Yes. But it would have been even better if they checked for the *features* they need rather than checking the distribution. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 62178
Jaroslaw Guzinski <jarguz@sunrise.pg.gda.pl> wrote in message news:<Pine.GSO.4.58.0310210953060.27819@sunrise.pg.gda.pl>... > In laboratory I have few boards with Altera Flex600. Boards are connected > with PC using ByteBlaster. On PC I have Win98 OS. On the all PC is the > same software. > Problem is that on some computers after configuring ALTERA device after > some time (sometimes very short) project in Altera is deleteted. > How to solve that problems without disconnecting ByteBlaster after > programming? > > We had a similar problem some time ago. We suspected the PC pokes the printer port every so often (something to do with polling peripherals??), causing the nStatus line to reset. We much reduced the problem by removing the LPT1 entry in the PCs device list, so that the PC doesn't know there is a printer port. YOu could also try adding a toggle switch on the nStatus line betweeh the ByteBlaster and the target.Article: 62179
Jaroslaw Guzinski wrote:
> In laboratory I have few boards with Altera Flex600. Boards are connected
> with PC using ByteBlaster. On PC I have Win98 OS. On the all PC is the
> same software.
> Problem is that on some computers after configuring ALTERA device after
> some time (sometimes very short) project in Altera is deleteted.
I assume this means the downloaded image is corrupted.
> How to solve that problems without disconnecting ByteBlaster after
> programming?
Sounds like a intermittent connection on the ByteBlaster or PC connector.
-- Mike Treseler
Article: 62180
Carl wrote:
> I was playing with the Altera Quartus II software and it seems that by
> using existing blocks this could be fairly straight forward.
Your design is fairly simple and time is short,
so consider using Quartus schematic capture
for your first design.
File, New, Block Diagram, RightClick Insert, Symbol,
libraries\other\maxplus2\74374 LeftClick.
... and you're off to the races.
Since you already know the circuit, you can likely
get it functioning without simulation.
Learn the HDL for a testbench for your schematic block
using the Modelsim CD. Then redo the design in HDL
and rerun the testbench as a tutorial.
-- Mike Treseler
Article: 62181"Carl" <jiz_king@hotmail.com> wrote in message news:8aec9d92.0310210623.443ba2d5@posting.google.com... > I have never used PLD's before, but have used PIC's (asm) and was > wondering if it is realistic for me to grasp enough of PLD design (not > necessarily VHDL) to implement some simple logic functions within a > month or so? > > Or is this likely to take far longer? Assuming you're not learning logic from scratch: When I first started with CPLD's I was using a rather early Xilinx Foundation, covertly provided to me, and it went something like this: Day 0: Be friendly towards the FAE when he's on-site anyway. Get a hint. Day 1: Get the tool installed. Why the hell won't my schematic of a simple buffer translate? Day 2: Discovered that I needed I/O buffers. Place a single counter into the design, figure out how to put the pins where I want them. It translates and fits! Build a small board with an oscillator, an XC9536, and a LED. Borrow a Parallel-III cable. Day 3: Programming works, LED is blinking (very quickly). Conclude that this is feasible. Day 6: Call the friendly FAE. "This is a tool bug. Do this instead." Get a few tricks and nasty jokes. Day 10: Create a better Parallel-III cable, give back the original. Day 20: "Parallel port to IDE interface CPLD" is working. The prototype has analogue bugs and I'm out of room in the XC95108. Add an external filter as this is hobby and I'm living off a friendly Xilinx FAE and samples. Day 200: Design-in lots of Xilinxes: I know they will work and the FAE is nice. As to the Schematic|VHDL|Verilog debate|mudthrowing|discussion, I've used all three professionally. It's somewhat like the assember|Pascal|C programming-language question. It depends on what you're doing which one is best, but I believe that for the beginner who comes from a schematic world, a quick success experience is important. Once you reach the level of complexity where you're spending as much time figuring out your own schematics as designing, learning one of the HDL's is a good idea. They are extremely powerful tools once you master them. > What do you think and what would be a good entry level device? An in-system programmable CPLD like the XC9572 is nice. It's also my preferred device for home projects, no reason to hide that. They are a bit power hungry, but they are well behaved, their routability is good enough that you generally don't have to think about it, and hard to kill. The 3.3V CoolRunner XPLA3 is nice too, but the tool is not as perfectly polished as for the old XC9500 series and the device is a bit tighter on resources. Those are Xilinxes, Xilinx' later tools are a bit weak on the schematic side, I prefer the older Foundation 3.3 for schematics but that's me. If you known an HDL the later tools work perfectly. Altera has some nice xPLDs too but I've only used their FPGA's so I can't comment on those other than that I know we use them in volume, and they work. Their latest Quartus tool works as well as Xilinx'. I've used Lattice's older devices, and back then they and the tool were the reason I ended up in the Xilinx/Altera camp. Whatever you do, choose something in-system programmable. It's invaluable once you enter the bughunting phase. When calculating the total cost, don't forget the programming connection and the time spent programming the device. /KasperArticle: 62182
Quartus II on SuSE Linux 8.1
-- Installs fine.
-- quartus -g comes up fine.
-- Loads an existing project fine.
-- Recompiles a windows precompiled project fine
-- Can't compile a new project itself.
Tries for a while then says
"Error: Current module quartus_map ended unexpectedly".
-- Mike Treseler
Article: 62183"Rene Tschaggelar" <none@none.none> ha scritto nel messaggio news:2e2341ee57ca2c93136ba7178992b4a1@news.teranews.com... > The G8 membership might distort the picture a bit. I agree. In fact, I don't think we will be members for much time again. > South of say Bolognia there is not much Technology > anymore. ^^^^^^^^ "Bologna", I live at 20 km from there. :) > A few Tomatoes and Olives plus lots of companies using the > cheap > labour for simple jobs. You forgot pizza, mafia and mandolino! <g> As someone has already told you, there are some exceptions. The south of the Italy is less industrialized than the North, but still it is more industrialized than some southern and midwest areas of the USA. However, your consideration is sostantially correct. The main reason of this decadence (that involves North as well as South, even if in different ways) is due to the political choices made from the eighties to the present time: constant reduction of funds for school and research, cultural impoverishment driven by media, laws that support cunning people, tax evasion and corruption (and I might add that things are going to get even worse, with the current government infested by thieves, xenophobes, separationists and so on). In spite of this, however, we still have something to say; italians are those who very often invent things (even if sometimes they do it outside of Italy). FPGA/DSP neglect is more a "cultural" problem rather than a technological one. -- LorenzoArticle: 62184
VHDL is by far the language to use for FPGAs. According to 2001 statistics 65% of the FPGA market uses VHDL and 15% uses Verilog. What makes VHDL hard to learn is its use of strange logic operators (and, or, not, xor) rather than the cryptic (but perhaps familar ones of C). This is the main extent of the similarity of between Verilog and C. Some consider VHDL hard to learn due to its strong typing. Strong typing requires you to learn some rules for correct expression formation. These rules are explained in the paper, VHDL Math Tricks of the Trade, which is available at: http://www.synthworks.com/papers So some consider Verilog easier because it does not force one to learn strong typing rules. One company that delivers IP in both VHDL and Verilog, requires its Verilog designers to use a lint tool which enforces' VHDL strong typing rules on Verilog. In a paper they presented at DVCon last year, they stated that 75% of the time a strong typing rule violation was a real bug in the design. Just a little food for thought. Verilog also requires you to learn adhoc rules about proper use of assignments so you can avoid execution race conditions. If you don't follow these rules, you code may execute differently on different simulators. There is nothing in the Verilog simulator that warns you of anything being wrong. Have a bad day coding with Verilog, you better have a lint tool and a good testbench. Have a bad day coding with VHDL and you will get abused by the compiler but you will not introduce bugs into your design. Personally, I cannot see why anyone would use Verilog. I would not recommend it to anyone (other than the competition :)). Cheers, Jim Lewis -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Jim Lewis Director of Training mailto:Jim@SynthWorks.com SynthWorks Design Inc. http://www.SynthWorks.com 1-503-590-4787 Expert VHDL Training for Hardware Design and Verification ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ B. Joshua Rosen wrote: > On Tue, 21 Oct 2003 07:23:25 -0700, Carl wrote: > > >>Hi, >> >>My apologies if this is not the most appropriate group for this query. >> >>I am starting to have great difficulty sourcing some 74 logic parts from >>my design in SMD (at least in small volumes). As I now have the chance >>to make a new PCB revision I am wondeing if I couldn't do away with the >>logic all together and use a PLD (CPLD). >> >>So for those who know the learning curve well, >> >>I have never used PLD's before, but have used PIC's (asm) and was >>wondering if it is realistic for me to grasp enough of PLD design (not >>necessarily VHDL) to implement some simple logic functions within a >>month or so? >> >>Or is this likely to take far longer? >> >>I was playing with the Altera Quartus II software and it seems that by >>using existing blocks this could be fairly straight forward. >> >>What do you think and what would be a good entry level device? >> >>Any comments would be greatly appreciated.! > > > Verilog is much easier to learn and use than VHDL, unless someone is > forcing you to use VHDL choose Verilog. If you know any C you should be > able to learn enough Verilog to do a simple 74xx conversion in a week. > BTW how old is this design? except for some bus transceivers I haven't > used any 74xx stuff for 20 years.Article: 62185
Followup to: <bn3f57$41o$1@agate.berkeley.edu> By author: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) In newsgroup: comp.arch.fpga > > Actually, mixed Dram/Logic (what gets your the ~10x greater memory > density for the HSRA) has effectively failed. It required too much > process fiddling, which nobody wants to do these days. > > Also, then you have the joy of the DRAM page access time anyway, so > you save on the pin crossings, but the rest of the latency is still > there, and still measured in several clock cycles. > It is, but you get *HUGE* amounts of data for each access. Existing DRAMs mux away an amazing amount of the data read for each array access. I suspect that DRAM integration is going to happen sooner or later, however, it's not going to happen just yet. -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 62186
After searching for the source of an error for quite a long time, I've decided that I need some help, and once again you guys drew the shortest straw ;-) I have a 8 bit DFF with output q[7..0]. This feeds the net dff_inst23_out[7..0]. (The reason this net is given this name, was to see if the error actually was located where I thought it was, since the original error pointed to some temp net.) Both the DFF output and the net is 8 bits wide, and still I get this error message: Error: Net dff_inst23_out[6] cannot be assigned more than one value Error: Net is fed by std_8bit_dff0:inst8|lpm_ff:lpm_ff_component|dffs[6] Error: Net is fed by std_8bit_dff0:inst9|lpm_ff:lpm_ff_component|dffs[6] Error: Net is fed by std_8bit_dff0:inst23|lpm_ff:lpm_ff_component|dffs[6] This is repeated for each bit of dff_inst23_out. Ok, so I have two other registers that feed this net, but they are not connected! I understand that this is happening because the output of these other registers are the same as the inst23 one, but hey, I've got more registers like that, all over the place! So why is this happening to this particular net? I've taken a screenshot of the design in question, and my troublesome net is the blue stub: http://www.battlefield.no/bilder/inst23.gif Any suggestions would be appreaciated! Sincerely -"Panic"Article: 62187
I haven't seen many job postings here, so, I have to ask. Is it OK to post one? Thanks, -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 62188
You should open a webcase with Xilinx if nothing else helps. I just burned several days trying to figure out why Modelsim wouldn't simulate a chunk-o-code. It complained about "glbl.v". To make a long and painful story short, there's a bug in the current release of MXE. This will be fixed in the ISE 6.2i release. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "Simone Winkler" <simone.winkler@gmx.at> wrote in message news:1066686601.590067@news.liwest.at... > Hello! > > I'm performing a VHDL design for a Xilinx Spartan2-FPGA that implements a > synchronous FIFO. > Actually, at the moment, I'm just using the Application Note Design offered > on the Xilinx Wepage (XAPP175). > So far, so good, I've got a testbench to be run in Modelsim. > But every time it tells me the following things: > > ___________________________________________________________________ > > # Reading D:/Programme/Modeltech_xe/tcl/vsim/pref.tcl > # do fifo_c_tb.fdo > # ** Warning: (vlib-34) Library already exists at "work". > # Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002 > # -- Loading package standard > # -- Loading package std_logic_1164 > # -- Loading package std_logic_arith > # -- Loading package std_logic_unsigned > # -- Compiling entity fifoctlr_cc > # Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002 > # -- Loading package standard > # -- Compiling architecture fifoctlr_cc_hdl of fifoctlr_cc > # -- Loading package std_logic_1164 > # -- Loading package std_logic_arith > # -- Loading package std_logic_unsigned > # -- Loading entity fifoctlr_cc > # WARNING[1]: fifo_c.vhd(97): No default binding for component: "bufgp". (No > entity named "bufgp" was found) > # WARNING[1]: fifo_c.vhd(110): No default binding for component: > "ramb4_s8_s8". (No entity named "ramb4_s8_s8" was found) > # Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002 > # -- Loading package standard > # -- Loading package std_logic_1164 > # -- Loading package std_logic_arith > # -- Loading package std_logic_unsigned > # -- Compiling entity fifo_c_tb > # Model Technology ModelSim XE II vcom 5.6e Compiler 2002.10 Oct 22 2002 > # -- Loading package standard > # -- Compiling architecture test of fifo_c_tb > # -- Loading package std_logic_1164 > # -- Loading package std_logic_arith > # -- Loading package std_logic_unsigned > # -- Loading entity fifo_c_tb > # -- Loading entity fifoctlr_cc > # WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port write_data_in > # WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this > component instantiation will result in an elaboration error. > # WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port read_data_out > # WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this > component instantiation will result in an elaboration error. > # WARNING[1]: fifo_c_tb.vhd(46): Types do not match for port fifocount_out > # WARNING[1]: fifo_c_tb.vhd(46): A use of this default binding for this > component instantiation will result in an elaboration error. > # vsim -L xilinxcorelib -lib work -t 1ps testbench > # ** Warning: A ModelSim starter license was detected and will be used, even > though you have installed ModelSim XE. You should obtain an XE license in > order to access ModelSim XE's full capabilities.# Loading > D:/Programme/Modeltech_xe/win32xoem/../std.standard > # ** Error: (vsim-3173) Entity 'work.testbench' has no architecture. > # Error loading design > # Error: Error loading design > # Pausing macro execution > # MACRO ./fifo_c_tb.fdo PAUSED at line 9 > __________________________________________________________________ > > > The two components RAMB4_S1 and BUFGP should be in a library - so i don't > understand why it's not found. > I don't understand, why the ports don't match - they are really the same > type (most of them std_ulogic(_vector)). > And at the end, why does it say "Entity 'work.testbench' has no > architecture" ? > My idea is that i need a configuration file. But i'm doing everything out of > Xilinx ISE Webpack, there i never need a configuration file, or do i? I'm > quite out of understanding at the moment...:(. > > > > My TestBench-Code (at least parts of it) was: > ___________________________________________ > > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_unsigned.conv_integer; > use ieee.std_logic_arith.conv_std_logic_vector; > > entity fifo_c_tb is > end fifo_c_tb; > > architecture test of fifo_c_tb is > component fifoctlr_cc > port (clock_in: in std_ulogic; > read_enable_in: in std_ulogic; > write_enable_in: in std_ulogic; > write_data_in: in std_ulogic_vector(15 downto 0); > fifo_gsr_in: in std_ulogic; > read_data_out: out std_ulogic_vector(15 downto 0); > full_out: out std_ulogic; > empty_out: out std_ulogic; > fifocount_out: out std_ulogic_vector(7 downto 0)); > end component; > > constant clk_delay_c : time := 50 ns; > > signal clock_s: std_ulogic; > signal read_enable_s: std_ulogic; > signal write_enable_s: std_ulogic; > signal write_data_s: std_ulogic_vector(15 downto 0); > signal fifo_gsr_s: std_ulogic; > signal read_data_s: std_ulogic_vector(15 downto 0); > signal full_s: std_ulogic; > signal empty_s: std_ulogic; > signal fifocount_s: std_ulogic_vector(7 downto 0); > > begin > u1: fifoctlr_cc > port map( > clock_in => clock_s, > read_enable_in => read_enable_s, > write_enable_in => write_enable_s, > write_data_in => write_data_s, > fifo_gsr_in => fifo_gsr_s, > read_data_out => read_data_s, > full_out => full_s, > empty_out => empty_s, > fifocount_out => fifocount_s > ); > > > -- *** Test Bench - User Defined Section *** > clock: process > begin > [...] > __________________________________________________ > > please help me!! > > Thank you, Simone > > ------------------------------------------------------------------- > Simone Winkler > Mechatronik-Studentin / Universität Linz > simone.winkler@students.jku.at > ICQ: 20212150 >Article: 62189
Hi to all,
I'm writing a short program using verilog at the moment ,and I
encountered 4 errors of the same kind (a net is not a legal value in
this context). I've been tring to edit the program but i still get the
same errors... I need help urgently .Can someone explain the errors?
Thanks a lot!
Below is my program and I have indicated where the 4 errors (a net is
not a legal value in this context) the compiler pointed to.
--------------------------------------------------------------------------------
`timescale 1ns/1ps
module encoder(eingated, clr, clk, inhibit, keydet, eout);
input [3:0]eingated;
input clr, clk, inhibit ,keydet;
output [3:0]eout;
reg [3:0]eout;
parameter idle = 1'b0, keypressed = 1'b1;
reg [1:0] cur_state, next_state;
always @(posedge clk or negedge clr)
begin
if(clr==0)
cur_state = idle;
else
cur_state = next_state;
end
always@(cur_state or eingated)
begin
case(cur_state)
idle : if (eingated == 4'b1110 || eingated == 4'b1101 ||
eingated == 4'b1011 || eingated == 4'b0111)
begin
keydet = 1'b1; <-----a net is not a legal value...
inhibit = 1'b1; <-----a net is not a legal value...
next_state = keypressed;
end
else
begin
keydet = 1'b0; <-----a net is not a legal value...
inhibit = 1'b0; <-----a net is not a legal value...
next_state = idle;
end
keypressed : if(eingated==4'b1110)
begin
eout=2'b00;
end
else if(eingated==4'b1101)
begin
eout=2'b01;
end
else if(eingated==4'b1011)
begin
eout=2'b10;
end
else if(eingated==4'b0111)
begin
eout=2'b11;
end
else
begin
next_state = idle;
end
endcase
end
endmodule
Article: 62190
A new progress:
I re-implement the design without LOC constraints(in translate
stage) using my one-slice macro,after 12 hours of routing,the par
failed and there's always
1556 unrouted,and the ISE "keeps" the relative position of the slice
in the CLB.It seems to be the reason for the routing error,but how can
I resolve it?Is there some hidden option when I create the macro?
And sorry for my mistake in the last post:
.......
> First I generate a macro with only one LUT,but placer failed with a
~~~~~~~
one slice
......
> Secondly I generate another macro fully using the whole slice(but my
~~~~~~
CLB
Have a nice day!
Article: 62191This looks like a bug. Panic, please email me the qar file for your project, and I will take a look. In the meantime try replacing the lpm_ff with a dff primitive and see if it makes a difference. - Subroto Datta Altera Corp. "Panic" <panic74@hotmail.com> wrote in message news:cUglb.518$mf2.4092@news4.e.nsc.no... > After searching for the source of an error for quite a long time, I've > decided that I need some help, and once again you guys drew the shortest > straw ;-) > > I have a 8 bit DFF with output q[7..0]. This feeds the net > dff_inst23_out[7..0]. (The reason this net is given this name, was to see if > the error actually was located where I thought it was, since the original > error pointed to some temp net.) Both the DFF output and the net is 8 bits > wide, and still I get this error message: > > Error: Net dff_inst23_out[6] cannot be assigned more than one value > Error: Net is fed by std_8bit_dff0:inst8|lpm_ff:lpm_ff_component|dffs[6] > Error: Net is fed by std_8bit_dff0:inst9|lpm_ff:lpm_ff_component|dffs[6] > Error: Net is fed by std_8bit_dff0:inst23|lpm_ff:lpm_ff_component|dffs[6] > > This is repeated for each bit of dff_inst23_out. > > Ok, so I have two other registers that feed this net, but they are not > connected! I understand that this is happening because the output of these > other registers are the same as the inst23 one, but hey, I've got more > registers like that, all over the place! So why is this happening to this > particular net? > > I've taken a screenshot of the design in question, and my troublesome net is > the blue stub: > http://www.battlefield.no/bilder/inst23.gif > > Any suggestions would be appreaciated! > Sincerely > -"Panic" > > >Article: 62192
inside an always process you can assign only reg not nets. An input is a net unless you declare it also as a reg. Review Verilog 101 :) Tullio On 21 Oct 2003, Bose wrote: > Hi to all, > > I'm writing a short program using verilog at the moment ,and I > encountered 4 errors of the same kind (a net is not a legal value in > this context). I've been tring to edit the program but i still get the > same errors... I need help urgently .Can someone explain the errors? > > Thanks a lot! > > Below is my program and I have indicated where the 4 errors (a net is > not a legal value in this context) the compiler pointed to. > > > -------------------------------------------------------------------------------- > > > `timescale 1ns/1ps > > module encoder(eingated, clr, clk, inhibit, keydet, eout); > > input [3:0]eingated; > input clr, clk, inhibit ,keydet; > output [3:0]eout; > reg [3:0]eout; > > parameter idle = 1'b0, keypressed = 1'b1; > reg [1:0] cur_state, next_state; > > > always @(posedge clk or negedge clr) > begin > if(clr==0) > cur_state = idle; > else > cur_state = next_state; > end > > > > always@(cur_state or eingated) > begin > case(cur_state) > idle : if (eingated == 4'b1110 || eingated == 4'b1101 || > eingated == 4'b1011 || eingated == 4'b0111) > begin > keydet = 1'b1; <-----a net is not a legal value... > inhibit = 1'b1; <-----a net is not a legal value... > next_state = keypressed; > end > else > begin > keydet = 1'b0; <-----a net is not a legal value... > inhibit = 1'b0; <-----a net is not a legal value... > next_state = idle; > end > > > keypressed : if(eingated==4'b1110) > begin > eout=2'b00; > end > else if(eingated==4'b1101) > begin > eout=2'b01; > end > else if(eingated==4'b1011) > begin > eout=2'b10; > end > else if(eingated==4'b0111) > begin > eout=2'b11; > end > else > begin > next_state = idle; > end > > endcase > end > endmodule > -- Tullio Grassi ====================================== Univ. of Maryland-Dept. of Physics | College Park, MD 20742 - US | Tel +1 301 405 5970 | Fax +1 301 699 9195 | ======================================Article: 62193
"Panic" <panic74@hotmail.com> wrote in message news:<cUglb.518$mf2.4092@news4.e.nsc.no>... > After searching for the source of an error for quite a long time, I've > decided that I need some help, and once again you guys drew the shortest > straw ;-) > > I have a 8 bit DFF with output q[7..0]. This feeds the net > dff_inst23_out[7..0]. (The reason this net is given this name, was to see if > the error actually was located where I thought it was, since the original > error pointed to some temp net.) Both the DFF output and the net is 8 bits > wide, and still I get this error message: > > Error: Net dff_inst23_out[6] cannot be assigned more than one value > Error: Net is fed by std_8bit_dff0:inst8|lpm_ff:lpm_ff_component|dffs[6] > Error: Net is fed by std_8bit_dff0:inst9|lpm_ff:lpm_ff_component|dffs[6] > Error: Net is fed by std_8bit_dff0:inst23|lpm_ff:lpm_ff_component|dffs[6] > > This is repeated for each bit of dff_inst23_out. > > Ok, so I have two other registers that feed this net, but they are not > connected! I understand that this is happening because the output of these > other registers are the same as the inst23 one, but hey, I've got more > registers like that, all over the place! So why is this happening to this > particular net? > > I've taken a screenshot of the design in question, and my troublesome net is > the blue stub: > http://www.battlefield.no/bilder/inst23.gif > > Any suggestions would be appreaciated! > Sincerely > -"Panic" Sounds like you shorted several outputs together. Given the error messages, you should check if your instantiations of std_8bit_dff0:inst8|lpm_ff:lpm_ff_component|dffs[6] etc. are correct. It looks like you assigned several of them the same output node. Vaughn AlteraArticle: 62194
> > "Panic" <panic74@hotmail.com> wrote in message > news:8rEkb.32199$os2.467326@news2.e.nsc.no... > > > > I'm a student working an a Altera EPXA1F484C1 FPGA, and I'm having some > > problems I hope someone can help me with. > > > > 2. I get stuck-at errors...and I have no idea why. I get this warning: > > "Warning: No clock transition on AESRoundSP- > > 2:inst|lpm_dff0:inst5|lpm_ff:lpm_ff_component|dffs[127] register" > > And this continues for all 128 flipflops. But they are clocked by the > > "master clock". I have not created a clock signal, but the clock is named > > clk, and then Quartus should assume that the signal is a clock, right? > > Anyway, Quartus compiles my design without errors, but the summary tells > me > > that I'm not using any LEs or any memory bits... > > > > The AESRoundSP-2 is a building block in a larger design, but does not > > compile "on its own" because it uses too many pins and memory bits. Can > this > > cause the weird error in (2)? > > The only times I've seen the warning above is when Quartus detects that your clock signal will never toggle (i.e. it is either a logic '0' or '1' all the time, due to the logic feeding it reducing to that). This almost always indicates a design error. So I think this is more basic than making clock settings etc. to tell Quartus your clock frequency requirements and such -- Quartus has detected that this circuit is almost certainly not what you want. You should examine your HDL to see exactly what logic is generating this clock. Vaughn AlteraArticle: 62195
"Mancini Stephane" <nospam@nospam.nospam> wrote in message news:<pan.2003.10.14.12.17.57.905341@nospam.nospam>... > Thanks Mike, > That's we are already doing. The problem is that I want to synthesize the > sopc project before and just perform the P&R during the course to speed up the whole > process. So I have to synthesize the sopc project with leonardo or > Quartus. In this later case, is it possible to just perform a synthesis > with Quartus ? > What can I do ? > thanks a lot. > > Stéphane > Hi Mancini, Yes, it is possible. Go to Assignments->Settings->Synthesis and check "Save a node-level netlist to a persistant source file (Verilog Quartus Mapping File)". Give this file some name in the box (say sopc_base.vqm). Just run synthesis next (Processing->Start->Run Analysis & Synthesis). You will now have sopc.vqm in your project directory. It is a flattened, synthesized netlist in structural Verilog, where everything is made up of Altera primitives that exist on the device. Next, create a new project where you include this sopc_base.vqm file. You can now write peripherals in verilog or VHDL (or whatever) and hook them up to your base SoPC logic. Quartus synthesis will be run when you compile your total design, but since the sopc_base part of the design is already synthesized, there will be little to do there exist hook it into the circuit, so it will save some CPU time. I doubt it takes very long to synthesize a base SoPC system in any case, so this may not be worth the effort, but it is an option. VaughnArticle: 62196
On 21 Oct 2003 07:23:25 -0700, jiz_king@hotmail.com (Carl) wrote: >Hi, > >My apologies if this is not the most appropriate group for this query. > >I am starting to have great difficulty sourcing some 74 logic parts >from my design in SMD (at least in small volumes). As I now have the >chance to make a new PCB revision I am wondeing if I couldn't do away >with the logic all together and use a PLD (CPLD). > >So for those who know the learning curve well, > >I have never used PLD's before, but have used PIC's (asm) and was >wondering if it is realistic for me to grasp enough of PLD design (not >necessarily VHDL) to implement some simple logic functions within a >month or so? > >Or is this likely to take far longer? > >I was playing with the Altera Quartus II software and it seems that by >using existing blocks this could be fairly straight forward. > >What do you think and what would be a good entry level device? > >Any comments would be greatly appreciated.! What all the other guys said, plus this: Be *very* careful about gated clocks and async resets. It's common for an SSI or MSI TTL design to do all sorts of funny tricks with async resets or clock gating. A direct translation of your TTL design to CPLD isn't guaranteed to work. Failures are usually due to glitches or races. Don't be discouraged though, as it should be easy to do some minor amount of redesign to avoid those problems. Read up on synchronous design techniques. Regards, Allan.Article: 62197
Carl wrote:
>
> Hi,
>
> My apologies if this is not the most appropriate group for this query.
>
> I am starting to have great difficulty sourcing some 74 logic parts
> from my design in SMD (at least in small volumes). As I now have the
> chance to make a new PCB revision I am wondeing if I couldn't do away
> with the logic all together and use a PLD (CPLD).
>
> So for those who know the learning curve well,
>
> I have never used PLD's before, but have used PIC's (asm) and was
> wondering if it is realistic for me to grasp enough of PLD design (not
> necessarily VHDL) to implement some simple logic functions within a
> month or so?
>
> Or is this likely to take far longer?
>
> I was playing with the Altera Quartus II software and it seems that by
> using existing blocks this could be fairly straight forward.
>
> What do you think and what would be a good entry level device?
>
> Any comments would be greatly appreciated.!
First you need to collect your logic, and tabulate the
IP's, OP's, and buried nodes, required.
Good devices could start at SPLD 16V8 (8i8o), 22V10 (12i10o),
or 32 Macrocell CPLD (32io,2-4ip) on up.
Next look at the Power supply budget : Voltage and mA/uA,
and if can you tolerate multiple Vccs.
For simple logic you do NOT have to use Verilog or VHDL.
Most tool flows include simpler Boolean Eqn entry options
in the form or ABEL or CUPL.
Here you enter eqns like
CS4 = !(A12 & A13 & A14 & !A15);
Qs1.d = Shift & Qs0
# Load & Ds0;
This is very similar to the Assembler you are used to.
The tools can also run command-line, just like the ASM.
-jg
Article: 62198Carl wrote: >Hi, > >My apologies if this is not the most appropriate group for this query. > >I am starting to have great difficulty sourcing some 74 logic parts >from my design in SMD (at least in small volumes). As I now have the >chance to make a new PCB revision I am wondeing if I couldn't do away >with the logic all together and use a PLD (CPLD). > >So for those who know the learning curve well, > >I have never used PLD's before, but have used PIC's (asm) and was >wondering if it is realistic for me to grasp enough of PLD design (not >necessarily VHDL) to implement some simple logic functions within a >month or so? > >Or is this likely to take far longer? > >I was playing with the Altera Quartus II software and it seems that by >using existing blocks this could be fairly straight forward. > >What do you think and what would be a good entry level device? > >Any comments would be greatly appreciated.! > > You can use Xilinx's XC9500 series for smaller designs, they hold the program in flash memory inside the chip, and are pretty cheap. For larger designs, there is the Spartan series, a bit more expensive, and it needs an external serial PROM and a reset circuit. These are both 5 V parts, although most of the new stuff from Xilinx is 3.3 V and less. They have a schematic entry package in their ISE software. Oh, yeah, all their software dropped support of all 5 V parts about 3 years ago. So, you have to get ISE 4.1 or 4.2 to get support for those 5 V parts. Their schematic entry package is not to my liking, after suffering with it for some time, I have figured out how to do schematics in Protel 99 and send VHDL over to the Xilinx tools. If you have a favorite schematic package and it can export VHDL, you can probably do the same. The Xilinx libraries have most of the standard 7400 series parts as standard items. You can mix and match 74xx and basic gate and FF components from the library in your schematic. With a CPLD (XC9500 series) you can put dozens of 74xx parts into one $10 chip. With the FPGA (XCS - Spartan series) you can put several large boards worth of SSI-MSI chips onto one $15 - 30 chip. I have a product that has 4 24-bit pulse rate generators with controllable pulse width and setup and hold times, 4 24-bit quadrature encoder counters plus a bunch of digital I/O pins and an IEEE-1284 bus controller, all in one $30 Spartan XCS30 chip. There is a 74HC14 used mostly as a reset generator, and a 74HC4538 one shot used as a watchdog timer, otherwise, the Spartan has all the logic on the entire board. Jon
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