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Ken, Easy, just use the power estimator spreadsheet. http://www.xilinx.com/ise/power_tools/spreadsheet_pt.htm Austin PS: generally speaking, if the dynamic power is dominating, CV^2F=P implies that the power will double if F is doubled, but there are lots of other fatcors you need to pay attention to, such as what the IOs are doing (did the data rate double there as well?), etc. Ken wrote: > Hi folks, > > Been checking the archives for an answer to this one without much luck... > > What does doubling the clock rate of a design on an FPGA do to the power > consumption (in general - I am just looking for a rule of thumb here..)? > > If you need some assumptions to answer: > > Assume: > critical path is a 25-bit carry chain in an adder. > a highly pipelined design occupying most of the device. > > Not sure what else would be useful assumptions-wise - please feel free to > add your own! :-) > > Also, if I double my clock rate and reduce my hardware by half due to > sharing hardware over 2 clock cycles, obviously the reduced hardware will > reduce power consumotion and the increased clock will increase power > consumption, question is, which is the overriding factor? (the clock I > guess?). > > Again, just looking for a rule of thumb. > > Cheers, > > KenArticle: 61226
To inject a fresh idea into this long thread: One dual-ported BlockRAM, configured as a 4K x 4 ROM can obviously take 12 inputs and generate 4 binary encoded outputs, but it can do this twice, once per port. (Both ports look at the same code converter simultaneously). So one BlockRAM takes 24 inputs and generates two sets of 4 binary outputs which can be combined in one CLB to generate the 5-bit result. Two BlockRAMs can similarily encode 48 inputs, and the final result is available in substantially less than 10 ns. Note that the BlockRAM requires an input clock edge to initiate the conversion. Since Virtex-II devices contain tens and even hundreds of such BlockRAMs, it is highly likely that a few of them are unused, which makes this design not only simple and fast, but also almost zero cost. Peter Alfke, Xilinx Applications. =============================== Jake Janovetz wrote: > > Hi Aart- > > In the Xilinx FPGAs, a LUT RAM block can conveniently be 32x1. You > could use three of these, with five identical inputs to provide a > look-up sum of five bits. Then, take the results of these sums (five > inputs at a time) into an adder tree. For example, if A, B, C, D, E, > F are the sets of 5-bits of a 30-bit input, then you'd sum A+B, C+D, > E+F. Two more levels and you'd have a complete sum. I'm not sure if > this is what the group decided on as the most efficient method, but > it's the first one that comes to mind. You could use BRAMs if you'd > like for a larger lookup (10-bits at a time to a 4-bit result if you > use RAMB4_S4_S4, for example). > > Jake > > Aart van Beuzekom <aart@westcontrol.dontspamme.com> wrote in message news:<bl8u9v$1v5$1@news.netpower.no>... > > Hi, > > > > Can anybody tell me a practical way (in VHDL) to count the number of > > ones in a bit pattern? Counting should be done with combinatorial logic, > > which means that a for-to loop cannot be used here (but being quite new > > to FPGA and VHDL, I'm not even sure). The number of bits to be counted > > is about 30, so a single look-up table is not the solution, using only a > > Spartan II. > > > > Any suggestions? Purpose is amongst others pattern matching, where I > > count how many bits differ from the expected result. > > > > Thanks, > > > > AartArticle: 61227
Hi. In a SpartanIIe design I use an input signal as clock, although it does not enter the chip through a global clock pin. To do this, I instantiate an IBUF and a BUFG. Now I want to put a timing constraint on the BUFG output. In the ISE5 timing constraints editor, the clock appears under a different name, whenever I change the design. It's called _n0063 or _n0067 etc. Can I specify a name for the clock net somewhere in the VHDL code? Here's the code I use (PBUS_CLK is the input signal, ICLK is the clock): C1: IBUF port map (I => PBUS_CLK, O => PBUS_CLK_IBUF); C2: BUFG port map (I => not(PBUS_CLK_IBUF), O => ICLK); Kind regards, MarcArticle: 61228
> Hello, > > I spent some time experimenting with the Parallel Slave Mode > configuration procedure available in the Spartan-IIE to > configure an XC2S300E over the parallel port; the motivation > was to use the same interface for configuration and, after > startup, for external communication during normal operation. > > I'm using a CPLD to generate the necessary signals from the > IEEE1284 compatibility mode handshake and this is working just > fine, but I'd like to follow up on the behavior I observed. > > If I understand the datasheet correctly, the FPGA expects the > user to load the complete bitstream before deasserting the /CS > and /WRITE signals, and then procedes to the CRC check. From > what I've seen, this doesn't appear to be the case; the device > drives DONE high after only 234448 of the documented 234456 > configuration bytes are loaded; I'm assuming that I simply did > not understand the datasheet correctly with respect to /WRITE > and /CS, but why does the configuration complete early? I've done the (fairly) same thing but without a CPLD: the download is slower since you can't use EPP mode but that's not a big deal for me. I'm experiencing the same: the bit stream is longer than the FPGA actually wants. Also, make sure you read the APP notes on 5V compatibility of the Spartant2E series and that the clock you use is clean enough. That can cause a lot of programming problems. Regards, Andras TantosArticle: 61229
Hey Sneaker,
I can't give you the code to our host side driver (I don't own it) but I can
tell you its a slight modification to a sample driver in the MicroSoft
Device Driver Kit.
From the original header. (So you could search)
Copyright (c) 1995 Microsoft Corporation
Module Name:
I82930.c
Abstract:
USB device driver for Intel 82930 USB test board
Environment:
kernel mode only
So if you have access to or can get the MS DDK then I think it has all you
need.
Our setup was pretty much done for us, but you need to compile this driver
with a unique filename and maybe your USB ID (not sure about this) and then
you setup a .inf file that says your device uses this driver file.
(executable renamed to SneakersUSB.SYS or such)
"your device" is the name that should show up even without a driver when you
plug it into a Windows box. I assume the USB core has some default. (.inf
file basically maps this name to which driver to load. May be able to use
someone elses driver by creating a .inf for all I know)
Surprised they gave away the core, but not the driver they tested it with.
Good Luck!
Ken
"SneakerNet" <nospam@nospam.org> wrote in message
news:_x7eb.163252$JA5.4024668@news.xtra.co.nz...
> Hello again Paul ;o)
>>>>
>>>> Big quote deleted by Archive Owner
>>>>
Article: 61230> > I've done the (fairly) same thing but without a CPLD: the download > is slower since you can't use EPP mode but that's not a big deal > for me. I'm experiencing the same: the bit stream is longer than > the FPGA actually wants. Also, make sure you read the APP notes on > 5V compatibility of the Spartant2E series and that the clock you > use is clean enough. That can cause a lot of programming problems. > The original plan was to just use some of the control lines to drive /PROGRAM, CCLK, /CS and /WRITE, as well as status lines to monitor /INIT and DONE, likely the cheapest solution; I was also just going to fiddle the parallel port signals manually to get data to and from the device after configuration. I changed my mind after doing some reading on IEEE1284 and the modes it offers; EPP is simple and hosts implement it in hardware, making it a good choice. The idea then was to use compatibility mode writes to configure the device with a CPLD to coordinate the handshake(s); with the configuration done, I was going to let the CPLD "disappear" from the status lines, allowing the FPGA to take over. This works fine, with the exception that the configuration completes early. Since the CPLD seems to fit enough logic for an IEEE1284 compliant peripheral, I'll probably move all parallel port handling there for good, though. At first, things didn't work quite right since DONE was going high before I expected it; as described, it did so before I finished the bitstream download, before I got a chance to deassert /CS and /WRITE and, lastly, before the FPGA finished its startup sequence. Because of this, the last two CCLK transitions were missing. While it was frustrating for a little while, it motivated me to check the clocks and relevant signals for noise, but they were/are all fine. In terms of 5V tolerance and dealing with the parallel port itself, I decided to play safe, a 19bit IEEE1284 bus interface takes care of the details; its peripheral side operates on 3.3V. Thanks,Article: 61231
Martin Euredjian wrote: > I know about the various algorithms to draw lines, circles, etc. All of > these pretty much rely on painting onto a frame buffer that is later used > to scan out to a CRT. > Use the function of the shape. > Does anyone know of any algorithms to draw primitives that work without > the > intermediate frame buffer step. In other words, the algorithm's input > would be the current x,y pixel being painted on the screen and the desired > shape's > parameters. Horizontal and vertical lines (and rectangles), of course, > are > easy. But, how do you do curves or diagonal lines? > For a circle: (x - x0)^2 + (y - y0)^2 = r^2 Test for equality (or close to equality) for each pixel position (x,y) Circle center = (x0, y0). Circle radius = r. Lines: kx*x + ky*y = y0 In addition you vould need some limiter. kx*x + ky*y = y0 when 20<x<52 I have not checked the functions, but they should be close enough. /RogerL -- Roger Larsson Skellefteå SwedenArticle: 61232
Hello,
I am just now learning VHDL and am wondering how I work write code to use
one single 8bit in/out pins, which is mapped to 4 internal 8bit registers,
which can either be read or written too. It of course would has a 2 bit
address select. I know how to do the entity declaration, I'm not quite sure
how to do the arch process. Here is what I am thinking, please tell me if I
am doing this wrong.
Note also that this is just an example on not my actual project.
entity myMemory is
port (Clk : in std_logic;
DataIo :inout std_logic_vector (7 downto 0) Bus :=(others=>'Z');
OutEn : in std_logic_vector; --Enables the output buffers.
Write : in std_logic; --Write to memory " Active low"
Read : in std_logic; --Read from memory "Active low"
Addr : in std_logic_vector (1 downto 0));
end myMemory;
architecture Behavioral of myMemory is
signal Reg0 : std_logic_vector (7 downto 0);
signal Reg1 : std_logic_vector (7 downto 0);
signal Reg2 : std_logic_vector (7 downto 0);
signal Reg3 : std_logic_vector (7 downto 0);
begin
process(Clk) begin
if(Clk'event and Clk='1') then
case Addr is
when "00"=>
if(Read='0' and Write='1' and 'OutEn='1') then
DataIo<=Reg0;
elsif (Read='1' and Write='0' and OutEn='X') then
Reg0<=DataIo;
else DataIo<=(others=>'Z');
when "01"=>
if(Read='0' and Write='1' and 'OutEn='1') then
DataIo<=Reg1;
elsif (Read='1' and Write='0' and OutEn='X') then
Reg1<=DataIo;
else DataIo<=(others=>'Z');
when "10"=>
if(Read='0' and Write='1' and 'OutEn='1') then
DataIo<=Reg2;
elsif (Read='1' and Write='0' and OutEn='X') then
Reg2<=DataIo;
else DataIo<=(others=>'Z');
when "11"=>
if(Read='0' and Write='1' and 'OutEn='1') then
DataIo<=Reg3;
elsif (Read='1' and Write='0' and OutEn='X') then
Reg3<=DataIo;
else DataIo<=(others=>'Z');
when others =>
if(OutEn='0' then DataIo<=(others=>'Z');
end if;
end case;
end if;
end process;
end Behavioral;
Article: 61233Stephen Williams wrote: > Petter Gustad wrote: > >> "Martin Euredjian" <0_0_0_0_@pacbell.net> writes: >> >>> Is there a way to have more than one computer work on compiling a >>> design? >> >> The Solaris version of par (Xilinx place and route tool) can do >> multiple iterations on multiple hosts (using the -m option to par). > > Hey, the Linux versionhas that too. Interesting. I didn't think this worked yet. It's pretty easy to do this with scripts, so we did not schedule the feature for 6.1i. Let us know how you got it to work. Steve > I can use that to make an extra process on the local machine in order > to put a dual processor > to use? >Article: 61234
"Colin Jackson" <jacksoncolin@fake_yahoo.com> wrote in message
news:R06dneVoUbFL4uSiU-KYhA@comcast.com...
>
> "SneakerNet" <nospam@nospam.org> wrote in message
> news:HI2eb.162954$JA5.4020112@news.xtra.co.nz...
> > Hi Guys
> >
> > I know someone of you have helped me in my replies regarding USB
> > Implementation before.
> > I downloaded the USB Core (referred to as the Japanese version). The
> beauty
> > of this core is that no hardware is required. Just need to connect the
D+
> > and D- of the USB cable to pins of the FPGA.
> >
> > The facts..
> > I changed the code around so that it has a altera pll running and
> producing
> > a 48Mhz clock for the usb.
> > I connected some of the output pins to the leds to see what's going on.
> > I uploaded the program and connected the usb cable to the pins and to
the
> PC
> > (and added some circuitry like 3 extra resistors).
> > and Behold, the program on the FPGA actually does something. I know it's
> > working because when i connect/disconnect the usb calbe, the lights on
> fpga
> > change their pattern for a small amount of time..
> >
> > However I can't test the actual communication. The reason being, when I
> > connect the usb cable to the PC, the PC recognizes a new USB device is
> > attached (as win2k shows in the system try all the usb devices.),
however
> is
> > unrcognised as VALID drivers are not installed.
> >
> > What I need is some help/tips on how i can install a driver for this
> > product. The fpga has been configured so that it recognises a vendor ID
of
> > C91 and product ID of 2001. I have tried playing around with .inf files,
> but
> > win2k rejects all of them and uses the standard c:\winnt\inf\usb.inf
file.
> >
> > I'm so close to getting this thing to work.
> >
> > Pls help/advice
> > Regards
> >
> >
> Try http://www.jungo.com/products.html#driver_tools
> They have a demo version that looks really easy to make drivers.
> I played with it but not on a real device.
> Let us know if it works!
>
> -Colin
>
>
Hello Colin
LOL, while doing a search on google, I had come across that site.
Installed it, then deleted it :P..
Guess looks like I'll have to try again. I hope I can crack it.
Thanks Colin
Regards
Article: 61235I've just released a new version of HDLmaker. I've added support for the Xilinx 6.1 tools including project generation and I've added a comment feature to the .pin files which allows you to add comments to ports. Example, In the .pin file IB_STAT_RX_LINK_ELP type = out,comment = "End of Link Packet"; Generated Verilog //-- End of Link Packet output IB_STAT_RX_LINK_ELP; HDLmaker generates hierarchical Verilog and VHDL as well as scripts and constraint files for all of the better know simulators, synthesis tools and FPGA tool sets. You can get HDLmaker from, http://www.polybus.com/hdlmaker/users_guide/ It's free with a BSD style license.Article: 61236
Hi Ken Thanks for the important tip. I'll give that a shot. (so there is no way u can send me driver? all i need is a driver with vendor id = 0c91 and product id = 2001). Anyway like u mentioned, very big pity that the guys didn't include drivers and they gave their whole vhdl code free. Pity! Hope god has mercy on my soul while i'm doing usb driver.. LOL Thanks Ken Kind Regards "Ken Land" <kland1@neuralog1.com> wrote in message news:vnjklpqkrag6e8@news.supernews.com... > Hey Sneaker, >>>> >>>> Big quote deleted by Archive Owner >>>>Article: 61237
LOL Thanks Paul All help appreciated at this stage.. "Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:pX7eb.162860$Lnr1.3280@news01.bloor.is.net.cable.rogers.com... > Hi, >>>> >>>> Big quote deleted by Archive Owner >>>>Article: 61238
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F751429.40DB59C3@yahoo.com>... > Andy Peters wrote: > > > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F7257C6.91BECAD0@yahoo.com>... > > > > > That is the part I am not clear about. These traces are all individual > > > circuits. If you have the luxury of a lot of open board space to route > > > straight lines here and there, then sure, you can make each one very > > > similar. On a small, tight board it will be very difficult to make them > > > that similar. If the signal is critical enough to require a simulation, > > > then I expect I would need to simulate each of them. > > > > The traces may not actually be individual circuits! While Austin (and > > others, including myself) advocate SI simulations to show the effects > > of terminations on line ringing and what not, what can _really_ bite > > you in the ass is crosstalk. In one particular case, there was an > > issue with crosstalk from a data bus affecting a nearby reset line. > > When a simulation was finally run, the problem was obvious. > > > > So, yeah, I'd say that not bothering to simulate these lines because > > they weren't clocks and because "the signals can bounce around for a > > couple of ns" was a bad idea. > > Ringing is not the cause of crosstalk. Crosstalk is coupling of the > primary wavefront coupling to adjacent traces due to proximity over > excessively long lengths. No amount of simulation will correct a problem > if you don't understand what is going on. I did not say that "ringing is the cause of crosstalk." I said that another SI issue that you ought to be concerned about is crosstalk. I then went on to say that, because of crosstalk, we saw that the badness on the data lines was being coupled to a reset line. And, yes, simulation showed us exactly what was going on. I'm sorry if I wasn't clear. > But you are making assumptions about the circuits I am building. The > original issue was the fact that the Spartan 3 chips are sensitive to > even short term overvoltage due to ringing. Like I have said, I have > never seen this in any data sheet until now. All the chips I have > worked with either have specifically indicated that there would be no > problem of damage due to small, short term transitions outside the rated > voltage spec, or this was stated when the manufacturer was contacted. > The Spartan 3 chips are the first I have heard of this being > specifically contraindicated. Like I said -- consider that Xilinx are erring on the side of caution. And, as Austin points out, one can minimize the possibility of this sort of potential damage by performing the appropriate SI simulations, and adjusting the layout as needed. > He is not the only one who is frustrated. My questions were not about > the issues of designing for SI, but about the sensitivity of the Spartan > 3 chips to damage from ringing. His replys are not responsive to my > comments and questions. Again, his comments are that as chip geometries shrink and rise times get faster, one needs to consider SI issues everywhere. Erring on the side of caution. > I can do a few simple calculations to get worst > case numbers for ringing on a 6" trace. I don't need to use expensive > software that does the same calulation with a few extra variables thrown > in that simply fine tune the calcs. You know your needs better than the rest of us; I can't argue with that. > The other reason that I can't simulate the signals up front is because > the Spartan 3 in this design will be driving signals to multiple > daughter boards that are not designed or even planned yet. Obviously > this will have to be dealt with at the design level when the time > comes. Ah, but you can, if you can obtain a model of the connector you're going to use, and assume that you've got a perfect load on the other side. Better than nothing. You can also deviate from "perfection" and see the effects on your board. --aArticle: 61239
I have been away, but was glad to see people are starting to talk about this possible issue with the S3. > The confusion is (to many) that the question is what does the reflection back to the driver do to the > driver, right? This is a fairly obscure distinction, so I would not expect every one of the 200+ hotline > CAEs to get it perfectly right on the first try. > > Did you submit multiple cases? Or call some folks you know? (IE how did you get multiple answers...) It > would help if you worked this thru the hotline, as they need to learn from their mistakes, and improve > their service sometimes. If you are talking about it here, then we are not closing the loop! Well, like I had stated early on, I had spent about two months working the channels at Xilinx trying to get an answer, starting with the person who made the original comment about it being a problem. I never opened a case with the hotline. I have never found them to be useful and it seems their only goal to it to close as many calls as possible, not help the customers. That's for a different topic. > > Well, if the PMOS is ON, then it is really hard for a reflection to drive the output pin to a voltage that > is higher than the specification. Conversely, if the NMOS is ON, then it is really hard for the reflection > to drive the output pin below ground. > > Look at the IBIS simulation at the output pin to see what the voltage excursions are, an be sure they stay > within the specifications sheet and user's guide. Well, not like Mr. Pease, I have always been a big user of simulation as one tool. Certainly, not the last tool and I don't see it replacing the VNA any time soon as a way to get the 'real' picture of what is going on. But the question I always have when some one throws out the simulation card is how good is your model. When Xilinx released the IBIS models for the S3, how much data was it based upon? Have they continued to update the model as parts are being tested? How much do you trust it? > > If you have a specific waveform, you may email it to me directly, and I will get the "final word" from the > designers and technology groups. Do I have a specific waveform, no. I am asking a general question about the S3. Just how sensitive it really is and what precautions do I need to take to make it work. Because each layout is different, the loading can be anything if you consider all of the failure modes.Article: 61240
symon_brewer@hotmail.com (Symon) writes: > ... So, I can't stick > 5V PECL into my 3.3V Virtex-E differential input, it's outside the > common mode range. So, I could AC couple it with a couple of caps > after the PECL driver's emitter resistors. How about just a DC-coupled resistive divider to ground, doubling as the emitter load? A (3.3/5) ratio would put the common-mode voltage about right, and 3 dB of attenuation is no big deal.Article: 61241
Hi,there I received my avnet VirtexII Pro development kit(XC2VP7) this month. I know it is somehow different from the evaluation board(stronger in general). But I guess I can try to give some premitive views. And right now, since I am still a newbie on this board, the information I gave may not be accurate. 1.In the flash memory of the development board, there already stores a linux core there, which will run on the spartan(the pci bridge) when power up. you can use a serial cable to connect with a host pc and use a hypertermianl program to watch. The flash also installed some other applications which will help you monitor the board like avmon. I can't provide further details right now since my work are usually done in windows 2.I already installed the board into a pci slot and used it. So the answer to the second question is yes.( although it took me more than a week to contact avnet engieer and figure out some tedious technique detail. The documment coming with the board is not that helpful.) There is a tool called PCIutility which can help you to debug the board and download the file. However all these work are finished under the 3rd party driver (jungo or to say windriver). So as far as I know, probably only on windows. 3.I havn't test the memory speed yet. So I can't tell whether there is a bottleneck yet.( you need to write your own project both hd and sw to contol all types of the memory) 4. with the pciutility I mentioned above, yes you can program the FPGA through PCI. 5. you can connect it to a host pc not simply a monitor. Hope it is helpful to you. P.S. Do you know whether it is possible to feed input to the FPGA on board from a PC and read output to the PC?? If so, how?? I need to implement an algorithm and now stuck here. I mean write your own API instead of using some tools. "Mancini Stephane" <nospam@nospam.nospam> wrote in message news:<pan.2003.09.26.07.58.52.284871@nospam.nospam>... > Hi, > I would like to know if anybody here has tested the avnet VirtexII Pro > evaluation board with XC2VP7 or XC2VP20 chip (board ref : ADS-XLX-V2PRO-DEVP7-5 > and ADS-XLX-V2PRO-DEVP20-5) > http://www.silica.com/eval_kits/ads-20030515.html > > > I would like to know if : > - it's possible to install an OS like linux or uclinux on this board ? > What about the linux port from http://penguinppc.org/dev/kernel.shtml > What about ucOSII (http://www.micrium.com) > > - Is there any bottleneck to access the SRAM from the chip through the PCI bridge ? > > By the way has anybody tried to put it in a PC and communicate with it? > The card seems to be delivered with a windows interface. What's this ? > How to use it with a PC running linux ? > > > Is it possible to programm the FPGA trough PCI (once in a PC) or is it mandatory to use > the standard way ? > > - is there a way to connect it a display - LCD or video ? > > > More generally, about VirtexII Pro, it seems that all the coreconnect bus > stuff has to be synthesized using FPGA ressources ? At the opposite, it > seems the Excalibur Arm solution proposes a basic microsystem (a CPU with > some peripherals) which preserves FPGA ressources. > Am I right ? > What's the complexity of the coreconnect bus ? How many room is left > in XC2VP7 or XC2VP20 chips for, say, a single PLB bus, a SDRAM/RAM > controller, UART, timer and interface to > PCI (to the PC or PMC-daughter cards)? > Do I have to use two PLB bus if I use the XC2VP20 chip (with 2 PowerPC) ? > I understand that it doesn't consume multipliers but what about > combinatorial/sequencing logic for the bus stuff ? > > > Thanks a lot for your future responses > > StéphaneArticle: 61242
That was some good reading! Thanks to everyone who had input on this subject. I would like to know more details about how the S3 I/O models are being maintained. I can't seem to get Xilinx to keep up with their timing models in their own tools. If the S3 really is that sensitive, I would not use simulation as the last word. While we have more "sensitive" boards tested at the supplier's, even this may no longer be "good enough" to validate the PCB. And if they hit 10% on their test pads I think they are doing good. My big fear is that while we have been doing 1G digital designs for several years using ECL without any problems (well), as we migrate to putting these designs into faster FPGAs that we may loose reliablity. The best thing we could hope for is for the FPGA designers to make a quantum jump to 100GHz+ internal routing and take all the fun out of the layout. And while your at it, there are some other features I would like packed in there as well. Maybe I will live to be that old, but I don't think so. Thanks again for putting some light on this.Article: 61243
lecroy, See below, Austin lecroy wrote: > I have been away, but was glad to see people are starting to talk > about this possible issue with the S3. > > > The confusion is (to many) that the question is what does the reflection back to the driver do to the driver, > right? This is a fairly obscure distinction, so I would not expect every one of the 200+ hotline CAEs to get > it perfectly right on the first try. > > Did you submit multiple cases? Or call some folks you know? (IE how did you get multiple answers...) It > would help if you worked this thru the hotline, as they need to learn from their mistakes, and improve their > service sometimes. If you are talking about it here, then we are not closing the loop! > > Well, like I had stated early on, I had spent about two months working > the channels at Xilinx trying to get an answer, starting with the > person who made the original comment about it being a problem. I > never opened a case with the hotline. I have never found them to be > useful and it seems their only goal to it to close as many calls as > possible, not help the customers. That's for a different topic. Unfortunate. If you don't ask, you don't get an answer. Try it. If it doesn't work, let us (me) know. You must prefer doing everything the hardest way possible. We also do not appreciate the slamming of our hotline staff. Theya re all dedicated to helping our customers succeed, as that is what sells parts, not "closed cases." If a hotline engineer can not resolve the problem within a fixed amount of time, it is escalated. Once escalated, it then goes up the ladder til it reaches someone who can resolve the issue. > > > > Well, if the PMOS is ON, then it is really hard for a reflection to drive the output pin to a voltage that is > higher than the specification. Conversely, if the NMOS is ON, then it is really hard for the reflection to > drive the output pin below ground. > > > > Look at the IBIS simulation at the output pin to see what the voltage excursions are, an be sure they stay > within the specifications sheet and user's guide. > > Well, not like Mr. Pease, I have always been a big user of simulation > as one tool. Certainly, not the last tool and I don't see it > replacing the VNA any time soon as a way to get the 'real' picture of > what is going on. You can not even probe, nor observe the points that are in question here. The VNA is a frequency domain tool, and unless you convert the S parameters into their transient form (done by some advanced simulators) you will learn nothing at all (even after simulating or trying to measure). "Real" only applies to this one part. What about the next one? > But the question I always have when some one throws > out the simulation card is how good is your model. When Xilinx > released the IBIS models for the S3, how much data was it based upon? The test chips from UMC that had all of the transistors on them and characterized. > > Have they continued to update the model as parts are being tested? Yes. That is the procedure. > > How much do you trust it? Better than the real silicon, which may be from any yielding corner, and not be representative of the worst possible cases (fast, cold corner, with hi-voltages for example. You can not buy a fast corner IO transistor version of the chip, you have to simulate it. Folks who submit their chips to a third party for IBIS models do their customers a terrible dis-service, as the model is only as good as the sample of chips sent, which is ususally terrible. We must support our devices through accurate and useful models. Fact of life (and business). The models are an IOU: that is what we tell you you will get. > > > > > If you have a specific waveform, you may email it to me directly, and I will get the "final word" from the > designers and technology groups. > > Do I have a specific waveform, no. I am asking a general question > about the S3. General Answer: simulate it, and make sure it meets yourt needs, and our operating and abs max specifications. > Just how sensitive it really is and what precautions do > I need to take to make it work. Already stated, if you exceed the abs max specs, you may find that more than .1% of the parts do not last the intended operating life. Good Signal Engineering practices will result in a robust design that will meet all goals, and all specs and last a long, long time. A car manufacturer was once asked, "what is the safest way to use your vehicle?" The answer: "don't use it at all. Just park it, and walk away." So ask questions that can be answered, like sending me a plot of what you think might be a problem. Or logging a call to the hotline (and then letting us know if you are not completely satisfied with the answer). > Because each layout is different, the > loading can be anything if you consider all of the failure modes. Failure mode is simple: the stress on the pmos output device when the IO pin is used as an input shall not exceed that stated in the abs max spec (4.05V for example on Virtex II Pro and Spartan 3, +3.75V abs max Vcco, and -0.3V abs max Vio on the io pin). If this stress is exceeded, it will eventually cause the IO to become leaky (ie > 10uA IOB leakage current spec will be violated). This increase in leakage may, or may not affect your system. Simulate and you will see......Article: 61244
"Colin Jackson" <jacksoncolin@fake_yahoo.com> wrote in message news:R06dneVoUbFL4uSiU-KYhA@comcast.com... > > "SneakerNet" <nospam@nospam.org> wrote in message > news:HI2eb.162954$JA5.4020112@news.xtra.co.nz... > > Hi Guys > > > > I know someone of you have helped me in my replies regarding USB > > Implementation before. > > I downloaded the USB Core (referred to as the Japanese version). The > beauty > > of this core is that no hardware is required. Just need to connect the D+ > > and D- of the USB cable to pins of the FPGA. > > > > The facts.. > > I changed the code around so that it has a altera pll running and > producing > > a 48Mhz clock for the usb. > > I connected some of the output pins to the leds to see what's going on. > > I uploaded the program and connected the usb cable to the pins and to the > PC > > (and added some circuitry like 3 extra resistors). > > and Behold, the program on the FPGA actually does something. I know it's > > working because when i connect/disconnect the usb calbe, the lights on > fpga > > change their pattern for a small amount of time.. > > > > However I can't test the actual communication. The reason being, when I > > connect the usb cable to the PC, the PC recognizes a new USB device is > > attached (as win2k shows in the system try all the usb devices.), however > is > > unrcognised as VALID drivers are not installed. > > > > What I need is some help/tips on how i can install a driver for this > > product. The fpga has been configured so that it recognises a vendor ID of > > C91 and product ID of 2001. I have tried playing around with .inf files, > but > > win2k rejects all of them and uses the standard c:\winnt\inf\usb.inf file. > > > > I'm so close to getting this thing to work. > > > > Pls help/advice > > Regards > > > > > Try http://www.jungo.com/products.html#driver_tools > They have a demo version that looks really easy to make drivers. > I played with it but not on a real device. > Let us know if it works! > > -Colin > > Colin Have u got a crack for this program? Since I installed it about a month back, then uninstalled it, and now it won't work.. Sigh CheersArticle: 61245
Austin Lesea wrote: > Failure mode is simple: the stress on the pmos output device when > the IO pin is used as an input shall not exceed that stated in the > abs max spec (4.05V for example on Virtex II Pro and Spartan 3, > +3.75V abs max Vcco, and -0.3V abs max Vio on the io pin). If this > stress is exceeded, it will eventually cause the IO to become leaky > (ie > 10uA IOB leakage current spec will be violated). This increase > in leakage may, or may not affect your system. If you go outside the limits with Vio and are current limited to 10uA will there be a problem? How about 100uA? 1mA? Please excuse my ignorance on this stuff....Article: 61246
Greetings,
I need to detect runs. I want to look at 65 bits and show when there are 9
consecutive 1s or 0s from the byte boundaries resulting in 8 values per
clock. This should be comfortably done in two logic levels (I need clean
logic delays).
The idea is simple but the implementation is tough. I'm working with
Verilog in Synplify, targeting a Xilinx Spartan-3. I have to resort to
design violence to get the results that I believe are "best."
Any thoughts on how to do this "better?" (the following code likes fixed
fonts)
- John_H
=====================================
module testRun ( input clk
, input [64:0] bytePlus1
, output reg [ 7:0] runByte /* synthesis xc_props = "INIT=R"
*/
); // INIT included to force register as FD primitive - bleah
reg [23:0] runBits; // I wanted the syn_keep on this combinatorial "reg"
wire [23:0] runBits_ /* synthesis syn_keep = 1 */ = runBits; // - bleah
reg [ 7:0] runByte_;
integer i,j,k;
always @(*)
begin
runBits = -24'h1;
runByte_ = -8'h1;
k = 0; // overlapping aaa aaaa
for( i=0; i<64; i=i+j ) // consecutive aaaa
begin // bit regions 876543210
for( j=0; (i%8+j<8) && (j<3); j=j+1 )
runBits[k] = runBits[k] & (bytePlus1[i+j]==bytePlus1[i+j+1]);
runByte_[i/8] = runByte_[i/8] & runBits_[k];
k = k + 1;
end
end
always @(posedge clk) runByte = runByte_;
endmodule
Article: 61247Javier, Do you use NT? Xilinx dropped NT support with ISE version 5.1i, but it still ran. With 6.1i Impact won't even start up. Neither will the Core Generator. YMMV. Marc Javier Fernández Baldomero wrote: > Hi all: > > I was using a Digilent 2DE + DIO1 (Spartan2E) with the > Free ISE WebPack 5.2, with no problems. > > I have just downloaded the new WebPack 6.1 and everything > runs well until iMPACT tries to automatically configure > the BoundaryScan chain. The Digilent D2E is programmed > thru a parallel cable connected to LPT1: and worked OK > under WebPack 5.2 > > Comparing 5.2 with 6.1, we have found that 5.2 said > --------------------------------------------------- > Connecting to cable (Parallel Port - LPT1). > Checking cable driver. > Driver windrvr.sys version = 5.0.5.1. > LPT base address = 0378h. > ... > --------------------------------------------------- > > but 6.1 says > --------------------------------------------------- > LPT base address = 0B78h. > --------------------------------------------------- > > and finally says "communications with the cable > could not be stablished. Check cable and power" > > Has anybody found the same problem and any workaround? > > Thanks in advance > > -javierArticle: 61248
So, when you plugin your device, does Windows say New Device Found, etc.? Giving you a chance to install a driver? If so, does it tell you the name of the device? I"ve never built our driver, but I'll give it the ol' 15 minute try. Ken "SneakerNet" <nospam@nospam.org> wrote in message news:G8meb.164007$JA5.4045853@news.xtra.co.nz... > Hi Ken >>>> >>>> Big quote deleted by Archive Owner >>>>Article: 61249
Hi Again Colin Don't worry about the crack, I found it. Did u have this problem, WinDriver finds the device, and I assign the Vendor ID and the Product ID and windriver generates a inf file, and then tries to install the driver. However at this stage, win2k takes over and reports that c:\winnt\inf\usb.inf is a closer match and windows ends up using that driver instead of my custom generated driver and I can't do anything about it. Cheers. "Colin Jackson" <jacksoncolin@fake_yahoo.com> wrote in message news:R06dneVoUbFL4uSiU-KYhA@comcast.com... > > "SneakerNet" <nospam@nospam.org> wrote in message > news:HI2eb.162954$JA5.4020112@news.xtra.co.nz... > > Hi Guys > > > > I know someone of you have helped me in my replies regarding USB > > Implementation before. > > I downloaded the USB Core (referred to as the Japanese version). The > beauty > > of this core is that no hardware is required. Just need to connect the D+ > > and D- of the USB cable to pins of the FPGA. > > > > The facts.. > > I changed the code around so that it has a altera pll running and > producing > > a 48Mhz clock for the usb. > > I connected some of the output pins to the leds to see what's going on. > > I uploaded the program and connected the usb cable to the pins and to the > PC > > (and added some circuitry like 3 extra resistors). > > and Behold, the program on the FPGA actually does something. I know it's > > working because when i connect/disconnect the usb calbe, the lights on > fpga > > change their pattern for a small amount of time.. > > > > However I can't test the actual communication. The reason being, when I > > connect the usb cable to the PC, the PC recognizes a new USB device is > > attached (as win2k shows in the system try all the usb devices.), however > is > > unrcognised as VALID drivers are not installed. > > > > What I need is some help/tips on how i can install a driver for this > > product. The fpga has been configured so that it recognises a vendor ID of > > C91 and product ID of 2001. I have tried playing around with .inf files, > but > > win2k rejects all of them and uses the standard c:\winnt\inf\usb.inf file. > > > > I'm so close to getting this thing to work. > > > > Pls help/advice > > Regards > > > > > Try http://www.jungo.com/products.html#driver_tools > They have a demo version that looks really easy to make drivers. > I played with it but not on a real device. > Let us know if it works! > > -Colin > >
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