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I am working on a consumer product development. We have decided to use the Spartan 3 FPGA. But to keep the cost down, we want to use a very small PROM on the board. How could I program the Spartan 3 FPGA with a tiny PROM? I was thinking of creating a compressed bitstream for the small processor interface logic that will take hardly 5 to 10% of the slices(that should lead to good compression ratios so as to fit in a tiny PROM) and then use this logic to self configure the new bitstream file from the processor interface and the FPGA having an external interface to talk to itself using selectMAP port (since Spartan 3 does not have any ICAP module). But I have many questions: 1. First of all, does Spartan 3 at all support self/dynamic reconfiguation as my microprocessor interface inside the FPGA has to keep working to configure the FPGA? So Spartan3 partial reconfiguration should not affect my functionality. 2. I know there is a option called compressed bitstream. Is it possible to use compressed bitstream from the PROM at the powerup? I did not notice any decompression engine in the spart3 documentation. I need to use the compressed bitstream at the startup because I want to use the small PROM, but the partial reconfiguraton requires that very first configuration should be of full bit stream. So I need to have a tiny bitstream that can be loaded in the PROM, and used by the Spartan3 for the first time configuration. Thank you ~Naveen "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:<XFb9b.2983$n22.624510994@twister1.starband.net>... > ICAP, or the Internal Configuration Access Port, is not supported in > Spartan-3 FPGAs. Glimpses of the ICAP interface appear in various tools, > either because it was too difficult to remove this function from the > software, or the software mistakenly assumed that Spartan-3 had ICAP. > > Dynamic reconfiguration is still supported in Spartan-3 via the external > SelectMAP interface or JTAG, just not through the ICAP interface. The > decision to remove it was due to silicon resource requirements and testing > cost. Although dynamic reconfiguration is a powerful concept, few > consumer-oriented applications use it. > > The following is some background on partial reconfiguration in Spartan-3 and > the ICAP primitive. > > Does Spartan-3 Support Partial Reconfiguration? > > Virtex/E, Virtex-II, and Virtex-II Pro devices - generically called Virtex > throughout this article - support a feature called partial reconfiguration. > Using this feature, an application can modify a portion of the bitstream > programming inside an FPGA to change the FPGA's functionality. Spartan-3 > FPGAs support some of these same capabilities, but with limitations compared > to Virtex. > > Via today's design software, partial bitstream changes must be performed on > an entire IOB, CLB, or Block RAM column basis in both Virtex and Spartan-3 > FPGAs. For example, to change a single bit within a single LUT, the > application must update all the CLBs in the affected column. Any unmodified > CLBs within the column are overwritten with the same configuration data. > > Perhaps the most important difference between Virtex and Spartan-3 FPGAs is > how the FPGA logic behaves during the reconfiguration process. In the Virtex > devices, any unmodified bits in the affected column continue to operate > normally. Consequently, if bits within a column are unchanged, then the > surrounding logic continues to function normally. In Spartan-3 FPGAs, > however, even unmodified bits in a column are temporarily reset during the > reconfiguration process, which greatly complicates using partial > reconfiguration. Partial reconfiguration works in Spartan-3 FPGAs, just with > extra complications. > > A column consists of multiple configuration frames. Physically, the Virtex > hardware supports configuration changes at the frame level, but software > currently just supports changes at the column level. The Spartan-3 hardware > supports bitstream changes at the column level only. > > The application can partially reconfigure the FPGA via a variety of means, > including the parallel SelectMap configuration interface and the FPGA's JTAG > port. Virtex-II and Virtex-II Pro families also support another means called > the ICAP (Internal Configuration Access Port). The ICAP interface is similar > to the parallel SelectMAP interface, but is available from within the FPGA. > Although the Spartan-3 architecture is based on the Virtex-II and Virtex-II > Pro architectures, the Spartan-3 family does not support the ICAP interface. > > Table 1 summarizes how partial reconfiguration compares between families. > > Table 1. Partial Reconfiguration Support in Virtex-II vs. Spartan-3. > > > Software supports... > Virtex: Column-based reconfiguration > Spartan-3: Column-based reconfiguration > > Hardware supports... > Virtex: Frame-based reconfiguration > Spartan-3: Column-based reconfiguration > > Unmodified logic remains active during reconfiguration? > Virtex: Yes > Spartan-3: No > > Reconfigure via SelectMAP? > Virtex: Yes > Spartan-3: Yes > > Reconfigure via JTAG? > Virtex: Yes > Spartan-3: Yes > > Reconfigure via ICAP? > Virtex: Virtex-II and Virtex-II Pro only > Spartan-3: No > > > > > For more information on partial reconfiguration, visit the following web > links: > > Partial Reconfigurability Frequently Asked Questions > http://www.xilinx.com/ise/advanced/partial_reconf_faq.htm > > XAPP151: Virtex Series Configuration Architecture User Guide > http://support.xilinx.com/xapp/xapp151.pdf > > XAPP290: Two Flows for Partial Reconfiguration: Module Based or Small Bit > Manipulations > > http://www.xilinx.com/xapp/xapp290.pdf > > --------------------------------- > Steven K. Knapp > Applications Manager, Xilinx Inc. > Spartan-3/II/IIE FPGAs > http://www.xilinx.com/spartan3 > --------------------------------- > Spartan-3: Make it Your ASIC > > "Antti Lukats" <antti@case2000.com> wrote in message > news:80a3aea5.0309131115.164ea0ee@posting.google.com... > > Xilinx what is correct in ISE 5.1 schematics editor the ICAP primitive > > doesnt show, but if looking at XDL output then ICAP primitive does > > exist ?! > > > > I was very disappointed to see that Spartan 3 doesnt have ICAP > > (i.e. self reconfig) but it seems it is there? > > > > anttiArticle: 60651
I am working on a consumer product development. We have decided to use the Spartan 3 FPGA. But to keep the cost down, we want to use a very small PROM on the board. How could I program the Spartan 3 FPGA with a tiny PROM? I was thinking of creating a compressed bitstream for the small processor interface logic that will take hardly 5 to 10% of the slices(that should lead to good compression ratios so as to fit in a tiny PROM) and then use this logic to self configure the new bitstream file from the processor interface and the FPGA having an external interface to talk to itself using selectMAP port (since Spartan 3 does not have any ICAP module). But I have many questions: 1. First of all, does Spartan 3 at all support self/dynamic reconfiguation as my microprocessor interface inside the FPGA has to keep working to configure the FPGA? So Spartan3 partial reconfiguration should not affect my functionality. 2. I know there is a option called compressed bitstream. Is it possible to use compressed bitstream from the PROM at the powerup? I did not notice any decompression engine in the spart3 documentation. I need to use the compressed bitstream at the startup because I want to use the small PROM, but the partial reconfiguraton requires that very first configuration should be of full bit stream. So I need to have a tiny bitstream that can be loaded in the PROM, and used by the Spartan3 for the first time configuration. Thank you ~NaveenArticle: 60652
Hi,
I have been trying to learn the "generic" statement in VHDL and as a
result I have made the generic binary decoder (below) in VHDL. Note that
both the encoded input A and decoded output Y are of type unsigned. Also
in the "for" loop I have used "to_integer"
Then I have a top level file that instantiates this decoder with SizeIn =
8 and SizeOut = 256.
The design is synthesized and implemented without any errors on XST.
However when I try to simulate the design using ModelSim I get warnings
and errors such as -
# WARNING[1]: Types do not match for port A
# WARNING[1]: A use of this default binding for this component
instantiation will result in an elaboration error.
# WARNING[1]: Types do not match for port Y
# WARNING[1]: A use of this default binding for this component
instantiation will result in an elaboration error.
** Failure: Default binding had errors for entity "top_architecture" on
the component declaration of line 55. See the compiler messages.
I think this is because of type "unsigned" When I remove "unsigned" and
make it type "std_logic_vector," I cannot use the "to_integer" in
the "for" loop. XST does not synthesize and gives the following error
ERROR: HDLParsers:808 - to_integer cannot have such operands in this
context
Any ideas? I am absolutely frustrated with VHDL right now :D. Maybe the
best way would be to make it std_logic_vector and somehow get the same
functionality of "to_integer" by some other function.
Thanks in advance for your help.
-Yash
*************************************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity generic_decoder is
generic (SizeIn, SizeOut: integer);
port ( Clock, Rst : in std_logic;
A : in unsigned(SizeIn - 1 downto 0);
Y : out unsigned(SizeOut - 1 downto 0));
end generic_decoder;
architecture arch_generic_decoder of generic_decoder is
begin
process (Clock, Rst)
begin
if (Rst = '1') then
Y <= (others => '0');
elsif (Clock'event and Clock = '1') then
for N in 0 to SizeOut - 1 loop
if (to_integer(A) = N) then
Y(N) <= '1';
else
Y(N) <= '0';
end if;
end loop;
end if;
end process;
end arch_generic_decoder;
Article: 60653Followup to: <95776079.0309180911.4f8937ae@posting.google.com> By author: kempaj@yahoo.com (Jesse Kempa) In newsgroup: comp.arch.fpga > > You might check the dev. board schematic (installed into the Nios kit > "documents/nios_stratix_1s10" folder) page 32, which goes over the > RS232 connections between FPGA & DB9 connectors. We use the same > circuit for both serial ports on the board. The distinction of > communication vs. debug serial port is just for software purposes > (where does STDOUT go...). For hardware development & interfacing > purposes, both ports are functionally equivalent. > At least on the Cyclone board, this is not true -- only the most basic pins are wired up on the DEBUG port (highly unfortunate IMO.) -hpa -- <hpa@transmeta.com> at work, <hpa@zytor.com> in private! If you send me mail in HTML format I will assume it's spam. "Unix gives you enough rope to shoot yourself in the foot." Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64Article: 60654
You'll get more consistent results by instantiating the LUTs and initializing
them with a function. The synth tools results are vendor and version
specific, especially when it so happens that one of the address inputs for a
particular bit winds up being a don't care (worst case is when the LUT bit is
constant). Also, I prefer to use SRL16's for this, as that way it is
reloadable without recompiling and reconfiguring the FPGA.
Bob wrote:
> Hello again,
>
> I have an array of 16 10 bit coefficients, and I would like to store
> these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and
> Altera devices by selecting various options say on Quartus, or can I
> switch on any synthesis switches or do I have to change my VHDL. Any ideas
> as always is greatly appreciated.
>
> Thanks
> Bob
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60655
You need to decide what your requirements are:
size, precision, accuracy, number of clocks per sample and clock rate.
You aren't going to get all of them at once, however if you can compromise on
accuracy, a normalize -> look up -> denormalize might be the best approach.
Theron Hicks wrote:
> Hello,
> I have a project in mind where I would like to caclculate the resistance
> of a sensor. Because of the remainder of the circuit configuration, this
> must be done using a voltage divider. If I implement this in a spartan3,
> what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a
> shift and subtract, but I would prefer something a little faster. Any
> suggestions? (I know I could go to a fast DSP but again, I would prefer to
> stick with what I am most comfortable with (FPGAs). My intent is to use the
> smallest spartan3 if posible.
> Thanks,
> Theron Hicks
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60656Hello all, I am unable to find the HDL bencher in the processes window Xilinx ISE5.1 version. All I see is the Verilog Test Fixture Module helping me to create the .tf testbench file. I used HDL bencher with 4.1 version as its free and integrated in it. Does this mean that its no longer free (or) maybe I have not installed the software properly. Thnx for your assistance, VikramArticle: 60657
Hello Jake/Ray I appreciate two esteemed people like yourselves offering me your advice. I would rather infer than instantiate (if that doesn't sound too rude). The reason being that I have all the VHDL written and working in simulation and I don't have the time to redesign it. Right now I am hoping for quick fixes to cut down on flop utilization. The following shows a few lines on my code.... subtype data_value is std_logic_vector(15 downto 0); type Array_A is array (0 to 15) of data_value; signal data_a: Array_A; Are there any directives that I could enclose the signals data_a in to infer LUTs or SRLs instead of having to do instantiations..say for synplify ? I would really like to avoid instantiation if I can. Thanks Bob jakespambox@yahoo.com (Jake Janovetz) wrote in message news:<d6ad3144.0309180658.4ada7252@posting.google.com>... > Sure- they could be conveniently stored in an SRL or RAM > implementation of the LUT. > > Most explicitly, you'll want to instantiate the RAMs or SRLs in VHDL. > You can infer this sort of thing but I don't really see why you would. > Simulation models can handle the simulation stuff and instantiation > makes the synthesizers job all that much easier. It's generally > easier to read the code, too. > > Jake > > > stenasc@yahoo.com (Bob) wrote in message news:<20540d3a.0309180006.ac62b3d@posting.google.com>... > > Hello again, > > > > I have an array of 16 10 bit coefficients, and I would like to store > > these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and > > Altera devices by selecting various options say on Quartus, or can I > > switch on any synthesis switches or do I have to change my VHDL. Any ideas > > as always is greatly appreciated. > > > > Thanks > > BobArticle: 60658
stevenarchibald@hotmail.com (Steven Archibald) wrote in message news:<bcc42006.0309180623.2d1b1bf2@posting.google.com>... > I'm trying to find a board consisting of a Virtex II or Virtex II Pro > and a fair amount of on-board memory i.e. 256 or 512MB. The board has > to be capable of outputting the data read from memory through some > kind of port at very high bandwidth - GBytes/s. It also has to be > attached to either a PCI interface or preferably a VMEbus. Does anyone > know of any single boards, or boards that could be doubled up that > would be capable of doing this? The DN6000k10S will do what you require. See: http://www.dinigroup.com/products/6000k10s.html Mike Dini mdini@dinigroup.comArticle: 60659
Sorry Ray,
I meant to give a little more detail than I ended up with. The number of
clock cycles per divide is not critical. I cannot accept any pipeline delay, but
I am willing to wait a few clock cycles before I get a final result. I basically
need to get a divide-by result as quickly as possible. The inputs are 2 16 bit
numbers and I need a minimum of 14 bits in the result. I would really like to get
to 16 bits if possible. The resultant resistance (the quotient) is subtracted
from the desired resistance. This difference serves as the input to a very fast
PID controller. This controller serves to control the temperature of a hot-wire
sensor in a research grade hot-wire anemometer. Based on that, the time delay
between requesting a quotient and the time when that quotient is valid needs to be
minimum. The 16 bit A/D currently has a latency of 460ns. The remainder of the
PID control loop should take about 30ns. I want the division to be substantially
faster than the sum of those two times if possible. As a maximum, it must be
faster that 500ns. If it were much faster (~100ns) then I could look at faster
A/D converters for an even higher system throughput when desired. I hope this
clarifies things.
Thanks,
Theron
Ray Andraka wrote:
> You need to decide what your requirements are:
> size, precision, accuracy, number of clocks per sample and clock rate.
> You aren't going to get all of them at once, however if you can compromise on
> accuracy, a normalize -> look up -> denormalize might be the best approach.
>
> Theron Hicks wrote:
>
> > Hello,
> > I have a project in mind where I would like to caclculate the resistance
> > of a sensor. Because of the remainder of the circuit configuration, this
> > must be done using a voltage divider. If I implement this in a spartan3,
> > what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a
> > shift and subtract, but I would prefer something a little faster. Any
> > suggestions? (I know I could go to a fast DSP but again, I would prefer to
> > stick with what I am most comfortable with (FPGAs). My intent is to use the
> > smallest spartan3 if posible.
> > Thanks,
> > Theron Hicks
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
Article: 60660Right click in the hierarchy window, select new source, select test bench waveform, enter name, OK (or is it next?), OK, and your running. vikram wrote: > Hello all, > > I am unable to find the HDL bencher in the processes window Xilinx > ISE5.1 version. All I see is the Verilog Test Fixture Module helping > me to create the .tf testbench file. > I used HDL bencher with 4.1 version as its free and integrated in it. > Does this mean that its no longer free (or) maybe I have not installed > the software properly. > > Thnx for your assistance, > VikramArticle: 60661
"Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:<bkcrmn$iah$1@msunews.cl.msu.edu>... > Hello, <in Spartan3> >> what is the fastest I can do a 16bit divide (unsigned) > Thanks, > Theron Hicks Perhaps try table lookup using blockram, followed by Newton-Raphson iteration..see for example: http://citeseer.nj.nec.com/oberman95analysis.html HTH JohnArticle: 60662
Virtex-II has 18 x 18 combinatorial multipliers with a through-delay of <10 ns . I think you can use this in a successive approximation loop with max 14 or 16 cycles. That would mean you can afford 30 ns per cycle. 33 MHz seems like a "piece-of-cake" to me. Peter Alfke "Theron Hicks (Terry)" wrote: > > Sorry Ray, > I meant to give a little more detail than I ended up with. The number of > clock cycles per divide is not critical. I cannot accept any pipeline delay, but > I am willing to wait a few clock cycles before I get a final result. I basically > need to get a divide-by result as quickly as possible. The inputs are 2 16 bit > numbers and I need a minimum of 14 bits in the result. I would really like to get > to 16 bits if possible. The resultant resistance (the quotient) is subtracted > from the desired resistance. This difference serves as the input to a very fast > PID controller. This controller serves to control the temperature of a hot-wire > sensor in a research grade hot-wire anemometer. Based on that, the time delay > between requesting a quotient and the time when that quotient is valid needs to be > minimum. The 16 bit A/D currently has a latency of 460ns. The remainder of the > PID control loop should take about 30ns. I want the division to be substantially > faster than the sum of those two times if possible. As a maximum, it must be > faster that 500ns. If it were much faster (~100ns) then I could look at faster > A/D converters for an even higher system throughput when desired. I hope this > clarifies things. > > Thanks, > Theron > > Ray Andraka wrote: > > > You need to decide what your requirements are: > > size, precision, accuracy, number of clocks per sample and clock rate. > > You aren't going to get all of them at once, however if you can compromise on > > accuracy, a normalize -> look up -> denormalize might be the best approach. > > > > Theron Hicks wrote: > > > > > Hello, > > > I have a project in mind where I would like to caclculate the resistance > > > of a sensor. Because of the remainder of the circuit configuration, this > > > must be done using a voltage divider. If I implement this in a spartan3, > > > what is the fastest I can do a 16bit divide (unsigned) Obviously I can do a > > > shift and subtract, but I would prefer something a little faster. Any > > > suggestions? (I know I could go to a fast DSP but again, I would prefer to > > > stick with what I am most comfortable with (FPGAs). My intent is to use the > > > smallest spartan3 if posible. > > > Thanks, > > > Theron Hicks > > > > -- > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759Article: 60664
I had one question about the Spartan 3 reconfiguration. I want to configure the FPGA from a PROM at the startup, and that will be done in master/slave serial mode so mode pins will have some corresponding settings. Then I want to use the configured FPGA logic to reconfigure itself. In this case since Spartan 3 does not have ICAP module, I will need to use the selectMap interface (of course I will need to bring out signals from the FPGA to connect to selectMap). My question is what happenens to the mode and init pins duing this reconfiguration by selectMap port. Do I just need to write the partial configuration bit file using D, CS, Write pins? or I need to change the mode bits settings too since I will be using the selectMap during reconfiguration and I was using Master/Slave serial mode........or the FPGA understands that it is partial reconfiguration and it does not need any mode input setting..in that case, how it will differentiate JTAG reconfiguration or selectMap reconfiguration. Thank you ~NaveenArticle: 60665
We have bitstream compression option. If it does really provide compression(does not matter whether it is 5% or 10%, it is still savings. Then why not we have it as default option? If I am compressing the bitstream from the Xilinx, does the FPGA automatically understands the compressed bitstream, decompresses it and configures the FPGA? What are the pros and cons? Thank you ~NaveenArticle: 60666
I am very thankful that Xilinx is now supporting Linux directly in ISE6.1. However, out of the box it only directly supports Redhat 7.3 and Redhat 8. Has anyone managed to install it under Redhat 9 and what if anything did you need to do to get it to call the glibc libraries successfully? At the moment when I run ./setup, it fails with an error msssage stating that it cannot find the glibc libraries. I am unsure if I can run multiple versions of the gcc compiler Comments Thanks Garry AllenArticle: 60667
Ray Andraka <ray@andraka.com> wrote in news:3E015446.DA84C8FA@andraka.com: Never divide by a constant... multiply by its reciprocal! -Stan > Unfortunately this algorithm is rather nasty to do in hardware, > requiring a multiply and divide at each iteration. Methods similar to > CORDIC and to hardware division are easier to implement in a hardware > design. > > Kip Ingram wrote: > >> The general approach to rapidly computing logarithms (used by Henry >> Briggs to generate the log tables he published in 1617) is to first >> reduce the problem to the computation of the logarithm of a value >> very near 1. Then use the power series >> >> log (1+x) = x - x^2/2 + x^3/3 - x^4/4 ...... >> >> to get a value of whatever accuracy you need. The "cleverness" is in >> how to creatively move the argument near 1. >> >> A full treatment of this is given in _Dead Reckoning - Calculating >> Without Instruments_ by Ronald Doerfler (ISBN 0-88415-087-9). >> >> Good luck. :-) >> >> Kip Ingram >> >> -- >> Get daily news and analysis from the FPGA market for pennies a day. >> Subscribe to >> The FPGA Roundup today: http://www.KipIngram.com/FPGARoundup.html >> >> -- >> "John" <john.l.smith@titan.com> wrote in message >> news:5b9931fd.0212111542.5d473661@posting.google.com... >> > "Tim Nicolson" <t.nicolson@signal.qinetiq.com> wrote in message >> news:<1037972506.869047@bengal>... >> > [snip] >> > > The ip algorithm requires that I compute logarithms. This can >> > > prove quite a computationally expensive operation, but I only >> > > need accuracy down to around 4/5 significant figures. >> > [snip] >> > > This method is inexpensive but gives limited accuracy. >> > > Operations shown below >> > > >> > > >> > > z = a + b*mant + c*mant^2 + d*mant^3; >> > > >> > > if (e ~= 0) >> > > z = z + exp * C1; >> > > end; >> > > >> > > This requires 6* and 4+. >> > >> > Hi Tim, >> > I don't have anything to add to the existing discussion >> > of logs (sorry), but if you are evaluating polynomials, >> > you should be aware of Horner's rule ( a personal favorite ): >> > >> > a + b*x + c*x^2 + d*x^3 = >> > ( a + x*(b + x*(c + x*d ) ) ) >> > >> > this reduces your 6 mults (??? 7) to 3 (??? 4). >> > >> > [snip] >> > >> > > >> > > Thanks very much for your time. >> > > >> > > Tim >> > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > > >Article: 60668
"Peter Alfke" <peter@xilinx.com> wrote in message news:3F6A547B.D4673C29@xilinx.com... > Virtex-II has 18 x 18 combinatorial multipliers with a through-delay of > <10 ns . > I think you can use this in a successive approximation loop with max 14 > or 16 cycles. That would mean you can afford 30 ns per cycle. 33 MHz > seems like a "piece-of-cake" to me. > Peter Alfke Even more, if I understand the application, it will be reading a slowly varying resistance. Using the previous result as the new approximation, and assuming reasonable rates of change, it should be able to generate a new result each cycle, after the first 16 cycles. -- glenArticle: 60669
stenasc@yahoo.com (Bob) wrote in message news:<20540d3a.0309180006.ac62b3d@posting.google.com>... > Hello again, > > I have an array of 16 10 bit coefficients, and I would like to store > these in LUT on an FPGA instead of Flops. Can I do this in Xilinx and > Altera devices by selecting various options say on Quartus, or can I > switch on any synthesis switches or do I have to change my VHDL. Any ideas > as always is greatly appreciated. > > Thanks > Bob The best match in Stratix for these would be an M512 RAM (configured as 16 bits deep x 10 wide). One RAM will handle them all. Synthesis tools should automatically infer the RAM, and the Quartus fitter (place and route engine) will automatically decide that this best matches an M512 RAM and put it in one. So you shouldn't have to do anything too special. You could also manually instantiate an altsyncram primitive in your HDL, but inferring really is more portable and intuitive. Hope this helps. Vaughn AlteraArticle: 60670
Parallel JTAG cable on a USB-only W2K laptop? I am wondering if anyone has been able to successfully use a Xilinx parallel JTAG cable/adapter with the ISE 5.2i iMPACT software to program EEPROMS (or even a successful boundary scan to see the JTAG chain) with a laptop that only has USB ports. I purchased an ECP mode bi-directional USB to Parallel IEEE 1284 converter cable to accomplish this on my Toshiba 5105 Satellite laptop, that only has 3 USB ports, no printer ports. iMPACT will not recognize the converter as a printer port. These cables don't install as LPT's and don't have, as far as I can tell, an IO hardware address. As I am a student and I can't justify buying a $495 MultiLINX USB-it would be cheaper for me to build another computer that has an LPT port, or get some other type of converter device, I guess. The problem on the Windows 2000 side is that it doesn't add an LPT port with this plug and play USB port converter device. It installs itself as a USB Printing Support, Driver 1999 by Microsoft (not an LPT). My local Xilinx distributor has given me the following advice which doesn't sound good for me since I have no LPT type hardware IO registers located at the address he suggests, or anywhere else (go to my computer, manage, computer management, system information, hardware resources, I/O). >From my rep: /* The workaround is to force the base address in iMPACT, rather than allowing the software to query the BIOS. To force the base address, the following environment variable should be set: set XIL_IMPACT_ENV_LPT_BASE_ADDRESS=xxx Typically 'xyz' will by '378' as that is the standard base address for the parallel port (LPT1) on Windows PCs. The Windows Device Manager should be used to confirm the base address assigned to LPT1. For information on accessing and using Device Manager see the Windows Help menu on your PC. */ Again, I don't have any LPT type device located at any address I can find to put in the 'xyz 'above. I don't think I should put in the address of the Intel 82801CA/CAM USB Host Controller into the LPT_BASE above? I have looked at support.microsoft.com and didn't find out how to accomplish this either. Any experiences appreciated.Article: 60671
I might as well give the Altera view -- 12.5% is a gross overstatement of the relative abilities of a Virtex LC vs. a Stratix LE. Our data suggests that nearly the reverse is true (about a 9% advantage for Stratix). Please see the following whitepaper for our reasoning and data. As you can see from Figure 1, your mileage will vary -- depending on your design, you could see vast density advantages from one architecture or the other. http://www.altera.com/literature/wp/wp_stx_logic_efficiency.pdf If we wanted to, we could start counting our M512 blocks as logic, as they can be used for shift-registers, small memories, and soft multipliers, but we don't bother. Bottom line -- you really need to compile *your* design to both Stratix and Virtex (or whatever families you are interested in) before you will really know what the story is density. Averages don't matter much to you if yours is that design that gets hosed in one architecture or the other! Regards, Paul Leventis Altera Corp. "Peter Alfke" <peter@xilinx.com> wrote in message news:3F69D605.63B715DB@xilinx.com... > Rick, I will not defend the +12,5%, but I can explain it: > > It is the price we all pay for the intense and sometimes ruthless > competition in this market. Without a bloodthirsty competitor "in our > rear-view mirror", we would be gentlemanlike and give you conservative > numbers. But the way it is, our marketing folks think it would throw > away some really (really!) powerful features if they are not somehow > represented in the numbers. Each Xilinx Logic Cell does more than an > Altera LE, there can be no doubt about that. > > This is not an excuse (personally I agree with you), but an explanation. > > Peter Alfke > ========================== > > rickman wrote: > I care about the fact that I have to ignore a > > column of data in a data sheet as marketing hype and use a calculator to > > get the *real* numbers. Clearly the marketing people don't think we can > > add and multiply ourselves. > >Article: 60672
naveen_jain86@hotmail.com (video1) wrote in message news:<b29aaa65.0309181138.1ffed2ad@posting.google.com>... > I am working on a consumer product development. We have decided to use > the Spartan 3 FPGA. But to keep the cost down, we want to use a very > small PROM on the board. How could I program the Spartan 3 FPGA with a > tiny PROM? > > I was thinking of creating a compressed bitstream for the small > processor interface logic that will take hardly 5 to 10% of the > slices(that should lead to good compression ratios so as to fit in a > tiny PROM) and then use this logic to self configure the new bitstream > file from the processor interface and the FPGA having an external > interface to talk to itself using selectMAP port (since Spartan 3 > does not have any ICAP module). read the postings - S3 logic (your tiny cpu) is not active during reconfiguration, at least what I understood what xilinx had to say :( anttiArticle: 60673
>Even more, if I understand the application, it will be reading a slowly >varying resistance. Using the previous result as the new approximation, and >assuming reasonable rates of change, it should be able to generate a new >result each cycle, after the first 16 cycles. It may be even simpler than that. You might be able to avoid the divide and come up with some kludge heuristics, say table lookup on the difference between the current reading and the previous reading and add/sub that the the running answer. Something like that can easily get you lots of bits of output and/or gives you a place to put in a PLL filter. (I'm guessing this is some sort of PLL.) I still don't understand the big picture. It takes two numbers to do a divide, but the description only mentioned one A/D. Where does the other number come from? Which one is on top? [obvious comments about multiply by inverse if you can] -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 60674
naveen_jain86@hotmail.com (video1) wrote in message news:<b29aaa65.0309181723.dcbe3d8@posting.google.com>... Thank you in advance. > We have bitstream compression option. If it does really provide > compression(does not matter whether it is 5% or 10%, it is still > savings. Then why not we have it as default option? If I am > compressing the bitstream from the Xilinx, does the FPGA automatically > understands the compressed bitstream, decompresses it and configures > the FPGA? What are the pros and cons? > > Thank you > ~Naveen
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