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I was referring to conventions established while Bill Gates was still in kindergarten... Peter Alfke ===========================Article: 50751
Hi all, I remember reading somewhere that under the version of embedded linux for the xilinx virtex II-Pro, you could load and unload hardware modules as it ran -much in the same way that you can do with drivers. Is this true? If so could you send me a link where i could read up about it? Cheers, Stephen.Article: 50753
I think you got the P and S backwards. S is for the synchronous set, P is for
the async preset.
Peter Alfke wrote:
> "Christopher R. Carlen" wrote:
>
> > I have discovered that the R input is not in fact an asynchronous reset
> > input, but instead it doesn't do its thing until a clock pulse comes
> > along. This is very strange, but I suppose I simply assumed that R
> > meant something that it doesn't seem to mean.
>
> It is a long-standing practice to use "R" for synchronous Reset, and "C"
> for asynchronous Clear., and "P" for synchronous Preset, and "S" for
> asynchronous Set.
>
> Of course, not everybody abides by these inofficial rules...
>
> You have already the answer to your problem: Use the right library element.
>
> Peter Alfke, Xilinx Applications
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50755Jee wrote: > Hello, > My friend has an ISE project on his PC, now I want to load his > project and on top of that do some minor modification and re-build it, > but when I load it, PROJNAV told some directory path error and I can > only see an empty project. I know that's because my directory structure > is different from his, then I open the .npl file in a text editor, but I > see a lot info which I am not sure I understand correctly. Then is there > any easy way for me to port his project to my area? Is it possible to do > it without his involvement? > > Thanks > I am not very sure your mean when you say "load it". The easiest way I know to build your design based on your friend's is to build your design direct in the origional project (or a renamed one). In this way you just need to creat a new module and declare&instantiate your friend's design as a component. And you can modified your friend's design or add your own design into the new project. It will be a little bit complicated if you already have your own project and you are trying to merge your friend's design with yours. If your friend's design are completely built on VHDL files (i.e., no cores), then you may copy the related vhdl files of your friend's design into your directory, and use them directly as component in your projects. For those projects with some cores in them, I never try that but you 'd better generate those cores by your own for your design. HuaArticle: 50756
Sounds like you need to consider your approach. There are no memory structures I am aware of that add together
inputs from several sources all at once. Depending on your clock rate, you have several options. One may be to
run at a 16x clock, assigning one of the 16 resulting time slices to each processor so that it updates the memory
only when it is it's turn. If your data rate is such tht that cannot be done, then you can accumulate a separate
histogram for each processor (16 memories), then on read read all 16 in parallel adding the partial results from
each to get a composite result. Again, depending on read rate, you may trade off size of the adder tree for clock
cycles. You can also go somewhere between for intermediate clock rates...say 4 processors per memory working on a
4x clock, then read and accumulate the 4 memories for each bin.
alison wrote:
> Peter Alfke <peter@xilinx.com> wrote in message news:<3DFE0CE9.37756DD4@xilinx.com>...
> > alison wrote:
> >
> > > Actually there will be 8 to 16 identical components(simultaneously
> > > data bytes being fed to the components) doing number crunching
> > > and their outputs could be such that they could be writing data to the
> > > same
> > > location in a memory at exactly the same time.
> >
> > Well, let's for a moment forget about the implementation details:
> > What is it you expect as a result after several sources have written different data "simultaneously" into the
> > same location? Last man wins? But who is last ?
> >
> > Peter Alfke
>
> Let me make a clarification, when i say data could be written simultaneosly
> i want data at that location increamented by the value of output data from
> component(s).
> So let say if the memory location FF has a value 5 in it. 13 out
> of 16 components could be trying to increament location FF with their
> particular output. In software you make them wait by using a semaphore.
> What could be a very fast way of doing that in Logic.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50757Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3E00C2F3.31A0@designtools.co.nz>... > Peter Alfke wrote: > > > > Don't expect to do this in an FPGA alone, but -if I remember right - a > > Sigma-Delta A/D converter is ideal for this applications. Others may know > > more or better... > > There is a lot of science in the better S-D ADC's, but a 2.5MHz sample > rate > will push a first order one - that indicates a clock speed of 640MHz. > There are maths schemes to give higher resolutions, but they usually > impact the > step response times. > > FPGAs are inherently noisy, but that need not be inside the Analog Loop > - > tiny logic gates can buffer from a (very) clean Vcc for the integrator > drive. > > > > > Peter Alfke > > ================= > > Bill Sloman wrote: > > > > > This is a dumb "wouldn't it be nice if there were a" question. > > > > > > At the moment we have a fast-ish, relatively low level alaog front end > > > whose amplified output is digitised to 8-bits at 2.5MHz, and > > > accumulated into 16 32-bit wide bins over about 2000 sampling cycles > > > (24-bits would be enough ...). > > > > > > The conversion noise is visible on the analog signal and the "wouldn't > > > it be nice" idea is that if the A/D converter were embedded in an FPGA > > > which also managed the accumulation into on-chip RAM, there would be a > > > whole lot less conversion noise visible at the front end. > > So you don't actually need 2.5MHz x 8 - but are trying to sample over > 2000 cycles to get more 'bits' - correct ? > > Multi-Cycle averaging makes a very important assumption about the > errors, > that they are random, and evenly distributed. > Real ADCs do not always follow classic maths, so large base averages do > not give the expected noise reductions. Use a better ADC... > > That said, the Sigma-Delta ADCs are good for multi cycle maths, because > the integration cap preserves fractional sample info, so you can, for > example, have a faster 8 bit loop running, for good step response, > and a 12/14/16 bit averaging loop, for good static / low slew following. > > > > > > > In the interests of creeping featurism, a 10-bit A/D converter would > > > be interesting, and room for 200 32-bit bins. The 2.5MHz sampling rate > > > seems to be perfectly adequate. > > > > > > I've had a quick look at Lattice's analog FPGA and the analog isn't > > > really fast enough while the digital side looks to be rudimentary - is > > > there anything better out there? > > > > > > The application is a low volume (order of 100 per year) industrial > > > measuring instrument, so ASICs are out of the question, and > > > significant up-front costs would be a real problem. > > > > > > I suspect that what I'm asking for is a cross-breed between a camel > > > and a mantee, but I'd love to be wrong. > > There are Micro Controllers with 16 & 24 bit ADCs, so the art of mixing > Noisy Digital and Analog is getting better, but it is significant that > they come from the very experienced Analog players - Burr Brown, and > Analog Devices. The signal processors with built-in A/D and D/A converters were all aimed at the audio market when I last looked. Something aimed at digital AM radio might be fast enough. Thanks for all the responses - they've saved me from a fairly tedious and time-consuming search. My own impression was that sigma-delta wasn't going to hack it at 2.5MHz, and there seems to be enough support for this opinion for me to skip any serious chasing-up there too. I can't say much about the application, but if I do get the chance to experiment I'd like to see what one of the 14-bit digital radio A/D converters would do - the frequency distribution of the noise is not white, and while the individual 2.5MHz samples are pretty noisy, the noise at the lowest frequency we have to detect - when present - is quite a lot lower, and we might see some advantage of the better linearity of the 14-bit parts. ----- Bill Sloman, NijmegenArticle: 50758
Bill Sloman wrote: > > Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3E00C2F3.31A0@designtools.co.nz>... > > Peter Alfke wrote: > > > > > > Don't expect to do this in an FPGA alone, but -if I remember right - a > > > Sigma-Delta A/D converter is ideal for this applications. Others may know > > > more or better... > > > > There is a lot of science in the better S-D ADC's, but a 2.5MHz sample > > rate > > will push a first order one - that indicates a clock speed of 640MHz. > > There are maths schemes to give higher resolutions, but they usually > > impact the > > step response times. > > > > FPGAs are inherently noisy, but that need not be inside the Analog Loop > > - > > tiny logic gates can buffer from a (very) clean Vcc for the integrator > > drive. > > > > > > > > Peter Alfke > > > ================= > > > Bill Sloman wrote: > > > > > > > This is a dumb "wouldn't it be nice if there were a" question. > > > > > > > > At the moment we have a fast-ish, relatively low level alaog front end > > > > whose amplified output is digitised to 8-bits at 2.5MHz, and > > > > accumulated into 16 32-bit wide bins over about 2000 sampling cycles > > > > (24-bits would be enough ...). > > > > > > > > The conversion noise is visible on the analog signal and the "wouldn't > > > > it be nice" idea is that if the A/D converter were embedded in an FPGA > > > > which also managed the accumulation into on-chip RAM, there would be a > > > > whole lot less conversion noise visible at the front end. > > > > So you don't actually need 2.5MHz x 8 - but are trying to sample over > > 2000 cycles to get more 'bits' - correct ? > > > > Multi-Cycle averaging makes a very important assumption about the > > errors, > > that they are random, and evenly distributed. > > Real ADCs do not always follow classic maths, so large base averages do > > not give the expected noise reductions. Use a better ADC... > > > > That said, the Sigma-Delta ADCs are good for multi cycle maths, because > > the integration cap preserves fractional sample info, so you can, for > > example, have a faster 8 bit loop running, for good step response, > > and a 12/14/16 bit averaging loop, for good static / low slew following. > > > > > > > > > > In the interests of creeping featurism, a 10-bit A/D converter would > > > > be interesting, and room for 200 32-bit bins. The 2.5MHz sampling rate > > > > seems to be perfectly adequate. > > > > > > > > I've had a quick look at Lattice's analog FPGA and the analog isn't > > > > really fast enough while the digital side looks to be rudimentary - is > > > > there anything better out there? > > > > > > > > The application is a low volume (order of 100 per year) industrial > > > > measuring instrument, so ASICs are out of the question, and > > > > significant up-front costs would be a real problem. > > > > > > > > I suspect that what I'm asking for is a cross-breed between a camel > > > > and a mantee, but I'd love to be wrong. > > > > There are Micro Controllers with 16 & 24 bit ADCs, so the art of mixing > > Noisy Digital and Analog is getting better, but it is significant that > > they come from the very experienced Analog players - Burr Brown, and > > Analog Devices. > > The signal processors with built-in A/D and D/A converters were all > aimed at the audio market when I last looked. Something aimed at > digital AM radio might be fast enough. > > Thanks for all the responses - they've saved me from a fairly tedious > and time-consuming search. > > My own impression was that sigma-delta wasn't going to hack it at > 2.5MHz, and there seems to be enough support for this opinion for me > to skip any serious chasing-up there too. > > I can't say much about the application, but if I do get the chance to > experiment I'd like to see what one of the 14-bit digital radio A/D > converters would do - the frequency distribution of the noise is not > white, and while the individual 2.5MHz samples are pretty noisy, the > noise at the lowest frequency we have to detect - when present - is > quite a lot lower, and we might see some advantage of the better > linearity of the 14-bit parts. The most impressive mix of Analog + Digital I've seen is this announcement from Analog Devices : ADSP-21992 160 MIPS, 16-bit ADSP-219x DSP Core 8-channel, 14-bit, 20 MSPS, 48K words of on-chip RAM, Price indication was $22.50/10K -jgArticle: 50759
I'm using a Xilinx Coolrunner CPLD (CMOS I/O's), with a VCC of 3.0 V. In what range would the inputs be considered floating? -JohnArticle: 50760
The duplicated pins are a result of making one table that supports both the PQ208 and the other packages. There are two VCCO pads on the die, both connected to pin P208 in the PQ208 package. In the other packages, those two pads have independent connections (to support multiple VCCO levels in the device) and therefore separate rows have to be shown for each pad (see the pinout tables at http://www.xilinx.com/bvdocs/publications/ds001_4.pdf). You can ignore the second instance of any pin in the table for the PQ208; this is also true of the VQ100, TQ144, and CS144 packages. Leon Heller wrote: > I've been using the Excel pinout spreadsheet for the XC2S200 > (pin_2s200.xls) from the Xilinx web site to build a PCB part and noticed > that some pins are duplicated for the PQ208 package, when I found I had 216 > pins, instead of 208! > > The offending signals are amongst the GND and VCCO pins. For instance, P208 > (VCCO) is repeated. > > I haven't checked the other packages or parts. > > I've emailed the person responsible. Name withheld to protect the guilty! > > Leon > -- > Leon Heller, G1HSM > leon_heller@hotmail.com > http://www.geocities.com/leon_heller -- Marc Baker Xilinx ApplicationsArticle: 50761
Anyone know how to do a parameterized priority encoder in AHDL? Thanks MikeArticle: 50762
>I'm using a Xilinx Coolrunner CPLD (CMOS I/O's), with a VCC of 3.0 V. >In what range would the inputs be considered floating? The details should be in the data sheet. I'd call anything between a solid low and a solid high (Vil-max, Vih-min) "floating". (maybe the letters are wrong or the min/max swapped) If you put a scope on a floating CMOS input to see what the voltage is, the 1 megohm from the scope will pull it down to a solid low. What happens with FET probes? I haven't learned that the hard way yet. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50763
On Wed, 18 Dec 2002 18:45:55 GMT, Ray Andraka <ray@andraka.com> wrote: >The paid version of modelsim, as well as Aldec have an analog display mode >that lets you display any signal as an "analog" value. You can also write >to a text file and import to Excel (I used to do that with viewlogic >simulations). Hi Ray, Excel has a 32k point limit and rather limited graphing capabilities. This always seems to be a problem for my simulations, so I use gnuplot, http://www.gnuplot.info/ BTW, Simili also displays analog waveforms in its viewer. Regards, Allan. >Kevin Becker wrote: > >> Hi, >> >> for developing an audio application, I need a way to display a bus >> signal as a "real" waveform, not a number. I want to see the actual >> waveform that goes out to the DAC (sine, triangle or whatever). >> >> For example, for an 8bit bus, 00 would be a line at the bottom, 80 >> would be in the middle and FF would be at the top of the wave display. >> >> Can you recommend a software that does this? I'm using WebPack with >> ModelSimXE so far. >> >> Thanks, >> Kevin > >-- >--Ray Andraka, P.E. >President, the Andraka Consulting Group, Inc. >401/884-7930 Fax 401/884-7950 >email ray@andraka.com >http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 50764
It has admittedly been years since I used Excel to view sim plots. For the
cases where I need more capability than the analog trace in modelsim and Aldec
I now export to matlab via the dlmread command in Matlab.
Allan Herriman wrote:
> On Wed, 18 Dec 2002 18:45:55 GMT, Ray Andraka <ray@andraka.com> wrote:
>
> >The paid version of modelsim, as well as Aldec have an analog display mode
> >that lets you display any signal as an "analog" value. You can also write
> >to a text file and import to Excel (I used to do that with viewlogic
> >simulations).
>
> Hi Ray,
>
> Excel has a 32k point limit and rather limited graphing capabilities.
> This always seems to be a problem for my simulations, so I use
> gnuplot, http://www.gnuplot.info/
>
> BTW, Simili also displays analog waveforms in its viewer.
>
> Regards,
> Allan.
>
> >Kevin Becker wrote:
> >
> >> Hi,
> >>
> >> for developing an audio application, I need a way to display a bus
> >> signal as a "real" waveform, not a number. I want to see the actual
> >> waveform that goes out to the DAC (sine, triangle or whatever).
> >>
> >> For example, for an 8bit bus, 00 would be a line at the bottom, 80
> >> would be in the middle and FF would be at the top of the wave display.
> >>
> >> Can you recommend a software that does this? I'm using WebPack with
> >> ModelSimXE so far.
> >>
> >> Thanks,
> >> Kevin
> >
> >--
> >--Ray Andraka, P.E.
> >President, the Andraka Consulting Group, Inc.
> >401/884-7930 Fax 401/884-7950
> >email ray@andraka.com
> >http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50765
Unfortunately this algorithm is rather nasty to do in hardware, requiring a
multiply and divide at each iteration. Methods similar to CORDIC and to
hardware division are easier to implement in a hardware design.
Kip Ingram wrote:
> The general approach to rapidly computing logarithms (used by Henry Briggs
> to generate the log tables he published in 1617) is to first reduce the
> problem to the computation of the logarithm of a value very near 1. Then
> use the power series
>
> log (1+x) = x - x^2/2 + x^3/3 - x^4/4 ......
>
> to get a value of whatever accuracy you need. The "cleverness" is in how to
> creatively move the argument near 1.
>
> A full treatment of this is given in _Dead Reckoning - Calculating Without
> Instruments_ by Ronald Doerfler (ISBN 0-88415-087-9).
>
> Good luck. :-)
>
> Kip Ingram
>
> --
> Get daily news and analysis from the FPGA market for pennies a day.
> Subscribe to
> The FPGA Roundup today: http://www.KipIngram.com/FPGARoundup.html
>
> --
> "John" <john.l.smith@titan.com> wrote in message
> news:5b9931fd.0212111542.5d473661@posting.google.com...
> > "Tim Nicolson" <t.nicolson@signal.qinetiq.com> wrote in message
> news:<1037972506.869047@bengal>...
> > [snip]
> > > The ip algorithm requires that I compute logarithms. This can prove
> > > quite a computationally expensive operation, but I only need accuracy
> > > down to around 4/5 significant figures.
> > [snip]
> > > This method is inexpensive but gives limited accuracy. Operations shown
> > > below
> > >
> > >
> > > z = a + b*mant + c*mant^2 + d*mant^3;
> > >
> > > if (e ~= 0)
> > > z = z + exp * C1;
> > > end;
> > >
> > > This requires 6* and 4+.
> >
> > Hi Tim,
> > I don't have anything to add to the existing discussion
> > of logs (sorry), but if you are evaluating polynomials,
> > you should be aware of Horner's rule ( a personal favorite ):
> >
> > a + b*x + c*x^2 + d*x^3 =
> > ( a + x*(b + x*(c + x*d ) ) )
> >
> > this reduces your 6 mults (??? 7) to 3 (??? 4).
> >
> > [snip]
> >
> > >
> > > Thanks very much for your time.
> > >
> > > Tim
> > >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50766I am getting the following error: "Cell instance 'U78' in 'proc_fpga' is an IOB.Xilinx does not allow IOB <BR> symbols in XNF for their 4000 family FPGAs.Please run the command <BR> 'replace_fpga' to convert the IOBs in this design to gates.(XNFO-11)." I get this error after running the replace_fpga command.I tried to run the command after getting this error but the same error. I have only a single 16 bit "inout" port definition in my program called <BR> memdata. Here is the script: <BR> TOP = proc_fpga <BR> PART = "4010epc84-4" <BR> designer = "Russ Joseph & David Penry" <BR> company = "Princeton University" analyze -format verilog proc_fpga.v <BR> analyze -format verilog control.v <BR> analyze -format verilog datapath.v <BR> analyze -format verilog memcontrol.v <BR> analyze -format verilog narrow.v <BR> analyze -format verilog mux.v <BR> analyze -format verilog /u/rjoseph/public/regfile-syn.v elaborate TOP <BR> current_design proc_fpga <BR> uniquify -force <BR> set_port_is_pad "*" <BR> set_pad_type -slewrate HIGH all_outputs() insert_pads <BR> remove_constraint -all create_clock "clk" -period 50 <BR> check_design <BR> compile <BR> report_fpga > TOP + ".fpga" <BR> report_timing > TOP + ".timing" <BR> check_design <BR> write -h -format db -output TOP + ".db" <BR> check_design <BR> set_attribute TOP "part" -type string PART <BR> set_attribute find(design,"*") "xnfout_use_blknames" \ <BR> -type boolean FALSE ungroup -all -flatten <BR> replace_fpga <BR> write -h -format xnf -output TOP + ".sxnf" <BR> exit Could anyone please help me in this regard?? LoganathanArticle: 50767
hai, Is it possible to implement a 16-bit LFSR using one CLB of XC4000 series. By configuring One 4 to 1 LUT as a shift register, and assuming there is only one 2-inout Xor gate in the feedback? (considering any tap points!) Please let me know how many min. no. of CLB's might require to do this. inputs: clk outputs: dout(1 bit) (serially reading the data_out) Thanks, Dasari.Article: 50768
Dear all, I am an Electrical Engineer and I would like to specialize in the area of VLSI. I wonder if there are any VLSI courses offered in Romania, Austria , Greece or Russia in English(or Russian) commercially/non-commercially that cover perhaps: -Techniques for digital system design -Hardware description languages -Design methodology for VLSI circuits and systems: ASIC, FPGA, PLD -Employing EDA tools like: ModelSim, Leonardo, Xilinx, Altera, etc. That could be either at some company or training center or maybe through distance internet course, please let me know of any details PS How suitable are fpga for realisation of telecom chips for example an OFDM modem core?Article: 50769
Hai Ray!, True. I would like to know if there some proven BIST structures like LFSR, MISR, BILBO.., for standard arithmetics, test point insertion methods etc.. targetted to Xilinx xc4000 architecture which consumes less area. If some one give info. regarding the specific BIST architectures for 16-/32-bit floating/Fixed point(IEEE standard) adders. (some proven results!), it helps me a lot. Thank you all, Dasari. Ray Andraka <ray@andraka.com> wrote in message news:<3E00F72D.9711BDD5@andraka.com>... > There are no dedicated BIST structures, you include whatever you need for > testing in your design which then gets loaded into the FPGA. SRAM type > FPGAs do offer a distinct advantage over conventional logic in that you > can reconfigure to do board level testing, thereby taking the FPGA > functionality out of the loop. My paper "An FPGA Based Processor Yields > a Real Time High Fidelity Radar Environment Simulator", available on my > website at no charge, goes into some detail on system test with > reconfigurable FPGAs. > > dasari wrote: > > > hai, > > > > I would like to know the BIST structures for Xilinx FPGAs for on-line > > functional test. Please let me know if there are some specific > > configurable BIST structures for any generic logic/Arithmetic logic. > > > > Thanks, > > Dasari. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 50770
Stephen Henry <s@s.com> wrote in message news:<Xns92E8E00263B28sscom@80.1.224.4>... > Hi all, > > I remember reading somewhere that under the version of embedded linux for > the xilinx virtex II-Pro, There is a PowerPC 405 embedded as a hardcore in the Virtex II-Pro. It is typically connected through a CoreConnect bus from IBM, for which you can get a free (gratis, not Libre) license from IBM. On that embedded PowerPC 405, it is possible to run Embedded Linux (and otherOS's). In the summer,we have published a port to an engineering board (on the linuxppc-embedded list and on ftp.mind.be) and we can support Embedded Linux on the V2P. Xilinx has implemented a version in the linuxppc_2_4_devel tree. > you could load and unload hardware modules as it > ran -much in the same way that you can do with drivers. Is this true? That is a different story. It is indeed possible to reconfigure the FPGA while it is running, but that is still an area of advanced research. E.g. IMEC (http://imec.be , the main university R&D center here in Leuven) has a research project on reconfigurable Hardware/Software combinations http://www.imec.be/wwwinter/mediacenter/en/reconfigurable.shtml). > If so could you send me a link where i could read up about it? http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Virtex-II+Pro+FPGAs http://www.xilinx.com/ml300 http://www.memec.co.jp/html/xilinx/eboard/docs/dskit2v/v2pro_board_users_guide_1_0.pdf I could also provide you with more detailed information. Did you select a specific board for the development (there are a few commercially available in the range of 1,500 - 3,000 USD from different HW vendors) ? Peter > Cheers, > > Stephen. -- .--------------------------------------------------------. | Mind: Embedded Linux and eCos Development | | Mind is looking for Embedded Linux Developers | |--------------------------------------------------------| | Peter Vandenabeele, CEO email: peter@mind.be | | Mind (http://mind.be) tel: +32-16-30.96.66 | | Vaartkom 11 fax: +32-16-30.96.44 | | B-3000 Leuven, Belgium gsm: +32-478-27.40.69 | '--------------------------------------------------------'Article: 50771
> > Is there any way the async on-board RAM can be used with a synchronous
> > design on the FPGA, without causing any errors ?
Yes. In order to use the async ram reliably you need to use a clock
operating at a higher frequency than the desired ram access, and build a
state machine that accesses the ram in a fashion that meets all the ram
timing requirements. The higher the clock frequency is, the better timing
resolution will be possible.
Register the address, data and control signals in the FPGA so the async ram
inputs are fed directly from the registered outputs (don't put in any
intervening mux's or other logic as this affects routing delays between
signals). Specify timing constraints for the ram signals so that tools can
use these when determining how to build the logic.
Don't try and fudge the delays by building in async elements in the FPGA;
this won't work reliably and will cause nothing but grief. Do a synchronous
design.
The FPGA is probably being clocked at a much higher rate than the external
async ram can be accessed, so there are probably wait states involved in
accessing the ram anyway. I use the simple state machine below. My system
runs at half the clock frequency which is why the ready line is held active
for two cycles. The ram runs at 1/4 the clock frequency. This machine forces
full timing for back-to-back accesses while allowing access to begin on any
clock cycle. The write line pulses low for one cycle in the middle of
access.
If you're using 15ns ram don't expect to be able to access it at 60MHz.
25MHz is more realistic. sram (even async) is great for random access
performance. Even at 25MHz it's operating a lot faster than SDRAM. If you
don't care about the performance interfacing regular DRAM is a snap as it's
an easy extension to the state machine, and DRAM uses fewer pins.
reg [2:0] rcd;
always @(posedge clkib)
begin
if (reset) begin
rcd <= 3'b0;
ram_rdy <= 0;
end
else begin
case(rcd)
0: begin
rcd <= ram_cs;
oe <= ~(rd|ifetch);
we <= 1;
end
1: begin
ram_rdy <= 1;
rcd <= rcd + 1;
we <= ~wr;
oe <= ~(rd|ifetch);
end
2: begin
ram_rdy <= 1;
rcd <= rcd + 1;
we <= 1;
oe <= ~(rd|ifetch);
end
3: begin
ram_rdy <= 0;
rcd <= 0;
oe <= 1;
end
endcase
end
end
Rob
www.birdcomputer.ca
Article: 50772
"Loganathan Lingappan" <loganathan_iitm@yahoo.co.in> wrote in
message news:ee7b04c.-1@WebX.sUN8CHnE...
> I am getting the following error:
> "Cell instance 'U78' in 'proc_fpga' is an IOB.Xilinx does not
allow IOB
> symbols in XNF for their 4000 family FPGAs.Please run the
command
> 'replace_fpga' to convert the IOBs in this design to
gates.(XNFO-11)."
>
> I get this error after running the replace_fpga command.I tried
to run the command after getting this error but the same error.
>
> I have only a single 16 bit "inout" port definition in my
program called
> memdata.
>
<snip>
> Could anyone please help me in this regard??
>
> Loganathan
>
Here is a script we have used in the past - though it hasn't been
tested recently, as Synopsys say you should use FPGA Compiler II
rather than DC nowadays. Perhaps you can compare the scripts to
see if there are any differences?
It looks like both our scripts are based on the template from
Xilinx?
SRCPATH = ../src/
FITPATH = ../fit/
SYNTHPATH = ../synth/
TOP = chip
MOD1 = flowpack
MOD2 = sevensegencoder
MOD3 = counter
MOD4 = prescaler
designer = "Anon"
company = "Doulos"
analyze -format vhdl SRCPATH + MOD1 + ".vhd"
analyze -format vhdl SRCPATH + MOD2 + ".vhd"
analyze -format vhdl SRCPATH + MOD3 + ".vhd"
analyze -format vhdl SRCPATH + MOD4 + ".vhd"
analyze -format vhdl SRCPATH + TOP + "xilinx_dc.vhd"
elaborate TOP
current_design TOP
uniquify
remove_constraint -all
dont_touch {G0}
dont_touch {U1}
create_clock "Clk25M" -period 40
set_pad_type -no_clock {Clk768, nTestMode}
set_port_is_pad "*"
remove_attribute "Clk25M" port_is_pad
set_pad_type -slewrate HIGH all_outputs()
insert_pads
compile -map_effort medium -ungroup_all
report_fpga > TOP + ".fpga"
report_timing > TOP + ".timing"
write -format db -hierarchy -output TOP + "_compiled.db"
replace_fpga
set_attribute TOP "part" -type string "4003epc84-4"
write -format db -hierarchy -output TOP + ".db"
write -format xnf -hierarchy -output FITPATH + TOP + ".sxnf"
write_script > TOP + ".dc"
sh dc2ncf TOP + ".dc" -o FITPATH + TOP +".ncf"
exit
Note that the design instantiates some black boxes, as there
was a problem with Synopsys inferring GSR (I think).
regards
Alan
--
Alan Fitch
[HDL Consultant]
DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire,
BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573 Web:
http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 50773Could you do something like the following: use a series of 10 Delta sigma ADC's operating on the signal in a circular fashion each one sampling one clock cycle after the next ? Rob www.birdcomputer.caArticle: 50774
Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3E010DF1.1685@designtools.co.nz>... > Bill Sloman wrote: > > > > Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3E00C2F3.31A0@designtools.co.nz>... > > > Peter Alfke wrote: > > > > > > > > Don't expect to do this in an FPGA alone, but -if I remember right - a > > > > Sigma-Delta A/D converter is ideal for this applications. Others may > > > > know more or better... > > > > > > There is a lot of science in the better S-D ADC's, but a 2.5MHz sample > > > rate will push a first order one - that indicates a clock speed of 640MHz. > > > There are maths schemes to give higher resolutions, but they usually > > > impact the step response times. > > > > > > FPGAs are inherently noisy, but that need not be inside the Analog Loop > > > - > > > tiny logic gates can buffer from a (very) clean Vcc for the integrator > > > drive. > > > > > > > > > > > Peter Alfke > > > > ================= > > > > Bill Sloman wrote: > > > > > > > > > This is a dumb "wouldn't it be nice if there were a" question. > > > > > > > > > > At the moment we have a fast-ish, relatively low level alaog front end > > > > > whose amplified output is digitised to 8-bits at 2.5MHz, and > > > > > accumulated into 16 32-bit wide bins over about 2000 sampling cycles > > > > > (24-bits would be enough ...). > > > > > > > > > > The conversion noise is visible on the analog signal and the "wouldn't > > > > > it be nice" idea is that if the A/D converter were embedded in an FPGA > > > > > which also managed the accumulation into on-chip RAM, there would be a > > > > > whole lot less conversion noise visible at the front end. > > > > > > So you don't actually need 2.5MHz x 8 - but are trying to sample over > > > 2000 cycles to get more 'bits' - correct ? No. We ned the 2.5MHz sampling rate/bandwidth, but the signal is noisy, and by "computing the average transient" we can reduce the noise on each sample point. > > > Multi-Cycle averaging makes a very important assumption about the > > > errors, that they are random, and evenly distributed. > > > Real ADCs do not always follow classic maths, so large base averages do > > > not give the expected noise reductions. Use a better ADC... I made this point once when refereeing a paper for "Measurement Science and Technology" - not clearly enough, becasue they published it despite my objections. > > > That said, the Sigma-Delta ADCs are good for multi cycle maths, because > > > the integration cap preserves fractional sample info, so you can, for > > > example, have a faster 8 bit loop running, for good step response, > > > and a 12/14/16 bit averaging loop, for good static / low slew following. > > > > > > > > > > > > > In the interests of creeping featurism, a 10-bit A/D converter would > > > > > be interesting, and room for 200 32-bit bins. The 2.5MHz sampling rate > > > > > seems to be perfectly adequate. > > > > > > > > > > I've had a quick look at Lattice's analog FPGA and the analog isn't > > > > > really fast enough while the digital side looks to be rudimentary - is > > > > > there anything better out there? > > > > > > > > > > The application is a low volume (order of 100 per year) industrial > > > > > measuring instrument, so ASICs are out of the question, and > > > > > significant up-front costs would be a real problem. > > > > > > > > > > I suspect that what I'm asking for is a cross-breed between a camel > > > > > and a mantee, but I'd love to be wrong. > > > > > > There are Micro Controllers with 16 & 24 bit ADCs, so the art of mixing > > > Noisy Digital and Analog is getting better, but it is significant that > > > they come from the very experienced Analog players - Burr Brown, and > > > Analog Devices. > > > > The signal processors with built-in A/D and D/A converters were all > > aimed at the audio market when I last looked. Something aimed at > > digital AM radio might be fast enough. > > > > Thanks for all the responses - they've saved me from a fairly tedious > > and time-consuming search. > > > > My own impression was that sigma-delta wasn't going to hack it at > > 2.5MHz, and there seems to be enough support for this opinion for me > > to skip any serious chasing-up there too. > > > > I can't say much about the application, but if I do get the chance to > > experiment I'd like to see what one of the 14-bit digital radio A/D > > converters would do - the frequency distribution of the noise is not > > white, and while the individual 2.5MHz samples are pretty noisy, the > > noise at the lowest frequency we have to detect - when present - is > > quite a lot lower, and we might see some advantage of the better > > linearity of the 14-bit parts. > > The most impressive mix of Analog + Digital I've seen is this > announcement > from Analog Devices : > > ADSP-21992 160 MIPS, 16-bit ADSP-219x DSP Core > 8-channel, 14-bit, 20 MSPS, > 48K words of on-chip RAM, > Price indication was $22.50/10K You are absolutely right - this part will do exactly what I want (and probably eliminate the national debt in its spare time). I hope Analog Devices gets it into full production in time for us to consider using it. In fact the ADSP-21990 or the ADSP-21991 look to be marginally more attractive - both come in a 15mm square ball-grid array, and both have more than enough on-board data RAM for our application. http://www.analog.com/UploadedFiles/Datasheets/619615028ADSP-21990_pra.pdf I'd prefer the ADSP-21992's LQFP 176-lead package if we had the space but a 26mm square device is too big. Thanks very much - if I hadn't asked the question I could have spent a long time looking in the wrong places. ------ Bill Sloman, Nijmegen
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