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Messages from 50700

Article: 50700
Subject: Re: Is it true that if you have a clock routed to non-clock resources then you are not allowed to use the clock nets?
From: mike_mitchener@yahoo.com (Mike Mitchener)
Date: 17 Dec 2002 13:10:52 -0800
Links: << >>  << T >>  << A >>
Depends on what device you are using.

On a Virtex-II, the answer is no it's not true. You may have both
clock and non-clock loads on a net. The clock loads will use the
global buffer lines, and the non-clock loads will use standard routing
resources. As for other devices - try it and see...use fpga_editor to
examine the routing resources used by the clock nets.

However, gating the clock like this is not recommended and will likely
cause problems or not work at all - your gated clock nets will be
delayed from the original clock by a significant amount of time
(possibly several nanoseconds). If the inputs to the flops are from
off-chip, this will result in large hold time requirements (which
maybe you can deal with). If they are internal, then you're likely to
end up with hold time violations that you just can't fix.

Mike

Article: 50701
Subject: Re: Tiny Forth Processors
From: garrya@ihug.com.au (Garry Allen)
Date: 17 Dec 2002 15:29:41 -0800
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> wrote in message news:<3DFECB8E.F1F8CFE7@yahoo.com>...
> Garry Allen wrote:
> > 
> > "Tim" <tim@rockylogic.com.nooospam.com> wrote in message news:<at8md9$rvg$1$8300dec7@news.demon.co.uk>...
> > 
> > > >     Certainly this is not commercially available in the same
> > > > way that other processors are, for example, the 8051 or Coldfire,
> > > > etc...  Where can I get a current Transputer?
> > >
> > > Available like the parts you mention, but the MOQ is a few orders
> > > of magnitude larger.  A little like XC2S30-6VQ100C (Meow)
> > 
> > do a hunt on the ST website for ST20. It is embedded into their DVB
> > decoders eg the ST55xx series.
> > Garry Allen
> 
> I will have to say that ST has one of the worst web sites for finding
> information that I have come across.  Even knowing that I am looking for
> information on the ST20 series of processors, I could find info on
> nothing but the ASIC ST20GP6 chip.  I found a page with a link for the
> ST20 core which was an invalid link.  None of these pages seemed to have
> links back up the heirarchy to find similar related products.  Searches
> on ST55 or DVB turned up nothing.  I am amazed that ST puts up such a
> poor web site.  
> 
> So can you tell us what is noteworthy about this processor?  
> 

I cant say a hell of a lot. A search on omega on the ST site turns up
a little bit but it appears that ST has removed a lot of information
from their site. If you wanted to, you could drag out the ST coasters
from last year and struggle through the information on integrated
chips for set top box applications.

And I am sure that if you were looking at 100000 a year that ST would
love to talk to you through your distributor

We went with another company's product that didnt involve ST20s or
ST20-connect or...
Garry Allen

Article: 50702
Subject: Video timing generator on a Flex 20K / Acex 1K.
From: "Roger" <rogerwilson@hotmail.com>
Date: Tue, 17 Dec 2002 23:35:26 -0000
Links: << >>  << T >>  << A >>
Hi,

I'm about to start a VTR design and am wondering how other people would
choose to enter the design. It's basically a couple of large counters that
preset, time-out, reset etc. and drive memory read lines and blanking lines
on a triple DAC. There will also be a CLUT and 2 FIFO buffers in the FPGA as
well.
Most of the main elements of the design can be brought in as Megafunctions
and this particular design seems to lend itself towards schematic design
entry. However I'm aware this isn't the favoured way these days. I would be
interested to hear other peoples' views on how they would go about entering
this design.

Thanks.

Roger.



Article: 50703
Subject: Re: How to asynchronously reset a flip-flop?
From: Ray Andraka <ray@andraka.com>
Date: Wed, 18 Dec 2002 00:43:10 GMT
Links: << >>  << T >>  << A >>
FDR is a flip-flop with a synchronous reset.  FDC, which has an asynchronous
clear, is what you want.  This is detailed in the libraries guide.

"Christopher R. Carlen" wrote:

> Hi:
>
> I am using a Xilinx XPLA3 CPLD and the WebPack 4.2 software.
>
> I am trying to make a simple circuit consisting of two D-flip flops and
> an AND gate.  The Q outputs of the FFs go to the AND gate inputs, and
> the AND gate output goes to the asynchronous reset inputs of the FFs.
>
> This is to implement a 3-state phase/frequency detector for use in a
> PLL.  The D inputs of the FFs go to VCC, and the clock inputs are the
> real world inputs.  Likewise for the Q outputs as well.
>
> After discovering that the circuit didn't work as expected, I
> reprogrammed the chip to expose a single flip flop to the outside, that
> is, the D, clk, R, and Q signals buffered to four IOs.
>
> I have discovered that the R input is not in fact an asynchronous reset
> input, but instead it doesn't do its thing until a clock pulse comes
> along.  This is very strange, but I suppose I simply assumed that R
> meant something that it doesn't seem to mean.
>
> How can I make an asynchronous flip flop reset input, or an asynchronous
> set for that matter?
>
> I am using the schematic editor, and using the flip flop that is called
> "FDR".  I can post the HDL if you want, but I don't know how to write
> HDL yet.  I think that the schematic creates what the software refers to
> as the "verilog functional model" which is a file that looks like
> program code.  I suspect that I would write that by hand if I wanted to
> design without the schematic entry, right?
>
> Thanks for comments.
>
> Good day.
>
> --
> ____________________________________
> Christopher R. Carlen
> Principal Laser/Optical Technologist
> Sandia National Laboratories CA USA
> crcarle@sandia.gov

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 50704
Subject: Re: Video timing generator on a Flex 20K / Acex 1K.
From: Ray Andraka <ray@andraka.com>
Date: Wed, 18 Dec 2002 00:46:55 GMT
Links: << >>  << T >>  << A >>
Whatever you and your company are most comfortable with.  If schematic gets you
to market faster and your company is willing to maintain a schematic design,
then go for it.  If the design is mostly instantiations, then your HDL would be
little more than a textual netlist anyway.  You might also consider an HDL in
conjunction with a block diagram editor such Renior or the one in the Aldec HDL
tool suite, which will get you a schematic-like entry with the maintainability
of HDL.

Roger wrote:

> Hi,
>
> I'm about to start a VTR design and am wondering how other people would
> choose to enter the design. It's basically a couple of large counters that
> preset, time-out, reset etc. and drive memory read lines and blanking lines
> on a triple DAC. There will also be a CLUT and 2 FIFO buffers in the FPGA as
> well.
> Most of the main elements of the design can be brought in as Megafunctions
> and this particular design seems to lend itself towards schematic design
> entry. However I'm aware this isn't the favoured way these days. I would be
> interested to hear other peoples' views on how they would go about entering
> this design.
>
> Thanks.
>
> Roger.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 50705
Subject: How to asynchronously reset a flip-flop?
From: "Christopher R. Carlen" <crcarle@sandia.gov>
Date: Tue, 17 Dec 2002 17:17:50 -0800
Links: << >>  << T >>  << A >>
Hi:

I am using a Xilinx XPLA3 CPLD and the WebPack 4.2 software.

I am trying to make a simple circuit consisting of two D-flip flops and 
an AND gate.  The Q outputs of the FFs go to the AND gate inputs, and 
the AND gate output goes to the asynchronous reset inputs of the FFs.

This is to implement a 3-state phase/frequency detector for use in a 
PLL.  The D inputs of the FFs go to VCC, and the clock inputs are the 
real world inputs.  Likewise for the Q outputs as well.

After discovering that the circuit didn't work as expected, I 
reprogrammed the chip to expose a single flip flop to the outside, that 
is, the D, clk, R, and Q signals buffered to four IOs.

I have discovered that the R input is not in fact an asynchronous reset 
input, but instead it doesn't do its thing until a clock pulse comes 
along.  This is very strange, but I suppose I simply assumed that R 
meant something that it doesn't seem to mean.

How can I make an asynchronous flip flop reset input, or an asynchronous 
set for that matter?

I am using the schematic editor, and using the flip flop that is called 
"FDR".  I can post the HDL if you want, but I don't know how to write 
HDL yet.  I think that the schematic creates what the software refers to 
as the "verilog functional model" which is a file that looks like 
program code.  I suspect that I would write that by hand if I wanted to 
design without the schematic entry, right?

Thanks for comments.

Good day.

-- 
____________________________________
Christopher R. Carlen
Principal Laser/Optical Technologist
Sandia National Laboratories CA USA
crcarle@sandia.gov


Article: 50706
Subject: Re: ACEX 1K Configuration Time
From: gregs@altera.com (Greg Steinke)
Date: 17 Dec 2002 19:17:08 -0800
Links: << >>  << T >>  << A >>
Khim and all,
There are a few things to keep in mind when computing configuration
time:
- Power on Reset time. This affects the first device configuration.
Since you plan to reconfigure the device, this will not be a big
factor for you. But for future reference, the POR time on the ACEX 1K
devices is 50 microseconds.
- The time to reconfigure the device is computed by taking the data
size and multiplying by the bit period of the configuration clock. The
data size is shown in Table 5 of AN116: Configuring SRAM-based LUT
Devices. For example, an EP1K50 device uses 785,000 bits to configure,
and can accept data up to 33.3 MHz in passive serial mode. Therefore
the reconfiguration takes 23.55 milliseconds.

For fastest configuration, passive serial is better than JTAG as the
passive serial clock can run faster than the JTAG clock. Also, the
JTAG algorithm is slightly more complicated.

By the way, on ACEX 1K devices there is no time difference between
parallel and serial configuration as the parallel data is internally
serialized. Newer devices such as APEX II and Stratix devices have a
"Fast Parallel Mode" that can accept one byte per clock at up to 100
MHz for Stratix devices. In your particular case, ACEX 1K devices may
still be better; the Stratix device programming file is longer since
the devices are larger and have more features so the programming time
is not really shorter.

Also, note that the configuration takes the same time, no matter if
the device is 1% or 100% used. The exception to this is the upcoming
Cyclone family, which incorporates compression into the FPGA. A
bitstream for a lightly-used device will compress more effectively
than for a heavily-used device, so in this case device utilization
will affect configuration time.

Sincerely,
Greg Steinke
gregs@altera.com

khimbittle@cliftonNOSPAMsystems.com (Khim Bittle) wrote in message news:<3dff5dba.4946969@news.compuserve.com>...
> On Tue, 17 Dec 2002 17:51:18 +0100, Rene Tschaggelar
> <tschaggelar@dplanet.ch> wrote:
> 
> >Khim Bittle wrote:
> >> Configuration time for the Altera ACEX 1K parts according to the data
> >> sheet is "less than 40ms" ... perhaps there is additional information
> >> but I can't seem to find it.  I figure that the configuration time
> >> varies considerably between the EP1K10 and the EP1K100 but I would
> >> like to know how much time I should expect for the different size
> >> parts , does anyone have any real experience here and can give me some
> >> better numbers ?  Thanks ,  Khim Bittle
> >> 
> >> ( These parts are being designed into a video processor which needs to
> >> reload the array once or twice with a selected algorithm during a
> >> processing cycle )
> >> 
> >
> >I'm currentl investigating the embedded programmability
> >of these devices.
> >
> >There are various influences to consider :
> >The programming clock, JTAG can go up to 10MHz.
> >The programming mode, parallel is probably faster than serial.
> >Assuming that only the ones(or zeroes) have to be
> >written, how full is your device ?
> >
> 
> Since fast loading is vital for my application I am only considering
> parallel mode with external memory or processor selected to configure
> the Altera part as fast as it can handle it.
> 
> Khim Bittle
> 
> (remove NOSPAM in email )

Article: 50707
Subject: Re: ACEX 1K Configuration Time
From: khimbittle@cliftonNOSPAMsystems.com (Khim Bittle)
Date: Wed, 18 Dec 2002 03:27:48 GMT
Links: << >>  << T >>  << A >>

Greg, thank you for the good information, Khim Bittle

On 17 Dec 2002 19:17:08 -0800, gregs@altera.com (Greg Steinke) wrote:

>Khim and all,
>There are a few things to keep in mind when computing configuration
>time:
>- Power on Reset time. This affects the first device configuration.
>Since you plan to reconfigure the device, this will not be a big
>factor for you. But for future reference, the POR time on the ACEX 1K
>devices is 50 microseconds.
>- The time to reconfigure the device is computed by taking the data
>size and multiplying by the bit period of the configuration clock. The
>data size is shown in Table 5 of AN116: Configuring SRAM-based LUT
>Devices. For example, an EP1K50 device uses 785,000 bits to configure,
>and can accept data up to 33.3 MHz in passive serial mode. Therefore
>the reconfiguration takes 23.55 milliseconds.
>
>For fastest configuration, passive serial is better than JTAG as the
>passive serial clock can run faster than the JTAG clock. Also, the
>JTAG algorithm is slightly more complicated.
>
>By the way, on ACEX 1K devices there is no time difference between
>parallel and serial configuration as the parallel data is internally
>serialized. Newer devices such as APEX II and Stratix devices have a
>"Fast Parallel Mode" that can accept one byte per clock at up to 100
>MHz for Stratix devices. In your particular case, ACEX 1K devices may
>still be better; the Stratix device programming file is longer since
>the devices are larger and have more features so the programming time
>is not really shorter.
>
>Also, note that the configuration takes the same time, no matter if
>the device is 1% or 100% used. The exception to this is the upcoming
>Cyclone family, which incorporates compression into the FPGA. A
>bitstream for a lightly-used device will compress more effectively
>than for a heavily-used device, so in this case device utilization
>will affect configuration time.
>
>Sincerely,
>Greg Steinke
>gregs@altera.com
>
>khimbittle@cliftonNOSPAMsystems.com (Khim Bittle) wrote in message news:<3dff5dba.4946969@news.compuserve.com>...
>> On Tue, 17 Dec 2002 17:51:18 +0100, Rene Tschaggelar
>> <tschaggelar@dplanet.ch> wrote:
>> 
>> >Khim Bittle wrote:
>> >> Configuration time for the Altera ACEX 1K parts according to the data
>> >> sheet is "less than 40ms" ... perhaps there is additional information
>> >> but I can't seem to find it.  I figure that the configuration time
>> >> varies considerably between the EP1K10 and the EP1K100 but I would
>> >> like to know how much time I should expect for the different size
>> >> parts , does anyone have any real experience here and can give me some
>> >> better numbers ?  Thanks ,  Khim Bittle
>> >> 
>> >> ( These parts are being designed into a video processor which needs to
>> >> reload the array once or twice with a selected algorithm during a
>> >> processing cycle )
>> >> 
>> >
>> >I'm currentl investigating the embedded programmability
>> >of these devices.
>> >
>> >There are various influences to consider :
>> >The programming clock, JTAG can go up to 10MHz.
>> >The programming mode, parallel is probably faster than serial.
>> >Assuming that only the ones(or zeroes) have to be
>> >written, how full is your device ?
>> >
>> 
>> Since fast loading is vital for my application I am only considering
>> parallel mode with external memory or processor selected to configure
>> the Altera part as fast as it can handle it.
>> 
>> Khim Bittle
>> 
>> (remove NOSPAM in email )


Article: 50708
Subject: PLD Project of the Month
From: alw@al-williams.com (Al Williams)
Date: 17 Dec 2002 21:20:10 -0800
Links: << >>  << T >>  << A >>
Some of you know we have started a simple "PLD Project of the Month"
every month on our Web site to compliment our tutorials (at
http://tutor.al-williams.com). The December project is up.

Have a look and let me know what you think:
http://www.al-williams.com/pom.htm

Al Williams
AWC

Article: 50709
Subject: Different Versions of Coregen
From: Kload <aperson@somewhere.com>
Date: Wed, 18 Dec 2002 16:23:10 +1000
Links: << >>  << T >>  << A >>
Hello all,

I have been using the Xilinx 2.1i student edition software for a while 
now with my Virtex XVC800 device.  The software itself works well 
however I can't use the latest COREs with V2 of the CoreGen software. 
So I bought the Xilinx 4.1i Student Edition software.  I was aware there 
may be difficulties porting my old projects to this new software since 
the file formats are significantly different.

However the biggest problem is that the 4.1i software does not support 
my Virtex device.  I know I should have checked before I bought it, but 
the older software supported the XVC800 so I just assumed the new 
software would too.

Anyway, before I try returning the software, I was wondering whether it 
would be possible to set up a project in the V4 software (for an XVC300 
device, the largest device supported), generate the cores I require 
(being careful not to use RPM), then somehow import the resulting data 
into the V2 software.

Any help at all on this front is much appreciated
Thanks


Article: 50710
Subject: Re: Video timing generator on a Flex 20K / Acex 1K.
From: kayrock66@yahoo.com (Jay)
Date: 17 Dec 2002 22:29:05 -0800
Links: << >>  << T >>  << A >>
VTR- Video Tape Recorder?

"Roger" <rogerwilson@hotmail.com> wrote in message news:<wEOL9.3831$594.249355@newsfep2-gui>...
> Hi,
> 
> I'm about to start a VTR design and am wondering how other people would
> choose to enter the design. It's basically a couple of large counters that
> preset, time-out, reset etc. and drive memory read lines and blanking lines
> on a triple DAC. There will also be a CLUT and 2 FIFO buffers in the FPGA as
> well.
> Most of the main elements of the design can be brought in as Megafunctions
> and this particular design seems to lend itself towards schematic design
> entry. However I'm aware this isn't the favoured way these days. I would be
> interested to hear other peoples' views on how they would go about entering
> this design.
> 
> Thanks.
> 
> Roger.

Article: 50711
Subject: Re: what makes an implementation a patent?
From: "glen herrmannsfeldt" <gah@ugcs.caltech.edu>
Date: Wed, 18 Dec 2002 06:35:58 GMT
Links: << >>  << T >>  << A >>

"Austin Franklin" <austin@da98rkroom.com> wrote in message
news:uvpi25jr3v0ka6@corp.supernews.com...
>
> "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message
> news:Sh7K9.339038$P31.129678@rwcrnsc53...
> >
> > "hristo" <hristostev@yahoo.com> wrote in message
> > news:b0ab35d4.0212120822.46ba96e@posting.google.com...
> > > Hello,
> > > general question here, sorry if it is off-topic.
> > >
> > > what makes an implementation be elligible for a patent status?
> > >
> > > i expect Novelty first. But if someone takes an architecture and
> > > optimise it according to a special FPGA (eg.  Virtex), so he takes the
> > > maximum of the chip features to implement it optimally. can he submit
> > > this work for a patent??
> >
> > Since the XOR operator has been patented, and upheld twice,
> > I would say that it doesn't take much to be eligible.
>
> I had not heard that.  Do you have case numbers for those "upholdings"?
>
> That would amaze me that it could even possibly be upheld (or even granted
> in the first place)...as no one throughout time ever said "No one can be
on
> this horse, or either you or I can be on this horse, but not both of
> us"...or something to that effect.

It was on of the GNU/FSF favorite examples.  That is where I saw it.
The other is backing store for windowing systems, saving the contents
of covered up windows to restore later.

In a Scientific American in the last year there were examples, including
teaching with a manual.

-- glen



Article: 50712
Subject: FPGA instead of HDMP-1022/24
From: naderimisc@yahoo.com (Masoud Naderi)
Date: 18 Dec 2002 01:01:48 -0800
Links: << >>  << T >>  << A >>
Hi,
I want to design a board with HDMP-1022/24 (fiber
driver/receiver)chip. This IC is from Agilent and has a
serializer/deserializer, 8b/10b coder and PLL inside. Now I want to
know is it possible to design an FPGA that work COMPLETELY instead of
HDMP-1022/24? Do you have any experiences on this or know any
resources?
With best regards
Masoud Naderi

Article: 50713
Subject: Re: Internal_Error of ISE 5.1.02i xst F.25.
From: "Alan Fitch" <alan.fitch@doulos.com>
Date: Wed, 18 Dec 2002 09:23:53 -0000
Links: << >>  << T >>  << A >>
"Hua Ai" <hai@ualberta.ca> wrote in message
news:atnv8i$9es$1@pulp.srv.ualberta.ca...
> Thanks, Alan. But I already checked that record and those
solutions
> don't apply to my case. After some analysis, I think it's
probably a bug
> of ISE 5.1i for solaris.
>

OK, I hope my reply didn't sound sarcastic.

> My design is something like this. I have a synthesizable
function block
> which integrated block memory cores and some MAC cores. I simply
need to
> integrate multiple such function blocks together in a higher
level.
> Those memory cores will have to be organized into a bigger
memory block
> therefore I need a decoder to decode some address lines to drive
those
> memory enables.
>
> Here is the problem: if I don't use the decoder at all (i.e. all
the
> enable ports are drived by one signal), then the design could be
> synthesized by ISE 5.1i for solaris. In this case, all my
function
> blocks are synthesized without problem. But if I add a decoder
written
> by concurrent statements (with ... select ..., or when ... else)
or by
> case statement, the error will occur when xst is doing low level
> synthesis and it reports the internal message:
>
> ==========
> Library "/CAD/tools/xilinx/data/librtl.xst" Consulted
> INTERNAL_ERROR:Xst:cmain.c:3195:1.89.2.1 -  To resolve this
error,
> please consult the Answers Database and other online resources
at
> http://support.xilinx.com
> -->
> ==========

<snip>
>
> I would appreciate if anyone could give a shot to this problem.
It would
> be even greater if someone in xilinx have interests to further
analyze
> this with me, after all, I probably still have to switch my work
to solaris.
>
Unfortunately we've only got 4.2i on Solaris.

I would suggest that you report it to Xilinx as a bug. Most tool
vendors
are pretty responsive to bug reports, and of course if they don't
know
about it they can't fix it!

One other thing to try is to check the patches applied on your
system
and check if Xilinx says that any particular patches are needed to
Solaris.
This often fixes problems.

Unfortunately this is in the realm of Solaris system
administration...

regards

Alan


--
Alan Fitch
[HDL Consultant]

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Article: 50714
(removed)


Article: 50715
Subject: Avoiding SRL16 in Synplify
From: "John Daae" <john.daae@datarespons.no>
Date: Wed, 18 Dec 2002 10:26:29 +0100
Links: << >>  << T >>  << A >>
Hi,

I am using Synplify 7.1 and I want to implement a delay line using registers
and not SRL16 in a Xilinx architecture. I thought that would be straight
forward using attributes as shown below, but I seem to miss out on
something.

Best Regrads

John Daae


############################################################################
#
library ieee;
use ieee.std_logic_1164.all;

entity test is
  port (
    a   : in  std_logic;
    b   : out std_logic;
    clk : in  std_logic
    );
end entity test;


architecture str of test is

  --------------------------------------------------------------------------
---
  -- Internal signal and attribute declarations
  --------------------------------------------------------------------------
---
  signal a_d1 : std_logic;
  signal a_d2 : std_logic;

  attribute syn_srlstyle         : string;
  attribute syn_srlstyle of a_d1 : signal is "registers";
  attribute syn_srlstyle of a_d2 : signal is "registers";

begin  -- architecture str

  process (clk) is
  begin  -- process
    if clk'event and clk = '1' then     -- rising clock edge
      a_d1 <= a;
      a_d2 <= a_d1;
      b    <= a_d2;
    end if;
  end process;

end architecture str;

############################################################################
#



Article: 50716
Subject: Re: Video timing generator on a Flex 20K / Acex 1K.
From: jonathan.bromley@doulos.com (Jonathan Bromley)
Date: 18 Dec 2002 01:37:14 -0800
Links: << >>  << T >>  << A >>
"Roger" <rogerwilson@hotmail.com> wrote...

> I'm about to start a VTR design and am wondering how other people would
> choose to enter the design. It's basically a couple of large counters that
> preset, time-out, reset etc. and drive memory read lines and blanking lines
> on a triple DAC. There will also be a CLUT and 2 FIFO buffers in the FPGA as
> well.
> Most of the main elements of the design can be brought in as Megafunctions
> and this particular design seems to lend itself towards schematic design
> entry. However I'm aware this isn't the favoured way these days. I would be
> interested to hear other peoples' views on how they would go about entering
> this design.

I've found that the most convenient way to do this kind of sequencer
is to divide the video line into sections - front porch, vsync,
back porch, burst, active video etc - and use a small register, typically
3 or 4 bits, to represent this "which section am I in" state information.  
Meanwhile there's a pixel counter grinding away;  it's usually a good
idea to reset the pixel counter to zero at the beginning of active 
video rather than on the horizontal datum, so that the count value 
ties up with pixel numbers on the video line - that makes it much
simpler to do overlays and suchlike.

Now you can use the "state" counter to address a small memory.
Each word in this memory contains the pixel count value on which
the state should change next.

You can then decode the state register to generate sync, blanking
and so forth, and also create a control signal that decides whether
the state register should increment or reset at the next change.

This is easy to code in VHDL or Verilog...

reg [11:0] pixcount;         // pixel counter
reg [3:0] state;             // where am I on the line?
reg [11:0] limit_mem[0:15];  // pixcount at the end of this section
reg line_sync, line_blank;   // output registers

// state names
parameter
  active_video=0, front_porch=1, sync=2, back_porch=3;
// a real design would need more than this!

always @(posedge clk or posedge rst)
  if (rst) begin
    pixcount <= 0;
    state <= active_video;
    line_sync <= 0;
    line_blank <= 0;
  end else begin
    // Default action is for pixel counter to increment
    pixcount <= pixcount+1;
    // But if it just reached the end of the current state,
    // it's time to move on...
    if (pixcount == limit_mem[state]) begin
      // Usually the outputs will be inactive:
      line_sync <= 0;
      line_blank <= 0;
      // Outputs and other actions determined by current state:
      case (state) begin
        active_video:
          begin
            state <= front_porch;
            line_blank <= 1;
          end
        front_porch:
          begin
            state <= line_sync;
            line_blank <= 1;
            line_sync <= 1;
          end
        line_sync:
          begin
            state <= back_porch;
            line_blank <= 1;
          end
        back_porch:
          begin
            state <= active_video;
            pixcount <= 0;
          end
        default:        
          begin
            state <= active_video;
            pixcount <= 0;
          end
      endcase
    end
  end

Then it's all done except for filling in the values in the
limit_mem[] ROM.  You could easily put the outputs and 
next-state values in the same ROM too, and then you could
make the ROM a RAM instead and have it loadable from your
CPU.  Bingo, a fully programmable sync generator in 40
lines of Verilog.  Beats schematics any day :-)

Vertical timing is a bit messier but the same ideas
work pretty well.  Then you need a little bit of logic
to combine vertical and horizontal timing signals for
the RAMDAC.

Hope this helps.
-- 
Jonathan Bromley
Doulos Ltd

Article: 50717
Subject: Re: Strange error on Xilinx Bitgen/Netcheck DRC check
From: Shareef Jalloq <sjalloq@REMOVEarm.com>
Date: Wed, 18 Dec 2002 09:47:52 +0000
Links: << >>  << T >>  << A >>
I've only ever had those errors when there has been an unconnected siganl
in the design.  Record Number: 2544 might help.

Shareef.



Article: 50718
Subject: Power Estimation
From: xest@intracom.gr (Xefteris Stefanos)
Date: 18 Dec 2002 02:08:32 -0800
Links: << >>  << T >>  << A >>
Hello,
My problem in a few words is this: I have done toggling activity
estimation and now I want to use this to apply power estimation on my
design.But,I havent yet found the way to incorporate the toggling
estimation in my power estimation.
Can this be done?Are there any of the excel sheets the companies
provide TRULY useful?Or power estimation is left to the "student as an
exercise"?And even without toggling estimation,are these spreadsheets
close to reality?Or do I have to take the results and combine them
with my own experience (being new to the profession,I admit I have not
tons of it) and predict the actual power consumption?? I am using
Xilinx's FPGA's,Modelsim and ISE.
Any suggestions???
Thanks in advance

Xefteris Stefanos
Mathematician - HW designer
Intracom S.A
Greece

Article: 50719
Subject: Re: Xilinx FPGA PAR warning
From: dirk.doerr@delsy.de (Dirk_Doerr)
Date: 18 Dec 2002 03:16:40 -0800
Links: << >>  << T >>  << A >>
kayrock66@yahoo.com (Jay) wrote in message news:<d049f91b.0212171051.3b108d74@posting.google.com>...

> You ran your synthesis tool and neglected to tell it to instantiate
> I/O cells (IOBs).  The P&R tool sees this, gives you a warning, then
> automatically puts them in for you knowing the port directions from
> your netlist.  Am I close?
> 

I am not sure if I understand you correctly. If you think that I don't
use an ucf file you are wrong. My ucf file contains a net entry for
each io signal of the toplevel vhdl entity.

Regards

Dirk Dörr

Article: 50720
Subject: A/D converter in FPGA
From: bill.sloman@ieee.org (Bill Sloman)
Date: 18 Dec 2002 03:38:18 -0800
Links: << >>  << T >>  << A >>
This is a dumb "wouldn't it be nice if there were a" question.

At the moment we have a fast-ish, relatively low level alaog front end
whose amplified output is digitised to 8-bits at 2.5MHz, and
accumulated into 16 32-bit wide bins over about 2000 sampling cycles
(24-bits would be enough ...).

The conversion noise is visible on the analog signal and the "wouldn't
it be nice" idea is that if the A/D converter were embedded in an FPGA
which also managed the accumulation into on-chip RAM, there would be a
whole lot less conversion noise visible at the front end.

In the interests of creeping featurism, a 10-bit A/D converter would
be interesting, and room for 200 32-bit bins. The 2.5MHz sampling rate
seems to be perfectly adequate.

I've had a quick look at Lattice's analog FPGA and the analog isn't
really fast enough while the digital side looks to be rudimentary - is
there anything better out there?

The application is a low volume (order of 100 per year) industrial
measuring instrument, so ASICs are out of the question, and
significant up-front costs would be a real problem.

I suspect that what I'm asking for is a cross-breed between a camel
and a mantee, but I'd love to be wrong.

-----
Bill Sloman, Nijmegen

Article: 50721
Subject: Re: Avoiding SRL16 in Synplify
From: Steven Derrien <sderrien@irisa.fr>
Date: Wed, 18 Dec 2002 12:40:21 +0100
Links: << >>  << T >>  << A >>
Hello, just add a reset signela to your delay line,
this will force symplify to create registers.

Steven
John Daae wrote:

> Hi,
>
> I am using Synplify 7.1 and I want to implement a delay line using registers
> and not SRL16 in a Xilinx architecture. I thought that would be straight
> forward using attributes as shown below, but I seem to miss out on
> something.
>
> Best Regrads
>
> John Daae
>
> ############################################################################
> #
> library ieee;
> use ieee.std_logic_1164.all;
>
> entity test is
>   port (
>     a   : in  std_logic;
>     b   : out std_logic;
>     clk : in  std_logic
>     );
> end entity test;
>
> architecture str of test is
>
>   --------------------------------------------------------------------------
> ---
>   -- Internal signal and attribute declarations
>   --------------------------------------------------------------------------
> ---
>   signal a_d1 : std_logic;
>   signal a_d2 : std_logic;
>
>   attribute syn_srlstyle         : string;
>   attribute syn_srlstyle of a_d1 : signal is "registers";
>   attribute syn_srlstyle of a_d2 : signal is "registers";
>
> begin  -- architecture str
>
>   process (clk) is
>   begin  -- process
>     if clk'event and clk = '1' then     -- rising clock edge
>       a_d1 <= a;
>       a_d2 <= a_d1;
>       b    <= a_d2;
>     end if;
>   end process;
>
> end architecture str;
>
> ############################################################################
> #


Article: 50722
Subject: Re: A/D converter in FPGA
From: "Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it>
Date: Wed, 18 Dec 2002 12:07:33 GMT
Links: << >>  << T >>  << A >>
"Bill Sloman" <bill.sloman@ieee.org> ha scritto nel messaggio
news:7c584d27.0212180338.70649bbc@posting.google.com...

> The conversion noise is visible on the analog signal and
> the "wouldn't
> it be nice" idea is that if the A/D converter were
> embedded in an FPGA
> which also managed the accumulation into on-chip RAM,
> there would be a
> whole lot less conversion noise visible at the front end.
> [...]

Instead of using an analog FPGA, you can easily implement a sigma-delta
ADC with a normal FPGA. If you look among the Xilinx application notes,
I'm quite sure there is what you need.

(later...)

See

http://www.xilinx.com/xapp/xapp154.pdf
http://www.xilinx.com/xapp/xapp155.pdf

--
Lorenzo



Article: 50723
Subject: Re: A/D converter in FPGA
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Wed, 18 Dec 2002 12:15:03 GMT
Links: << >>  << T >>  << A >>
Hi Bill,

not exactly what you search, but an idea:

You can build the digital part of a sigma delta ADC in the FPGA. As external
components you only need a precise switch, an integrator (RC) and a
comperator with voltage reference.

> In the interests of creeping featurism, a 10-bit A/D converter would
> be interesting, and room for 200 32-bit bins. The 2.5MHz sampling rate
> seems to be perfectly adequate.

10 bit at 2.5 MHz are a little bit too much for this approach. But I've done
this ADC in a very simple manner: using FPGA output for the switch, RC for
integration and a comperator. It works fine for lower resolution and
frequency.

You can find VHDL source under: http://www.jopdesign.com/download.html and
schematics for the external part under:
http://www.jopdesign.com/board/baseio2.pdf

Martin Schoeberl



Article: 50724
Subject: Re: A/D converter in FPGA
From: allan_herriman.hates.spam@agilent.com (Allan Herriman)
Date: Wed, 18 Dec 2002 12:39:08 GMT
Links: << >>  << T >>  << A >>
On Wed, 18 Dec 2002 12:07:33 GMT, "Lorenzo Lutti"
<lorenzo.lutti@DOHtiscalinet.it> wrote:

>"Bill Sloman" <bill.sloman@ieee.org> ha scritto nel messaggio
>news:7c584d27.0212180338.70649bbc@posting.google.com...
>
>> The conversion noise is visible on the analog signal and
>> the "wouldn't
>> it be nice" idea is that if the A/D converter were
>> embedded in an FPGA
>> which also managed the accumulation into on-chip RAM,
>> there would be a
>> whole lot less conversion noise visible at the front end.
>> [...]
>
>Instead of using an analog FPGA, you can easily implement a sigma-delta
>ADC with a normal FPGA. If you look among the Xilinx application notes,
>I'm quite sure there is what you need.
>
>http://www.xilinx.com/xapp/xapp154.pdf
>http://www.xilinx.com/xapp/xapp155.pdf

These won't even come close to being able to convert 10 bit values at
2.5MHz.

Bill will need to use an external ADC.  IMO it's the only way to keep
the noise down.  FPGAs are fairly noisy things in my experience.

Let's see: 200 x 32 bit bins = 6.4kbits
This will easily fit in an XC2S15 (~$10 at digikey) using block ram
for the bins, even if the bins were double banked (so that one set
could be read out by a cpu while the next set are being accumulated).

Company 'A' will also have suitable parts.

Regards,
Allan.



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