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This is a multi-part message in MIME format. ------=_NextPart_000_006C_01C2A8DB.E8004070 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Hi Ray. Not even one of the best engineers I know are PhD's, and I've worked = with many many many exceptional engineers from the top engineering = companies. In fact, most of the best engineers I know don't even have a = masters, and probably half of them don't have a degree at all....as the = programs to do what they do weren't around when they were in school. Austin "Ray Andraka" <ray@andraka.com> wrote in message = news:3E03860B.DA2A741A@andraka.com... Seems somewhat limiting, but then it is an employer's market more or = less. It would rule me out too, as well as the few people I know to be = very strong in both FPGAs and computer arithmetic/DSP.Article: 50876
Not interested anyway, but that is beside the point. Still, it is hard enough
to find someone with enough depth in two of the three to be useful. Hardware
and DSP haven't had a very strong overlap over the past 25 years. There is even
less overlap with either hardware or algorithms with molecular biology. I'd
take someone who has depth over breadth, provided I found someone who could
interact well with the other experts on my staff.
glen herrmannsfeldt wrote:
>
> Not to say that you wouldn't do a great job, but sometimes
> they want someone to understand FPGA design, algorithm
> design, and molecular biology. There are plenty of B.S.
> out there that understand two of the three, but finding all
> three is harder.
>
> -- glen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50877
Ray Andraka <ray@andraka.com> wrote:
> A qualifier to the responses the OP has received so far. The design will
> run at that speed provided the input clock has no jitter on it. Earlier
> versions of the tools would set the specified constraint as a minimum and
> would provide a routed solution that many times would b e significantly
> better. The v4.1 and later tools router is lazy, so you will only beat your
> constraint by a couple hundred ps in many cases. If you look at the
> resulting routing, you might be appalled at what the router has done.
> Unfortunately there is no easy fix other than setting the constraints
> higher, and even then the resulting route is quite sloppily done.
"Might be appalled"?? Sir, you jest! Try: "Will be appalled and
amazed". And did I mention appalled?
It is important that all constraints take clock jitter into account.
Input setup and output delay times should take the clock skew between
the source clock and the destination clock, jitter from the source
clock, the output delay of the source part(s), the best estimate of
board propagation delay and finally jitter in the destination clock.
The idea is to build a design that "just works". First time, every
time, all the time.
There is also the "little" issue of tilde. I didn't mention it as it
applies to parts older than VirtexII. With Spartan, Virtex and VirtexE
designs it's possible for the router to produce a route using too many
passive switches to accurately analyze the timing. To find out if your
design has this problem, search the design.dly file for a tilde
character ~ . If you find one, your design may not work over
process/temperature/voltage extremes. 5.1 seems to have a larger
problem with this, I'd suggest using older revisions of software for
Spartan, Virtex and VirtexE designs. Also may want to add
penalize_tilde to the design.pcf file.
Ken McElvain wrote:
> > Synthesis tools, on the other hand, may need set to a frequency other
> > than the design frequency, especially when you get to doing designs that
> > push the limits of the parts and/or tools. As a beginner, put this in
> > the back of your brain, and don't try to use it yet. When (not if) you
> > get a situation where the synthesis tool is mucking with your design in
> > a bad way remember it.... And if you do this, don't forget to disable
> > the synthesis from sending the fake timing to PAR.
>
> This is why Synplify has a "-route" adjustment to clock specifications
> which is an extra squeeze adjustment that is taken into account during
> synthesis but not passed on to P&R. It can also be specified on paths
> starting or ending at specific registers. Synthesis can get the logic
> delays right, but routing delay has a lot of noise in it unless you use
> physical synthesis.
I don't allow the synthesis tool to forward annotate timing I don't see
anything to gain by doing so, and as I don't trust the synthesis tool to
get it right based on past experiences.
The problem is this: the synthesis tool needs the timing in a different
format than the PAR tool. I might enter, document and verify the timing
in the synthesis tool, make adjustments as needed with "-route", and
then verify the resulting timings transformed by the synthesis tool into
the PAR tools syntax that have forward annotated are correct. This
means I need to verify timings twice, in two different formats,
involving doing a lot of conversion between them. This is more work for
no gain.
Or I might enter a rough version of the timing into the synthesis tool,
adjust it as needed to produce acceptable results, not allow the
synthesis tool to forward annotate timing, and make the design.ucf file
_the_ source of timing information ("the golden file"). I need to enter
it and verify it there, but that's less work than verifying both the
synthesis constraint file and the forward annotated version.
Also, it's important to look at the output of static timing (the
design.twr file) very carefully to make sure that the timing was
correctly checked for all signals. If the timing is documented in the
synthesis format, I need to convert formats to do this. And this is
something I do multiple times during a design. Once again it is less
work to make the golden file the design.ucf file.
I don't trust synthesis tools to get the timing forward annotated
correctly as I've caught them doing it wrong too many times before. A
sample of issues not handling correctly in the past: DLL doubling
clocks, the extra constraints needed with multiple clock domains, and
adding constraints I didn't ask for on inputs sampled by two different
clocks. And even if I did trust synthesis tool to forward annotate
timing, if the designer is being careful to verify results against the
golden timing document, it is more work to make this document the input
to synthesis rather than the input to PAR and TRCE, and no gain from
doing so.
While I've got your ear, I'd like to ask again that the next revision of
Amplify have some way to allow the period to NOT be forward annotated,
other than not writing the design.ncf file. Or to write it out and then
running a script to wack the period specification out during the build
script, which is what I'm going to be doing.
--
Phil Hays
Article: 50878Peter Alfke wrote: > > Weifeng Xu wrote: > > > Hi, > > I have a question about the Xilinx Routing Tools. Assuming we can > > find some broken interconnections such as single lines, is there > > anyway to guide > > the Xilinx tools not to use those faulty components while we do the > > routing? > > > > We do not sell faulty parts. > If you find something originally broken, return the part and get a new > one. And try to identify the fault in the part to Xilinx, as they will improve their tests when they get a part with a failure that their tests didn't catch. It's rare, but it happens. -- Phil HaysArticle: 50879
John Jakson wrote: > > I kind of posted it to illustrate the nonsense that goes on when two > cultures that normally do not work together are forced to rub shoulders. > In this particular case the company involved is 50 people with 30+ Phd > Bioinformatics types who do not understand that you can be a brilliant > and employed engineer and not even degreed (I know a few) let alone have > a Phd let alone selected to 5 schools. Now we all expect medical Dr's to > be Phd'ed otherwise they wouldn't be a Dr for the obvious legal reasons, > but I haven't ever worked with Phd EEs as a matter of legal necessity. A > few have, but most don't. > > Anyway I hope that all the good available EEs in this group who do know > what they are doing do apply for these positions. Eventually they will > get the message that there probably aren't too many ivory tower virgins > for them to recruit. > > Once they realize the cultural difference, 8 lucky guys might get busy. > > Irony is that even most of Xilinx or Altera EEs are also unqualified to > work on this FPGA project, hee hee. The ad I saw for "Senior FPGA and ASIC Engineer to build SuperComputer" did not require a PhD, an MS is sufficient. But I do see what you mean with their request for a graduate of a "TOP school". I ran into something similar when I applied for employment at a company making equipment for medical lab testing. The founders of the company were PhD chemists and had the same view of the world. They were very strong on what showed up on your resume vs. most engineering companies who seem more interested in finding out what you "really" know. They also had obsessive demands for privacy. They would not allow anyone to enter the building unless they signed the visitors log which was a small non-disclosure agreement. Very odd. I agree that there is a big difference in cultures between the biological/chemical sciences and engineering. I think this is largely due to the fact that often the real acheivements in those sciences are what happens in the lab which is documented on paper while most engineering acheivements are in the field as products. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50880
ed wrote: > > Hello All, > > I am doing a desing that's supposed to run at a 100Mhz in a Virtex-II. > Is it good desing practice to run the synthesis and PAR tool with > higher frequency constraints (ie: 120Mhz)? Or can I assume that if the > PAR tool says a design > meets the 100Mhz constraints, the desing CAN and WILL run at a 100Mhz? I read the responses to your post and I am not clear about the other answers. If you have a clock with a 10 nS period and you have 500 ps of jitter, I would suggest that you specify a clock period of 9.5 nS or 105.3 MHz. I believe that Ray's response is the only one that addressed this. As some indicated, the routes can and will be very, very close to the requirement, so if you don't constrain the paths to include the clock jitter, the design can end up not meeting your true timing needs. Of course this will most likely only fail under the worse case of chip process, temperature and voltage variation. This is why many designers can get away with ignoring clock jitter; their designs seldom or never are exposed to both temperature and voltage variation enough to get a marginal chip which will make the design fail. So if you don't include clock jitter in your clock spec, it will most likely work in 99.9% of the units you ship. But to exclude that 1 in 1000 failure mode, you should include it. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50881
Russell <rjshaw@iprimus.com.au> writes: > I need a linux version of webpack with a gui > that works. If it wasn't for spartan-II devices > with distributed ram (SRL16) and some floorplanning > ability, i'd be using altera now. The Qaurtus II Web Edition is not available for Linux. However, the full version of Quartus II is. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 50882
They also had
>obsessive demands for privacy. They would not allow anyone to enter the
>building unless they signed the visitors log which was a small
>non-disclosure agreement. Very odd.
Not uncommon where serious patents are involved.
They are worried about some little guy suing them for
stealing his ideas, claiming he told them about something
critical when he visited.
--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.
Article: 50883Theron Hicks wrote: > > Hello, > I have an EMI noise problem with a cooling fan on an FPGA based system. > As a result, I am considering using a thermostat to control my cooling fans > in my system. I would like to attach the thermostat directly to the worst > case element on the board. To do so I need to decide what the likely > maximum allowable case temperature is. I am using a Spartan2E > XC2S50E-7TQ144C. I believe that the part is dissipating about a watt > although I haven't measured this yet. When I look at XAPP415 I see that > they list a maximum Theta J-A of 57.6 C/W with a typical value of 33.5C/W. > They also list Theta J-C of 5.5 W/C (typical). The first question is, "What > are the assumtions about heatsinking through the ground plane in the PCB for > theta J/C ?" The second question is can I use the 5.5 number to calculate > the temperature setting for my thermostat? Thus the maximum junction > temperature is 85C and the part dissapates 1 watt for a J/C temperature rise > of 5.5C. Thus the temperature of the thermostat could be set at say 79.5C. > For safety, I could use a 65C thermostat. The intent of all this is to > allow the customer to run the part in a low noise condition if the > environment is cool enough, but yet protect the system from overheating. > > As I think about it turning the fan on will generate a nasty EMI glitch > that would corrupt the user's measurements. Perhaps, I should provide any > idiot light/beeper that would tell the user to turn on the fan. Still, how > do I make the determination as to what the allowable case temperature should > be. > > By the way, the system is a low noise pulse width modulated anemometer > which is intended to be used in the field (i.e. in the sun on the salt flats > in Utah.) > > Thanks, > Theron Hicks If you measure the case temp via contact, then you only need to consider the Theta J-C number. This number makes no assumptions about the rest of the cooling system since it is independant of that. The Theta J-A number does make assumptions about how the case is cooled by the ambient. This should be spec'd in terms of the air flow and the design of the PC board the chip is on. As to the EMI, if the radiated frequency of concern is high such as the FCC requirements for commercial or residential equiptment, then you should be able to isolate the fan from the rest of the case with an enclosure. The air can move through the holes while the EM field does not. Your design may be too sensitive since this attenuates the EMI, but does not eliminate it. If the EMI is being conducted, then you certainly can remove that using chokes and capacitors. Should I assume that you have already explored techniques to reduce the EMI? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50884
Ray Andraka wrote: > > I've done that on many designs. The weak pullups are enough as long as the > memory is located close to the FPGA. Where I have an influence, I recommend > pullups on the control signals so that reconfiguration won't upset the > contents of the RAM. It is very useful to have the capability to reconfigure > without corrupting RAM contents (see my paper on the radar environment > simulator for examples of this, available at no charge on my website). My understanding is that with FPGAs and other chips that have weak internal pullups on the IO pins, they are only for assuring the state of an unconnected input and are not guaranteed to hold an external trace an pins to a known value when not driven. I am pretty sure I have read this warning in Xilinx literature somewhere. I *always* use external pullups/downs if I need to assure the state of a signal before configuration. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50885
I'll second that, only make it so for all the tools, not just amplify. Need to
have a switch that keeps _any_ timing constraints from being written into the
.ncf.
Phil Hays wrote:
>
>
> While I've got your ear, I'd like to ask again that the next revision of
> Amplify have some way to allow the period to NOT be forward annotated,
> other than not writing the design.ncf file. Or to write it out and then
> running a script to wack the period specification out during the build
> script, which is what I'm going to be doing.
>
> --
> Phil Hays
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50886
Exactly, that is why I went on to state where I have influence... I've been
stuck with 3rd party boards without them though that didn't have the pull-ups.
With 4K parts, the pull ups were strong enough to ensure a high level in all but
the most severe emi environments if the trace was short and lightly loaded. Newer
parts have less margin I think.
rickman wrote:
> Ray Andraka wrote:
> >
> > I've done that on many designs. The weak pullups are enough as long as the
> > memory is located close to the FPGA. Where I have an influence, I recommend
> > pullups on the control signals so that reconfiguration won't upset the
> > contents of the RAM. It is very useful to have the capability to reconfigure
> > without corrupting RAM contents (see my paper on the radar environment
> > simulator for examples of this, available at no charge on my website).
>
> My understanding is that with FPGAs and other chips that have weak
> internal pullups on the IO pins, they are only for assuring the state of
> an unconnected input and are not guaranteed to hold an external trace an
> pins to a known value when not driven. I am pretty sure I have read
> this warning in Xilinx literature somewhere. I *always* use external
> pullups/downs if I need to assure the state of a signal before
> configuration.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50887Thanks, the local altera repesentative proposed the same. There is some script code to be executed and it assumes the code & data is available. Which I forgot to mention is not. It is planned to shift the data over a serial line or USB. That is what the rbf file is for. Unfortunately the rbf appears not to be suited for the configuration devices. The local controller, an AVR is having in the order of 500bytes RAM, but only say 32 bytes available for the programming of the ACEX. It appears Altera mucked it up. Many different choices, meagre documentation about it and some of them incompatible with config devices. I have the configuration of Fig29 from the year 2000 AN116, and it appears I'll have to give decoding the JTAG Byteblaster stream a day or so. Rene Chris wrote: > Hi, > > Try to use the jam-player. The source code and application notes for > 80C51 are available for free on the Altera website. > > I done it with the Fujitsu controllers and it's fairly easy to do. > > Chris > > > Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in message news:<3E009F1E.5070706@dplanet.ch>... > >>I have an ACEX1k30 together with an EPC2 in JTAG multichain >>configuration. The pair is prgrammeable with the Byteblaster >>adapter, plus the relevant pins TMS, TDI, TDO and TCK of the >>adapter are connected to a microcontroller (AVR), tristated while >>not used. This to keep the normal way of programming. >> >>Before decoding the Byteblaster stream, I went to have a look >>at the various application notes. To little avail. >>They were AN116, AN111, AN100, AN88, AN95 >> >>Since the *.pof and the *.sof appear to require interpretation >>by MaxPlus2 or Quartus2, the preferred format would be *.rbf >>it appears. But is the created rbf sufficient for the ACEX as >>well as for the configuration flash ? >>Since *.pof and *.sof are not identical, I assume I require >>two different files too. >> >>I tend to think the subject is far simpler than I now look at. >> >>Any hints ?Article: 50888
The sad thing is the v3.3 and earlier routers could be depended upon to get a good
route given a good placement, so floorplanning alone more or less guaranteed
repeatable performance. The new router is lazy, and there is no way to make it do
as good a job as the old one did. For that reason, we are still using the v3.3
tools for the devices supported by those tools (with the updated timing files
which you need to beg your FAE for, but that's another story). I'd gladly accept
a longer place and route time to get the results we used to get, even if it means
setting a switch somewhere to get it.
BTW, this is probably one of the more convincing arguments for going to a
hierarchical place and route. The flattening of the design done by the current
tools creates a more and more difficult routing problem as the parts get more
routing resources. Hierarchical place and route lets you do a divide and conquer
strategy that is not really viable with a flattened design, not to mention the
ability to have repeatable performance on reusable macros .
Phil Hays wrote:
> > better. The v4.1 and later tools router is lazy, so you will only beat your
> > constraint by a couple hundred ps in many cases. If you look at the
> > resulting routing, you might be appalled at what the router has done.
> > Unfortunately there is no easy fix other than setting the constraints
> > higher, and even then the resulting route is quite sloppily done.
>
> "Might be appalled"?? Sir, you jest! Try: "Will be appalled and
> amazed". And did I mention appalled?
>
> I
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50889Hello ! I am a newbie to CPLDs and i have looked at different devices from Altera, Xilinx and Lattice. All companies say, their devices are in system programmable. They all offer some kind of ISP download cable for this. Well, here is my question: I am a bit confused about JTAG download cables. I had a look at Alteras Byteblaster Cable..... Its completely different from the Xilinx download cable schematics. And i bet its also different from a Lattice JTAG cable. Can you please help me in understanding the difference between the cables of the 3 companies. Can i use a Altera ByteBlaster cable to program a Xilinx or Lattice device. Is there a standard cable to programm all of them ? If yes, can you please tell me where to find the schematics. TIA TigerMole -----------== Posted via Newsfeed.Com - Uncensored Usenet News ==---------- http://www.newsfeed.com The #1 Newsgroup Service in the World! -----= Over 100,000 Newsgroups - Unlimited Fast Downloads - 19 Servers =-----Article: 50890
Ray Andraka wrote: > > The sad thing is the v3.3 and earlier routers could be depended upon to get a good > route given a good placement, so floorplanning alone more or less guaranteed > repeatable performance. The new router is lazy, and there is no way to make it do > as good a job as the old one did. For that reason, we are still using the v3.3 > tools for the devices supported by those tools (with the updated timing files > which you need to beg your FAE for, but that's another story). I'd gladly accept > a longer place and route time to get the results we used to get, even if it means > setting a switch somewhere to get it. That might be optimistic, but certainly there is an argument for not LOOSING operational functionality. I can see that in the rush for 'timing driven routing' that the routers get slower run times, and become sloppy/lazy in placement - and so what looked like a good idea, can then require the user to generate a ream of timing specs, and having to be VERY fussy about these numbers. With 'too much slack' in the design, you can also see that different passes could give different timing results : both can be under Timing MAX, but one may work, and one may not. Of course, one can argue the timing MAX was then wrong, but how many systems have truly accurate system-wide specs on all timing values ? ( and are the timing files for FPGAs always 100.00% without errors ? ) - more commonly, you don't know what matters, until it fails somewhere.. Sounds like two prongs are needed : a) Timing Driven Routing : Timing first, placement secondary/reported. and b) Placement Steered Routing : Placement first, timing secondary/reported. a) is more novice / big-green-button friendly, and b) is more version-control, and design-stability as well as design-optimise and speed friendly. and 'good tools', would allow ready-movement between a) and b). It is Xmas, after all :) - jgArticle: 50891
Hello,
This is not FPGA's problem. but I couldn't discover at the CPLD(software).
so please tell for this group.
now I think that altera's chip used to will make a small computer.
but I couldn't understand these plan what into will be used software,
max+plus2's setting up in the windows 98 second edition. I am
software's licensing setting is probably okey. but my computer's
global variable??(japanese call kankyo-hensu) isn't understood.
I don't know how to set up global variable.
I know about windows XP and 2000's setting up because my buying
magazine wrote. but windows 98 second edition and windows 98
is not written this magazine. so please teach me global variable
in windows 98 second edition using and who altera's max+plus2
using user you. please teach me setting up global variable...or
Would you teach me these informaiton knew user.....sorry
not well my english.
Thank you very much.
I would do my best.
Toshihiro Yazawa
Article: 50892"TigerMole" <Mole@huegel.de> wrote in message news:7gp90vcbm6merkl2haatq9l25jnpf4d0pi@4ax.com... > > Hello ! > > I am a newbie to CPLDs and i have looked at different devices from > Altera, Xilinx and Lattice. All companies say, their devices are in > system programmable. They all offer some kind of ISP download cable > for this. > > Well, here is my question: I am a bit confused about JTAG download > cables. I had a look at Alteras Byteblaster Cable..... Its completely > different from the Xilinx download cable schematics. And i bet its > also different from a Lattice JTAG cable. > > Can you please help me in understanding the difference between > the cables of the 3 companies. Can i use a Altera ByteBlaster > cable to program a Xilinx or Lattice device. > > Is there a standard cable to programm all of them ? If yes, can you > please tell me where to find the schematics. No, they all require different interfaces. The schematics for all three are available on the relevant web sites. I've designed PCBs for the Altera and Xilinx interfaces if you want to build your own. The Altera one is on my web site. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 50893
Hi,
I generated a verilog module of lpm_ram_dp using Quartus
megafunction wizard.
module dpmem (
data,
wraddress,
rdaddress,
wren,
rden,
wrclock,
rdclock,
q);
input [31:0] data;
input [4:0] wraddress;
input [4:0] rdaddress;
input wren;
input rden;
input wrclock;
input rdclock;
output [31:0] q;
wire [31:0] sub_wire0;
wire [31:0] q = sub_wire0[31:0];
lpm_ram_dp lpm_ram_dp_component (
.rdclock (rdclock),
.wren (wren),
.wrclock (wrclock),
.rden (rden),
.data (data),
.rdaddress (rdaddress),
.wraddress (wraddress),
.q (sub_wire0));
defparam
lpm_ram_dp_component.lpm_width = 32,
lpm_ram_dp_component.lpm_widthad = 5,
lpm_ram_dp_component.lpm_indata = "REGISTERED",
lpm_ram_dp_component.lpm_wraddress_control
= "REGISTERED",
lpm_ram_dp_component.lpm_rdaddress_control
= "REGISTERED",
lpm_ram_dp_component.lpm_outdata = "REGISTERED",
lpm_ram_dp_component.lpm_hint = "USE_EAB=ON";
endmodule
I am trying to synthesize it using altera Leonardo spectrum but I
get error message indicating that this module is not a defined
module or gate in a library knowing that I loaded Apex library from
Leonardo.
This problem occured also when I try to make a instance of this
module in my design which is the most important for me.
I tried it using VHDL and it went OK but I had to change the
instance name in the resulted EDF file to compile it in Quartus.
do you have any suggestion to this problem?
pls reply to my email (jamilkhatib@haridy.com) if it is possible
Thanks in advance
Jamil Khatib
Article: 50894
"Theron Hicks (Terry)" <hicksthe@egr.msu.edu> wrote:
> By the way, do you folks over there have Digikey available. While they
> are sometimes a little more expensive than some of the competition they do
> sell small quantities of surface mount parts. I suspect that Farnell will
> do so as well. Here in the USA, they are Newark and I know that Newark
> does so. In fact, Newark sometimes gets small quantities of Farnell parts
> for me when Newark's US warehouse is out of stock.
Farnell and RS do - but not as wide a range as Digikey or Newark. At least
often Digikey/Newark bring up things on findchips.com after not being able
to find them with Farnell/RS. If only there was a European version of
findchips.com. Many of the distributors are still in 'ring them up, spend
half an hour telling them about your projected sales and then maybe they'll
quote you a price after you've opened an account' mode.
Case in point: findchips.com shows the CS8900 at $7.69 from Newark, but
Farnell don't stock it. I got some samples from Unique Memec, but these had
to be sent from Cirrus in the US - whilst Sequoia would only sell me them
for 10ukp each with an MOQ of 6. If only Newark shipped internationally (I
don't count a minimum order of $250 as sensible international shipping).
On the subject of surface mounting, I believe a number of people have had
success with a toaster oven[1] - see http://groups.yahoo.com/group/E-Z_Bake/
and http://www.pcbexpress.com/stencils/
Theo
[1] I don't think I've ever seen a toaster oven as depicted in the UK. This
may be naivete in domestic appliances on my part, but I once had a Baby
Belling which may do the same job (but no glass door). Possibly adaption of
an old oven, old microwave with integral grill or other heating element
retrofitted to an old microwave may do the trick. Reuse for food afterwards
is not recommended unless you like lead poisoning...
--
Theo Markettos theo@markettos.org.uk
Liphook, Hampshire, UK theom@chiark.greenend.org.uk
http://www.markettos.org.uk/
Article: 50895TigerMole wrote: > Hello ! > > I am a newbie to CPLDs and i have looked at different devices from > Altera, Xilinx and Lattice. All companies say, their devices are in > system programmable. They all offer some kind of ISP download cable > for this. > > Well, here is my question: I am a bit confused about JTAG download > cables. I had a look at Alteras Byteblaster Cable..... Its completely > different from the Xilinx download cable schematics. And i bet its > also different from a Lattice JTAG cable. > > Can you please help me in understanding the difference between > the cables of the 3 companies. Can i use a Altera ByteBlaster > cable to program a Xilinx or Lattice device. > > Is there a standard cable to programm all of them ? If yes, can you > please tell me where to find the schematics. > You also have to install a driver together with it. I wouldn't even attempt to use them for a different purpose than intended, meaning their respective devices. Schematics are to be found on their websites. The Altera one is under Application notes, ByteblasterMV. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 50896
While simulating a complete ASIC (~5 million gates) consisting of several individual blocks, is it possible to attempt a concurrent simulation (functional or timing) in a distributed environment with a pool of dedicated PCs simulating the individual blocks with inter-block communication handled by PLI/FLI wrappers in Modelsim which take care of "forcing" the signals driven by other blocks into this block? Each individual PC needs to load only a small part of the whole design and wait for new updates from interacting blocks. Pakcets keep travelling to and fro between the PCs progressing the simulation. It may also be possible to avoid IDLE time by allowing the individual PCs to assume a certain set of inpout values and start simulating, if later an update arrives that invalidates this assumption, all subsequent operatins are rerun with these new inoouts and the corresponding outputs generated invalidated. This will definitely require mor thinking than can fit in a single email, but how is the idea for starters?...and has it been tried before ? It would'nt be wrong to mention that attempting such a simulation on a single PC would be too tedious and time consuming. regards, Nachiket Kapre. Design Engineer. Paxonet Communication Inc.Article: 50897
I've made an even simpler solution than in AN 116. A MAX7032 is enough to program ACEX 1Kxx in PPA mode. You can find the details (schematic and VHDL) at http://www.jopdesign.com/download.html Martin "Greg Steinke" <gregs@altera.com> schrieb im Newsbeitrag news:5c1de958.0212201540.384ce808@posting.google.com... > Mr. Giaccaglini, > The Altera web site has some information for what you want to do. The > page http://www.altera.com/literature/lit-acx.html contains the > following: > - AN 116: Configuring SRAM-Based LUT Devices. This documents the > configuration process and how to set up the board. It also has an > example design for a MAX device which reads from a Flash eprom and > sends the configuration data to the FPGA. > - "Design File for Configuring FLEX 10K & FLEX 6000". This is VHDL > code for a MAX device to implement the design. The configuration > process is identical for ACEX 1K, so you can use this file. > > Sincerely, > Greg Steinke > gregs@altera.com > > > "Giaccaglini Giorgio" <g.giaccaglini@libero.it> wrote in message news:<QerM9.32988$TC5.1006092@twister1.libero.it>... > > I want to programme an ACEX1K (where I put a NIOS CPU) using a simple CPLD > > (as controller) and a Flash Eprom in which I have the FPGA configuration and > > the application. > > > > Do you have a VHDL source for the controller that download the FPGA? > > > > Thank you very much for your help. > > > > Giorgio Giaccaglini > > Aethra Telecommunication > > Italy > > +39 02 2189877 > > g.giaccaglini@aethra.it > > www.aethra.itArticle: 50898
Actually Glen, the device I am building _is_ a hot wire anemometer. The control system is Pulse Width Modulated as opposed to the conventional Whetstone Bridge based constant temperature anemometer. By using PWM we can get a better transfer function and use a simple counter instead of an A/D converter. Also, the system has a few other advantages. (See United States Patent #03603147.) The real problem is that the fan ENI shows up in the Spectral Plot for the recovered data from the anemometer. I am looking at several options including grounding the fan cases, filtering their input lines, and shielding the fan cases. I am currently using the best specified fans for EMI that I can find. The fans are 119mm square by 35mm high (however height is somewhat negotiable). I have even considered using a remote fan and ducting the coolant flow into the system via some large diameter hose. Thanks, Theron glen herrmannsfeldt wrote: > "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message > news:au01e8$17oj$1@msunews.cl.msu.edu... > > (snip) > > As I think about it turning the fan on will generate a nasty EMI > glitch > > that would corrupt the user's measurements. Perhaps, I should provide any > > idiot light/beeper that would tell the user to turn on the fan. Still, > how > > do I make the determination as to what the allowable case temperature > should > > be. > > > > By the way, the system is a low noise pulse width modulated anemometer > > which is intended to be used in the field (i.e. in the sun on the salt > flats > > in Utah.) > > How about a hot-wire anemometer? > > Do you have to worry about the effect of the fan on the > anemometer itself? > > -- glenArticle: 50899
Wrong patent number (5,654,507 is correct) "Theron Hicks (Terry)" wrote: > Actually Glen, the device I am building _is_ a hot wire anemometer. The control > system is Pulse Width Modulated as opposed to the conventional Whetstone Bridge > based constant temperature anemometer. By using PWM we can get a better > transfer function and use a simple counter instead of an A/D converter. Also, > the system has a few other advantages. (See United States Patent #03603147.) > The real problem is that the fan ENI shows up in the Spectral Plot for the > recovered data from the anemometer. I am looking at several options including > grounding the fan cases, filtering their input lines, and shielding the fan > cases. I am currently using the best specified fans for EMI that I can find. > The fans are 119mm square by 35mm high (however height is somewhat > negotiable). I have even considered using a remote fan and ducting the coolant > flow into the system via some large diameter hose. > > Thanks, > Theron > > glen herrmannsfeldt wrote: > > > "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message > > news:au01e8$17oj$1@msunews.cl.msu.edu... > > > > (snip) > > > As I think about it turning the fan on will generate a nasty EMI > > glitch > > > that would corrupt the user's measurements. Perhaps, I should provide any > > > idiot light/beeper that would tell the user to turn on the fan. Still, > > how > > > do I make the determination as to what the allowable case temperature > > should > > > be. > > > > > > By the way, the system is a low noise pulse width modulated anemometer > > > which is intended to be used in the field (i.e. in the sun on the salt > > flats > > > in Utah.) > > > > How about a hot-wire anemometer? > > > > Do you have to worry about the effect of the fan on the > > anemometer itself? > > > > -- glen
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