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"Peter Young" <Peter.Young@AMIRIX.com> wrote in message news:3CC5B113.C4AE7396@AMIRIX.com... > David Frith wrote: > > Hello all > > > > I've just loaded on ISE 4.2i and the first design I ran through gives me an > > error at ngdbuild. This is with exactly the same input files as 4.1i which > > works fine. > ... > > ERROR:NgdBuild:669 - A parsing error has occurred at line 0 while reading > > lsb_opif.ucf. The value is . > > ERROR:NgdBuild:31 - Errors found while parsing .ucf file "lsb_opif.ucf". > > Please > > check for syntax errors in the UCF file. For more information on legal UCF > > constraints, please see the Constraints Guide for more information on this > > attribute. > > We encountered an error like this on one of our machines as we migrated > from 4.1i to 4.2i. It eventually went away and we weren't 100% sure > why, but what we suspected was that the environment variables got > updated to point to 4.2i, but the path on the PC or the desktop shortcut > was still pointing to the old 4.1i installation. Double check your > System variables, path, and shortcuts to make sure everything points to > 4.2i. I had already checked the path and system variables but this time I also checked the shortcuts and found that the shortcut on the desktop that I used for Design Manager was still pointing to the 4.1i install location. When I updated this to the 4.2i install location it worked! Thank-you very much for pointing me in the right direction. (It's a pity that Xilinx never got back to me with this solution.) What's more, if I had used the Design Manager shortcut in the start menu, it would have worked in the first instance. I'll put that one down to experience and get on with evaluating 4.2i now. Again, thanks Pete. David Frith, Principal Engineer, Fujifilm Electronic Imaging, Hemel Hempstead, Herts, HP2 7RH. UK. Email: david.frith@ffei.co.uk Tel: (+44)(0)1442 343083Article: 42451
Ryan,
Here is the answer from the expert:
"Hi Austin,
The -r switch is currently a hidden switch, but it will be visible in the next major release. The switch will make bitgen read in an existing bitstream, and then when the bitstream for the new design is created, only the frames that
are different between the two bitstreams will be written.
The -r switch takes a bitstream as an argument. An example command line would be:
$ bitgen -w -r old.bit new.ncd
The -r switch is useful if you have a limited number of possible reconfigurations."
Austin
Ryan Fong wrote:
> Is it possible to generate partial bitstreams using the Xilinx ISE 4.2i tools, without using the Modular Design tools? I am interested in run-time partial reconfiguration to change areas of an FPGA while keeping others areas unchanged.
>
> Thanks.
Article: 42452I don't even know if I'm in the right news group or not. I haven't messed with PAL's/GAL's/FPGA's at all...yet. But I think I have a need for them now. Basically, I've got a project where I've got to move data around very quickly, from a USB port to a hard drive. Right now, my MCU (PIC16F877) strobes a USB interface chip for data (high byte), moves that data to a latch, strobes the USB chip again, hold that data on the lines (low byte), then strobe the drive's WRite lines, then releases everything, pauses for one cycle and repeats the process 256 times (one sector at a time dontcha know). So, that's all fine and dandy, it works and it works well, but it's slow, even with a 20Mhz clock rate, I can only transfer about 40K/second using nice tight code that doesn't do anything else inside the loops except move data around. I want faster!!! (who doesn't?) So, I'm wondering if some sort of PAL/GAL/FPGA chip might be the correct way to go to handle this at nice fast speeds. A chip of this type would have to have a 8 bit counter (to keep a running count of 256 words), 2 8-bit latches (one for each low and high byte), 6 output signals to control the drive (A0-A2, RD*, WR*, ChipSelect) and a few pins for CPU control and status (BuSY/ReaDY status, a CPU strobed START pin, a line to the USB chip for ReaD-ReaDY and ReaD-Byte). The CPU would pulse the START pin, which would start the FPGA (or whatever) chip doing it's thing. The FPGA (or whatever) would pull the BuSY/ReaDY low (or high, whatever), then would starting counting each word transferred, it would check the USB pin for see if it has data available, if it is, it would pull the RD low and strobe in a byte, shift that byte up to the upper byte latch, re-check the USB pin for more data, strobe that data and hold it on the data lines, then strobe the hard drives control lines accordingly. Wash-Lather-Rinse-Repeat 256 times for each word until a complete sector has been written. And for this part of the learning curve, just ignore any error checking for now. I figure at least a 44 pin PLCC or something like that, I don't know. Am I on the right track by looking at these types of chips? Any suggestions for companies/types of chips/software/websites/pdf files for reading up on them? -- Jeremy D. Grotte www.geocities.com/skimask87Article: 42453
Hello all, We are having multiple problems with the 256-point FFT core that comes with the Xilinx 4.1 ISE Core Generator. The 16-point FFT works fine, but the 256-point FFT fails in both the single- and triple-memory-space configurations. We've updated the Core Generator, and installed the patch. Our input is a simple rect function, but the output in no way resembles a sinc. During the intermediate steps of the FFT, the core seems to be coming up with strange values that it writes to memory, and the error propagates to the output. Also, neither configuration will implement properly onto our million-gate Virtex II. The place and route function claims that it can't route most of the core, even though we have more than enough slices available. Any help would be greatly appreciated. Thanks! MattArticle: 42454
Hi, I am trying to design a high precision (30 bit) frequency synthesiser inside a Spartan II. Of course, normal way to do this is with a charge pump, voltage controlled oscillator and a phase lock loop. Can anyone point me to some good references? I have a very high precision 5Mhz which is generated from a hydrogen maser and will be used as the input clock signal. thanks adrianArticle: 42455
Noddy, Use a DDFS (direct digital frequency Synthesizer). Austin Noddy wrote: > Hi, > > I am trying to design a high precision (30 bit) frequency synthesiser inside > a Spartan II. Of course, normal way to do this is with a charge pump, > voltage controlled oscillator and a phase lock loop. > > Can anyone point me to some good references? I have a very high precision > 5Mhz which is generated from a hydrogen maser and will be used as the input > clock signal. > > thanks > adrianArticle: 42456
To all gurus, Hope there is someone that can understand this I am currently using a memory block in a FPGA to change the frequency of my operation clock. i change the address and content of the memory give me the value that i feed to a counter that then change my freq. Everything run at real time and the freq is limited to the content of the memory. I wish to change the content of the memory without needing to stop the freq., reload a new memory content.... Therefore to be able to do variable freq. i need to replace the memory or look-up table methods. My limitation 1) i have to use the address method to change my freq. 2) the time delay between the address to memory content changing is about 6nsec (or equivalent 1 gate propagation delay) Many thanks to any suggestion Regards FKArticle: 42457
"Tim" wrote: > > Dorothy Parker isn't always quoted in full, but as the lady said: > "you cannot be too thin or too rich, or have too much RAM" > Another news item of hers: "Compilers make multiple passes on HDLs using classes." Or something like that - she was definitely down on SystemC. http://www.english.uiuc.edu/maps/poets/m_r/parker/additional.htm Paul.Butler@ni.comArticle: 42458
Steffen, Answer Record 12502 seems very similar to your problem, so it may help: http://support.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=12502 I found it by going to support.xilinx.com and searching for: "Chipviewer hang" Regards, Kamal Steffen Thieringer wrote: > Hello Newsgroup, > I have a problem with Chip Viewer as a part of of Xilinx ISE 4.2. > Program is coming up, but if I want to load a design the programs hangs up. > The 'Reading Data' keeps forever up, I have to kill the task. > Due to the fact this is a Java based program, the system environment > (java-plugins) > haven't been set the right way?! > I have installed Java 1.4 from Sun. > > Thank you, and regards > Steffen > >Article: 42459
"FK" <fk.chong@ntlworld.com> schrieb im Newsbeitrag news:96f26d85.0204240710.598733f9@posting.google.com... > Many thanks to any suggestion A DDS may be the thing you are looking for. -- MfG FalkArticle: 42460
"Jeremy D. Grotte" <jdgrotte@ndak.net> schrieb im Newsbeitrag news:ucdh9nbai2bg87@corp.supernews.com... > now, my MCU (PIC16F877) strobes a USB interface chip for > data (high byte), moves that data to a latch, strobes the > USB chip again, hold that data on the lines (low byte), then > strobe the drive's WRite lines, then releases everything, > pauses for one cycle and repeats the process 256 times (one > sector at a time dontcha know). So, that's all fine and > dandy, it works and it works well, but it's slow, even with > a 20Mhz clock rate, I can only transfer about 40K/second > using nice tight code that doesn't do anything else inside > the loops except move data around. I want faster!!! (who > doesn't?) > So, I'm wondering if some sort of PAL/GAL/FPGA chip might be > the correct way to go to handle this at nice fast speeds. It defenitely is. All you need is a fancy CPLD, go for the Coolrunners from Xilinx, but also other vendors will do. All you need is a small state-machine and some registers. Should fit into 32/36 macrocell CPLD, the come mostly only in QFP packages (0.65/ 0.5 mm pin pitch) Transfering 20 Mbyte/s with a 8 bit bus is easy. -- MfG FalkArticle: 42461
"Russell" <rjshaw@iprimus.com.au> schrieb im Newsbeitrag news:3CC6AD00.D92BD4FF@iprimus.com.au... > Hi, > > I made a JTAG programmer to connect a spartan2 > to a pc. Do the pins nPROGRAM, DONE, or nINIT > need pullups when configuring a single device? I think you mix something up. nPROGRAM, DONE, and nINIT anr not used for configuration via JTAG. Only TDO/TDI/TCK/TMS. BUT you better connect a pullup (4k7 is ok) to nPROGRAM, since this is vital pin for you FPGA ;-) nPROGRAM, DONE, or nINITArticle: 42462
Hi all,
i'm writing my first vhdl sources and in my simple
project happens something wrong:
entity parallel is
Port (
...
p_select : out std_logic;
p_init_n : in std_logic;
..
p_ack_n : out std_logic;
p_strobe_n : in std_logic;
-- Clock
clock : in std_logic;
.....
);
end parallel;
Into architecture section i have:
-- LEDs
d4 <= p_init_n;
d5 <= p_selectin_n;
d6 <= p_strobe_n;
process(p_init_n)
begin
p_busy <= '0';
if(p_init_n'event and p_init_n='0') then
p_ack_n <= '1';
p_busy <= '0';
end if;
end process;
process(p_strobe_n)
begin
if(p_strobe_n'event and p_strobe_n='0') then
byte <= p_data;
end if;
end process;
During Mapping i have following error:
ERROR:MapLib:93 - Illegal LOC on symbol "p_strobe_n" (pad signal=p_strobe_n) or
BUFGP symbol "p_strobe_n_BUFGP" (output signal=d6_OBUF), IPAD-IBUFG should
only be LOCed to GCLKIOB site.
I don't understand why p_strobe_n signal is considerated
as a clock (but it is NOT a clock) and p_init_n is OK.
They have similar code .....
PS: i use Xilinx WebPack 4.2
Thanks, regards
--
Stefano Mora
email: stefano.mora@*libero.it
(remove *)
Article: 42463
Hi all,
I'm an Electrical Engineering Student enterring my final year and i
have to choose a project to do. I want to build and design a small and
simple computer system, with a fpga as its cpu (designed by me) -hopefully
getting to the stage where i can get it to output to a VGA device.
I'll probably use the MIPS instruction architecture for my device.
Bear in mind that i'm new to this whole thing but i do have a
background in digital electronics (design and schematics) VHDL and computer
systems. Would this project be too much for me to handle at this stage? I
think i could handle it, but i dont want to find out later on down the road
that its a whole load of trouble. Cheers, Stephen Henry
Article: 42464Michael wrote: > > For a long time I've found CPU design interesting, but never had the > resources to go out and test any of my ideas.(strange memories of > arguing with my friends about CPU architecture at sushi restaurants > come to mind) Recently, I've been looking at FPGA boards, and would > like input. I'm a hobbyist(highschool student) and therefore have very > little funds. Why not make your own board. For a simple CPU design you don't need a high speed board. Take a look at: ftp://137.193.64.130/pub/xproz/mainb.gif ftp://137.193.64.130/pub/xproz/system.gifArticle: 42465
Is there a PQ208 package available for Virtex? Thanks.Article: 42466
Hello all, I made a lot of posts for Virtex DLL but I am in a difficult position, I hope its OK for the rest of the group. This post is pretty large and I am sorry for that... I use a Virtex XCV812EM speed grade 6, I make use of a CLKDLLHF to divide an external 155MHz clock by 2 ( I use both clocks for my logic). I make correct use of the DLL (the external clock uses a LVDS_DLL pin to reach the CLKIN pin of the DLL, the DLL feedback is the output of a BUFG whose input is CLK0, the feedback signal also uses an OBUF to be driven off chip, CLKDV uses a BUFG also for its proper distibution inside the FPGA) , but during timing (post PAR) simulation in modelsim I get the following timing. CLK155_P : the clock I receive from outside world CLK155_int : the 155 MHz clock used internal (output of the BUFG whose input is the CLK0 from DLL) CLK1/2 : the divided clock (output of the BUFG whose input is the clkdv from DLL) CLK155_OUT : the internal clock driven off chip Using the post PAR vhd simulation and SDF file, I get : CLK155_int's rising edge has 4745 ps delay in relation to clk155_P's rising edge...(the same for CLK155_OUT) CLK1/2's rising edge has 1045 ps delay in relation to clk155_P's rising edge These simulation results seemed strange to me because I was waiting both clocks' rising edges to be alligned with external clock's rising edge, so I look in www.xilinx.com for help. I found xilinx answer 11372 "The output signals of the CLKDLL and DCM do not appear to be aligned with each other in timing (post-PAR) simulation. For example, the rising edge of CLK0 is not synchronized with the rising edge of CLK2X or CLKDV (in "Divide by 2" mode). Why is this happening? " And says : "This problem is due to the way in which the simulators annotate the timing delays passed down by the SDF file. Depending on the input Clock frequency and the delays in the device, the signals may or may not appear to be properly aligned. In order to verify that the CLKDLL/DCM model is functionally correct, the simulation can be run for a short period of time without the SDF delays annotated; this will show whether the signals have lined up properly" So I didnt use the SDF file and the simulation results changed to : CLK155_int's rising edge has 0 ps delay in relation to clk155_P's rising edge... CLK1/2's rising edge has 3100 ps delay in relation to clk155_P's rising edge Also in www.xilinx.com I found answer 11067 General Description: "When I run a timing simulation with ModelSim, the clocks coming out of the DCM and CLKDLL models do not appear to be de-skewed. If the DCM and CLKDLL should line up the internal clock with the input clock, why is this happening? " And says : "....the ModelSim Wave window will still display a small amount of clock skew between the clocks. The simulation is correct, but the waveforms are not shown as expected. The reason for this apparent skew is the way that the delays in the SDF are handled by ModelSim" Question : the simulation is correct but waveforms are not shown as expected? How can this happen? The article finishes with this note : "The SDF annotates the CLOCK PORT delay on the X_FF components; however, the simulator displays the clock signal before taking this delay into account. If this CLOCK PORT delay on the X_FF is added to the internal clock signal, it will line up with the input port clock (within the device specifications in the data sheet) in the waveform viewer. Again, the simulation is functionally correct. This is only an issue with the way in which the waveforms are displayed in ModelSim. If you require the waveforms to be displayed correctly, there is a temporary way to work around this in the Xilinx ISE 4 software: Add an environment variable called "NLW_ADD_ROUTEDLY_BUFFER" and set its value to 1. This will result in an extra buffer being added before every clock input port. The delay that was previously annotated on the input port of the register will now be moved to this extra buffer. When you view the clock in the register, it will now be properly aligned with the input clock. However, this will increase netlist size, increase simulator memory usage, and slow down simulation. As a result, we do not recommended the use of the environment variable" I add this variable and my simulation results (with the SDF file) changed to : CLK155_int's rising edge has 4745 ps delay in relation to clk155_P's rising edge...(the same for CLK155_OUT) <--same waveform as without the variable CLK1/2's rising edge has 1545 ps delay in relation to clk155_P's rising edge CONLUSION (at last!!!! :)) ) From the above simulation results which is the most precise to "real life"? If none of the above is correct how must I consider the phase between the clocks? I wish somebody read this LARGE post and is willing to help me! Best Regards, HarrisArticle: 42467
Hi Hiro The best way to have init to be taken is from UCF the syntax is a bit different , check UCF syntax attributes does not work as it is synthetizer dependant and as far I have seen there is no problem ( except node name and language syntax ) with UCF jacky -- Use our news server 'news.foorum.com' from anywhere. More details at: http://nnrpinfo.go.foorum.com/Article: 42468
In article <meBx8.5640$W9.122542@twister2.libero.it>, stefano.mora@antispam.libero.it says... > Hi all, > i'm writing my first vhdl sources and in my simple > project happens something wrong: > > entity parallel is > Port ( > ... > p_select : out std_logic; > p_init_n : in std_logic; > .. > p_ack_n : out std_logic; > p_strobe_n : in std_logic; > -- Clock > clock : in std_logic; > ..... > ); > end parallel; > > Into architecture section i have: > > -- LEDs > d4 <= p_init_n; > d5 <= p_selectin_n; > d6 <= p_strobe_n; > > process(p_init_n) > begin > p_busy <= '0'; > if(p_init_n'event and p_init_n='0') then > p_ack_n <= '1'; > p_busy <= '0'; > end if; > end process; > > process(p_strobe_n) > begin > if(p_strobe_n'event and p_strobe_n='0') then > byte <= p_data; > end if; > end process; > > During Mapping i have following error: > ERROR:MapLib:93 - Illegal LOC on symbol "p_strobe_n" (pad signal=p_strobe_n) or > BUFGP symbol "p_strobe_n_BUFGP" (output signal=d6_OBUF), IPAD-IBUFG should > only be LOCed to GCLKIOB site. > > I don't understand why p_strobe_n signal is considerated > as a clock (but it is NOT a clock) and p_init_n is OK. > They have similar code ..... It is indeed a clock. The second process statement forms a D-FlipFlop with p_strobe_n as the negative-active clock, p_data as the D input, and byte as the Q output. Remember, the synthesizer is matching your code to a template. That process has DFF template written all over it. BTW, what is your first process trying to do? It doesn't look too useful. p_ack_n will be set to '1' (from 'X') on the first falling edge of p_init_n, and live as a '1' forever onward. p_busy will go to '0' (from 'X') on the first edge of p_init_n. This might not be realizable, since you're using both edges of the clock to set it. Note that like your second process, this process also has a clock (p_init_n). ---- KeithArticle: 42469
Hi,
I've just fired up a board with a x2v3000 and some xc18v04's
just as a go-no-go test I a very very simple design something
like;
module test(clk,rst_b,test1,test2,test3);
input clk,rst_b;
output [15:0] test1;
output test2;
output test2;
reg [15:0] test_reg1;
reg test_reg2;
assign test1 = test_reg1;
assign test2 = test_reg2;
assign test3 = clk;
always@(posedge clk or negedge rst_b)
begin
if(!rst_b) test_reg1 <= 16'hABCD;
else test_reg1 <= 16'h0001;
end
always@(posedge clk or negedge rst_b)
begin
if(!rst_b) test_reg2 <= 1'b0;
else test_reg2 <= ~test_reg2;
end
endmodule
here's the mystery,
If I configure the FGPA directly with JTAG everything works as expected
clk on test3, clk/2 on test2, counting on test1
If I put the design in flash, test3 is the clk as expected, test2 is
the clk divided by two as expected, but test1 is 16'hFFFF unless I
hit reset then test1 is 16'hABCD
How can it almost work, anyone with an explanation ???
thanks,
-Lasse
--
// Lasse Langwadt Christensen
// Aalborg, Danmark
Article: 42470I believe a PQ240 package is available for Virtex. You should go with Spartan-II which has a PQ208 package. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Stéphane Guyetant wrote: > > Is there a PQ208 package available for Virtex? > Thanks.Article: 42471
"Pawe³ J. Rajda" wrote:
>
> I am making a small (XC2S30) project and have a few questions:
>
> 1. DLL's
> Is the usage of DLLs obligatory or not? I am shifting data to the
> Spartan
> synchronously with external 4,096MHz clock. Another clock in my
> project
> is about 11MHz. Do such clocks need DLLs?
I don't use Spartan-II's DLL in my design, so I am not too
familiar with it, but I read that the frequency entering a DLL has to be
at least 25MHz.
> 2. I/Os
> I have to interface to 5V devices. Which I/O standard should I use:
> LVTTL
> or PCI_33_5? In what they differs (both are 5V tolerant)? Only in
> current
> sink/source capabilities?
I don't think you should use PCI33_5 unless you are dealing with
5V PCI.
Use LVTTL instead, and I am told that it is automatically 5V tolerant.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 42472Pawel, Some answers, below. Austin "Pawe³ J. Rajda" wrote: > I am making a small (XC2S30) project and have a few questions: > > 1. DLL's > Is the usage of DLLs obligatory or not? I am shifting data to the > Spartan > synchronously with external 4,096MHz clock. Another clock in my > project > is about 11MHz. Do such clocks need DLLs? No. They do not. DLLs deskew clocks for high speed applications where even 100's of ps are important to keep track of. At 1 MHz, deskew is not an issue, as the clock period is 1000 ns! > > 2. I/Os > I have to interface to 5V devices. Which I/O standard should I use: > LVTTL > or PCI_33_5? In what they differs (both are 5V tolerant)? Only in > current > sink/source capabilities? Run IBIS simualtions to choose the best IO standard. > > 3. Configuration > I will use Master Serial mode. What is the Preconfiguration > Pull-ups option? > Should I turn it on or off? One can have the IOs pull up while configuring, or not (remain tristate). > > > -- > Regards, > Pawel J. Rajda >Article: 42473
Ya, this is the kind of thing that a CPLD would do nicely. It's not for the faint of heart though if you don't have a background in these parts or at least logic design. The CPLD could give you a once cycle per clock kind of speed. If you're looking for a place to start, you can go with either the free Xilinx Web Pack tools or Altera's free tools. Regards "Jeremy D. Grotte" <jdgrotte@ndak.net> wrote in message news:<ucdh9nbai2bg87@corp.supernews.com>... > I don't even know if I'm in the right news group or not. I > haven't messed with PAL's/GAL's/FPGA's at all...yet. But I > think I have a need for them now. > Basically, I've got a project where I've got to move data > around very quickly, from a USB port to a hard drive. Right > now, my MCU (PIC16F877) strobes a USB interface chip for > data (high byte), moves that data to a latch, strobes the > USB chip again, hold that data on the lines (low byte), then > strobe the drive's WRite lines, then releases everything, > pauses for one cycle and repeats the process 256 times (one > sector at a time dontcha know). So, that's all fine and > dandy, it works and it works well, but it's slow, even with > a 20Mhz clock rate, I can only transfer about 40K/second > using nice tight code that doesn't do anything else inside > the loops except move data around. I want faster!!! (who > doesn't?) > So, I'm wondering if some sort of PAL/GAL/FPGA chip might be > the correct way to go to handle this at nice fast speeds. > A chip of this type would have to have a 8 bit counter (to > keep a running count of 256 words), 2 8-bit latches (one for > each low and high byte), 6 output signals to control the > drive (A0-A2, RD*, WR*, ChipSelect) and a few pins for CPU > control and status (BuSY/ReaDY status, a CPU strobed START > pin, a line to the USB chip for ReaD-ReaDY and ReaD-Byte). > The CPU would pulse the START pin, which would start the > FPGA (or whatever) chip doing it's thing. The FPGA (or > whatever) would pull the BuSY/ReaDY low (or high, whatever), > then would starting counting each word transferred, it would > check the USB pin for see if it has data available, if it > is, it would pull the RD low and strobe in a byte, shift > that byte up to the upper byte latch, re-check the USB pin > for more data, strobe that data and hold it on the data > lines, then strobe the hard drives control lines > accordingly. Wash-Lather-Rinse-Repeat 256 times for each > word until a complete sector has been written. And for this > part of the learning curve, just ignore any error checking > for now. I figure at least a 44 pin PLCC or something like > that, I don't know. > > Am I on the right track by looking at these types of chips? > Any suggestions for companies/types of > chips/software/websites/pdf files for reading up on them?Article: 42474
Read below... Austin Lesea <austin.lesea@xilinx.com> wrote in message news:<3CC57702.2620F2DB@xilinx.com>... > Jay, > > How much RAM is enough? About 8Mbits are required. > Is the 405PPC core in Virtex II Pro fast enough (>300 MHz)? Its completely the wrong processor, besides, thats a hardwired ASIC macro on your FPGA die, so thats why it's reasonably fast. > How much random logic is required? About twice as much as your largest shipping part. And its way too slow for prime time. The part complexity was scaled to use the available gates/ram in the current semiconductor process technology. If we could have made it bigger at a reasonable yield, we would have, and taken the performance. > EasyPath will be there for Virtex II Pro. We are looking to the future, and answers to these > questions will help us decide future family members. More data points the better. Glad to help. > Thanks for your comments, > > Austin
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