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> Phasen : process (MSP_CLK, Befehl_Empfangen) > Begin > if (Befehl_Empfangen='0' and Empfangs_Buffer(3 downto 0)="0000") then > Zustand <= Zustand0; Speicherdummy(3 downto 0)<="0000"; > > elsif falling_edge(Befehl_Empfangen) then Also be aware that in at least some technologies (Xilinx), the place and route tool will not trace paths into asynchronous inputs during timing analysis. Depending on what all of this is meant to do, you might get unexpected results after it's implemented in real hardware (worse, they'll change depending on build). In the right conditions, some flops may be reset in a different clock period than others because of assymetric routing delays. This problem can be exacerbated by logic replication. Please correct me if I'm wrong, but I think that this design technique is extremely hazardous and should be avoided at all costs. I suggest that you try synchronous resets to avoid these problems.Article: 38451
Thanks again rickman,
Yss, I know, 'God' has little with human's flabbergastings. That's
just an expression, sorta "hit-and-miss' situation.
Anyways, I haven't seen any ability to add BSDL files to IAR's
IDE. That practically menas that MSP430 has to have a separate
JTAG connector, or even somehow 'multiplexed' let's just say
for now I would keep Xilinx and MSP430 chain separated.
Well, neither Xilinx's JTAG programmer nor IAR's downloader
doesn't have compatible connectors, so here I need some
brainstorming on how to use one connector with two different
JTAG tools.
So, for now I have two solutions:
1) To have separate chains (and to use both JTAG tools
independently) and separate JTAG connectors.
2) To chin-up both chips into one JTAG chain and use Xilinx
download tool with added MSP430 BSDL file.
(debugging MSP430 would be handled by simulator prior
to adding resulting binary file into downloader's list)
and testing both poppies as is, without having conveniance
of debugging MSP430 via JTAG.
> I am also concerned with the same JTAG compatibility problem with the
> C67 DSP. I will need to contact TI about that.
Right. I haven't use C67 so far, but logic tells me that you will
encounter similar problem - how _your_ downloader is going
to distinguish between separate chips in the chain (without BSDL)
and how your debugger is going to perform function cause
JTAG is a serial stream of data, right? How debugger is going
to know where to start and to end the stream (without having BSDL).
> Oh yeah, I also have to check with Xilinx since I will need to program
> the XCR3256 after the board is built.
Here you'll not have a 'serious' problem - Xilinx's downloader tool
have a nice GUI - you can click on icon of the chip, add the binary,
add additional chip(s) and even play around with timings (to some
extent). I love it.
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3C42921C.4727C00@yahoo.com...
> I don't think I would leave this "in God's hands". I would contact IAR
> and get the straight scoop. If they don't give you a way to include BDSL
> files for the other chips in the chain, I don't think it will work. If
> nothing else, it has to know how many chips are in the chain. I think
> there is a way to put each chip in a state where it looks like a single
> FF. This would be the simplest way for the IAR debugger to deal with the
> other chips.
>
> I only need the JTAG on the MSP430 for debugging of the code in
> development and I need something to let me program the MSP430 flash in
> production. They have a "boot monitor" that will work as a 9600 bps
> serial port which I may use. But they did not use the same pins as the
> actual serial port, so it will be a little tricky to get this going
> without using up too many pins on the MSP430. I am using every last IO
> pin.
>
> I am also concerned with the same JTAG compatibility problem with the
> C67 DSP. I will need to contact TI about that.
>
> Oh yeah, I also have to check with Xilinx since I will need to program
> the XCR3256 after the board is built.
>
> Too bad JTAG is not more widely supported across vendors. It always
> seems to have trouble when the chains are mixed. I just don't have the
> board space to have three separate JTAG connectors.
>
>
>
> DG_1 wrote:
> >
> > Thanks 'rickman'.
> > The only problem I 'foresee' is the fact that IAR Kickstart doesn't
> > have any capability of adding/editing BSDL files (or I missed
something).
> > Therefore, I don't see the way how to use debugging features
> > of IAR Kickstart when _more_ than one chip is in the same chain.
> > I guess, designers of IAR's tool-set didn't (intentionally?)
> > though-out that possibility. Also, I guess, from Xilinx's perspective,
> > having MSP430 in the same chain is no big deal, just add BSDL
> > file for TI's part to Xilinx's 'JTAG programmer' tool.
> > In the past I've used JTAG to chain-up devices (Xilinx, Lattice)
> > but always from the same manufacturer, I've never mixed-up
> > different chips, from different manufacturers, neither I added MPUs
> > into the chain. now I guess the only way to check it up is to make
> > the actual circuitry and then 'everything is in God's hands'.
> > (Well, the same problem is applicable to Atmel AVmega128
> > to be chained-up with other JTAG-capable chips)
> >
> > "rickman" <spamgoeshere4@yahoo.com> wrote in message
> > news:3C414ACF.EA8194EA@yahoo.com...
> > > DG_1 wrote:
> > > >
> > > > Hi there,
> > > > Has anybody tried to chain-up a MSP430 with any of JTAG-capable
> > > > Xilinx chips and be able to programm both of them without problem(s)
> > > > (MSP430 via IAR KickStart, Xilinx via JTAG programmer)?
> > > > Or (re-arranged question)::
> > > > Does IAR Kick-Start still recognizes MSP430 and/or allows other
> > > > devices (other than MSP430) to be chained-up via JTAG?
> > > >
> > > > Thanks in advance,
> > > > -- D.G.
> > >
> > >
> > > I will be doing exactly this in a month or two. I am building a board
> > > with a TMS320C6711, an MSP430F148/9, an XC2S150E and an XCR3256XL all
in
> > > one JTAG chain. Actually, I may leave the MSP430F148/9 out of the
chain
> > > depending on the answers to the questions I will be asking the
vendors.
> > > But I really want the rest of it in a single chain so that I can do
> > > boundry scan testing on it all. The MSP430F148/9 will not be quite so
> > > integrated into the rest of the board, so it does not have to be
tested
> > > that way. It is also important to be able to burn software into it
> > > regarless of the state of the board. This will be used for initial
board
> > > test too. I am even considering using the MSP430F148/9 as a JTAG
> > > interface for the JTAG chain. But we will see if I can get it all to
> > > work together.
> > >
> > > If you have any results yourself, please let me know. Thanks!
> > >
> > > --
> > >
> > > Rick "rickman" Collins
> > >
> > > rick.collins@XYarius.com
> > > Ignore the reply address. To email me use the above address with the
XY
> > > removed.
> > >
> > > Arius - A Signal Processing Solutions Company
> > > Specializing in DSP and FPGA design URL http://www.arius.com
> > > 4 King Ave 301-682-7772 Voice
> > > Frederick, MD 21701-3110 301-682-7666 FAX
> > >
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
>
Article: 38452HI, "Martin Fischer" <Martin.Fischer@fzi.de> wrote: > I don't understand why an Signal toggles at the rising > edge, because I want to toggle it at an falling edge. Which Signal do you mean? Maybe its affected somewhere outside the code below. > Phasen : process (MSP_CLK, Befehl_Empfangen) There are two kind of process, you should use (the third is for people knowing what they do *g*) 1. clocked process => only sensitive to clock and reset. 2. logical process => sensitive to all signals, that occoure on the right side. Your Process is triggered on every Edge of Befehl_Empfangen or the unknown signal (for the newsgroup) MSP_CLK. > if (Befehl_Empfangen='0' and Empfangs_Buffer(3 downto 0)="0000") > then > Zustand <= Zustand0; > Speicherdummy(3 downto 0)<="0000"; > elsif falling_edge(Befehl_Empfangen) then > case Zustand is > when Zustand0 => > if Empfangs_Buffer(3 downto 0)="0001" then [..] > Zustand <= Zustand1; I can imagine thousands of settings, where code not listet here affect the behavior. You should be more precise, which was the initial value for Zustand, what's about MSP_CLK, when change Empfangs_buffer ist value... bye Thomas -- Thomas Stanka TE/EMD4 Space Communications Systems Tesat Spacecom GmbH & Co KG thomas.stanka@tesat.deArticle: 38453
when one is divided 64,how i do get the remainder? wire [7:0] a,b; assign a=b%6'b100000; Both a and b are variable. is it OK? or how shoult i implement?Article: 38454
Hello, How to generate the VHDL netlist for the design implemented on FPGA? I tried synthesizing the design through the dc_shell and written the netlist in VHDL. But the generic information for the LUT's in missing. If I try to generate the xnf netlsit then that information is present in the form of equations. The behaviour of the LUT's is also present in edif netlist. So while writting the VHDL netlist does dc_shell requires some additional thing? Regards, MadhuraArticle: 38455
Ansgar Bambynek wrote: > Hi, > > you should at least run a min and a max simulation. Min usually checks for > hold time violations, max for setup violations. To be sure your design works > properly you should run simulations with all 3 different timings. You can > also verify your timing statically with the timing analyzer which comes with > your FPGA place and route software. At least Xilinx Tools have this ability, > I'm not sure about other FPGA vendor tools since I only use Xilinx FPGAs. > > HTH > > Ansgar > > You might have to be careful here. When NGD2VER/NGD2VHD produces its SDF delay file from the NGDANNO backannotated database it may not produce one with all the min/nom/max timings. This was certainly the case as far as 2.1i where all 3 fields were the same, I haven't checked 3.x/4.x. The default for NGDANNO is to produce a max timing file based on the speed grade selected at the MAP stage. This can be changed using the `-s' command line flag and `-s min' will get you a minimum timing SDF. Note that not all Xilinx part families have min timings defined in their speed files, generally the more recent ones don't. You can find out whether the min timings are defined by using speedprint -min <device name> Note also that you can get a rough approximation for nom/min timings with a max SDF by using the scale factors available with the $sdfannotate system task (Verilog at least). If anyone out there has done a Perl script that merges the max & min SDFs please let me know. I started this but sort of gave up on the SDF syntax.Article: 38456
David Miller wrote: > > Phasen : process (MSP_CLK, Befehl_Empfangen) > > Begin > > if (Befehl_Empfangen='0' and Empfangs_Buffer(3 downto 0)="0000") then > > Zustand <= Zustand0; Speicherdummy(3 downto 0)<="0000"; > > > > elsif falling_edge(Befehl_Empfangen) then > > Also be aware that in at least some technologies (Xilinx), the place and > route tool will not trace paths into asynchronous inputs during timing > analysis. > I don't think this is true. But what *is* true is that there is a flag that controls this kind of path tracing. I was caught out by this when Xilinx changed the default from ON to OFF between 1.4 and 1.5! There was a lot of discussion that this was a BAAAD idea but, since I always set the path tracing control myself in the PCF I haven't checked to see whether they have changed it. This control affects timing analysis of both sync and async set/reset.Article: 38457
kossyma wrote: > There is one 32bit register.The [31:18] of register is divided 64.The register value is variable.i > write:is it OK? > *********************************** > wire [31:0 ]register; > wire Quotient; > wire Remainder; > assign Quotient=register[31:18]>>6'b100000; > assign Remainder=register[31:18]%6'b100000; > when i synthesis,it says: > Error: Operands to mod must be constant in routine % called from PT_EOP_GalNet_DMA line 109 in file 'E:/gt48350/PT_EOP_GalNet_DMA.v' (HDL-65) > Implementation Errors > > can you help me? Read the section of your synthesiser manual that describes the subset acceptable for synthesis.Article: 38458
I've attempted to synthesise a small design targeted at an XCR3128XL. The synthesis process completes o.k. but when I come to run NGDBUILD it hangs at the ``Reading component libraries for design expansion'' stage. Looking further it seems that Synplify (7.0.2) is not mapping to the Xilinx target library but some sort of internal set of primitives. This is even the case if I set the -domap option to 1 in the batch (Tcl) script. If I change the synthesis target technology back to XC9500-XL NGDBUILD goes through no problem with the part defined as "-p XCR3128XL..." and the device fits just fine. What dumb thing am I doing wrong ?Article: 38459
Thanks to all, but I changed my logic and added a new process. Now I have no faults. But I don't understand, why I can't toggle signals at the falling edge :-(( MartinArticle: 38460
Rick Filipkiewicz wrote: > I've attempted to synthesise a small design targeted at an XCR3128XL. > The synthesis process completes o.k. but when I come to run NGDBUILD it > hangs at the > > ``Reading component libraries for design expansion'' > > stage. Looking further it seems that Synplify (7.0.2) is not mapping to > the Xilinx target library but some sort of internal set of primitives. > This is even the case if I set the -domap option to 1 in the batch (Tcl) > script. > > If I change the synthesis target technology back to XC9500-XL NGDBUILD > goes through no problem with the part defined as "-p XCR3128XL..." and > the device fits just fine. > > What dumb thing am I doing wrong ? The answer to the last question was assuming that if CoolRunner is in the supported device list for 7.0 then its actually supported for mapping to a target device. It isn't and the workaround is to target - surprise, surprise - an XC9500. Was I naive or what? Don't you just love marketing's idea of device support.Article: 38461
Duane Clark wrote:
>
> David Findlay wrote:
> > Is it possible to build a homebrew computer of some description
> > using FPGA's? I know it won't be as powerful as a PC, but I'm more
> > interested in designing and building my own.
>
> Sure. For example, here is a Sparc on an FPGA:
> http://www.estec.esa.nl/wsmwww/leon/
We have a laboratory course at our university, in which students develop a
16-bit processor, using one XILINX FPGA (using WORKVIEW CAD-Software):
- 128 kByte memory-address
- 128 kByte i/o-address
- 5 Interrupt levels
- 3-address instructions
- 0.3 MIPS
- less than 2000 gate-functions
Two students have built a complete computer using this prozessor:
1. FPGA: processor
2. FPGA: graphics controller: 640x400 pixels, 2 pages, 2 colors out of 8
3. FPGA: - SCSI controller
- Keyboard controller
- Timer
4. FPGA: - parallel interface
- seriell interface
Multi-tasking operating system (also multiple shells can be startet)
The computer is built using only these 4 XILINX FPGA, static ram and rom
chips and line drivers. The only other components used were the hard-disk,
floppy-disk-drive, power supply, keyboard and monitor).
We have also made a redesign of the CPU with a memory management
included (16 MByte virtual address space for each task, protection
mechanism for multitasking). This CPU supports DRAM instead of SRAM.
The documentation and software can be downloaded from:
ftp://137.193.64.130/pub/xproz/
There is also a very simple 16-bit processor mproz buildt with only
65 FF's and about 250 gates:
ftp://137.193.64.130/pub/mproz/
Article: 38462Hello. We are using the Virtex-2 DCMs for clock synthesis. The output frequency has to be modified during run time. Is there a way to dynamically change the values of CLKFX_MULTIPLY and CLKFX_DIVIDE (e.g. connecting two register to these signals). If not, can the addresses of the relevant locations in the bitsream (XC2V3000-BF957CES) be documented or can we somehow use JBITS to do it or do we have to reverse engineer them ? Thanks for your help. Andreas -- Andreas Kugel - University of Mannheim - Dept. of Computer Science V FPGA-Processor Group B6,23-29A - 68131 Mannheim - Germany Phone:+(49)621 181 2632 - Fax:+(49)621 181 3580 mailto:kugel@ti.uni-mannheim.de http://www-li5.ti.uni-mannheim.de/fpga/index.shtmlArticle: 38463
Falk Brunner <Falk.Brunner@gmx.de> wrote: > In general this cascade works. Make sure you reset the DLLs, especial the > second. Have a look at the Xapps, there are good examples (including VDHL). It will suffer with clock jitter. If you have enough jitter on the input clock to the first DLL, you might violate the input requirements of the second. (I think.) Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 38464
David Miller <spam@quartz.net.nz> wrote: > Also be aware that in at least some technologies (Xilinx), the place and > route tool will not trace paths into asynchronous inputs during timing > analysis. It does if you enable it in your UCF/PCF. From memory it's "ENABLE = reg_sr_q" or something like that - check the constraints guide (4.1) / libraries guide (3.1). Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 38465
Magnus Homann <d0asta@mis.dtek.chalmers.se> wrote: > You have two cross-domain signals here, but I guess you knew that. Do > you have a constraint there too? Yes I do. > It's hard to understand what you are doing. Couldn't you just clock > the middle FF with LSCLK? If your Pulse is one LSCLK period long you > get metastability problems when CE comes in the metawindow of HSCLK. I have a pulse for one cycle of LSCLK. I sample it in HSCLK and detect the rising edge; I use the detected edge to clock the sampling flip flops with HSCLK. > Swapping HSCLK for LSCLK you instead get metastability problem when D > changes in the metawindow of LSCLK. > You said coherent, I'm assuming you have a several values > (e.g. counter) you want to sample at the same time? That's right. I need all the bits from the same sample ie I can't tolerate a few bits from one clock and the rest from another. Otherwise I could just deal with metastability and wouldn't need the sampling step. regards, Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 38466
Hal Murray <hmurray-nospam@megapathdsl.net> wrote: >>They're completely unrelated clocks, all sourced off-chip. I >>know how to cope with metastability -- but the tools are including >>some (AFAICT irrelevant) clock skew in the calculations. > My guess is that the tools are setup to process the case > where the clocks are correllated and the skew does matter. > That seems like it will be much more common than your case. I'd be interested to know if that really is more common (show of hands from the other newsgroup readers)? This is the first design I've worked on (from an admittedly small sample) which has any related clocks at all -- and most of them still aren't (and there's lots of them). So I live with FROM:TO's slightly screwy analysis of this case because it's certainly better than nothing. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 38467
Hi, does anybody know how to program the RS232 interface on the Atmel ATSTK40 board offered by Kanda? In particular I'm looking for 3 components to realize this: 1) UART circuit to be implented on the FPGA. 2) Interface software running on Windows 2000. 3) Since the serial port cannot be addressed directly, an extra driver is required. Thanx for any advice! Cheers, Bernd -- e-mail: scheuermann@aifb.uni-karlsruhe.deArticle: 38468
I just found an old box containing a DS-502, XC4003A-6 demo board. Does anybody know where I can find documentation and software tools for this device? TIA Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | (~8'h2B) - Hamlet in Verilog http://gustad.comArticle: 38469
FPGA 2002 Final Program and Information
ACM/SIGDA Tenth International Symposium on Field Programmable Gate Arrays
Sponsored by ACM/SIGDA
with support from Actel, Cypress Semiconductor, Altera and Xilinx
Monterey Beach Hotel, Monterey, California
February 24-26, 2002
web site: http://www.ecs.umass.edu/ece/fpga2002/
Several "reduced rate" deadlines are rapidly approaching.
The deadline for the reduced conference rate is January 18. The
deadline for guaranteed-rate Monterey Beach Hotel reservations is
February 4. Please see the symposium web site listed above
for more details.
----------------------------------------------------------------
PROGRAM
--------------------
SUNDAY, February 24, 2002
6:00PM Registration
7:00PM Welcoming Reception
MONDAY, February 25, 2002
7:30AM Continental Breakfast and Registration
8:20AM Opening Remarks, Martine Schlag, Steve Trimberger
Session 1. Interconnect Architecture
Chair: Steve Wilton, University of British Columbia
8:30AM Interconnect Enhancements for a High-Speed PLD Architecture,
Michael Hutton, Vinson Chan, Peter Kazarian, Victor Maruri,
Tony Ngai, Jim Park, Rakesh Patel, Bruce Pedersen, Jay Schleicher,
Sergey Shumarayev, Altera
8:50AM FPGA Switch Block Layout and Evaluation, Herman Schmit, Vikas
Chandra, Carnegie Mellon University
9:10AM Circuit Design of FPGA Routing Switches, Guy G. Lemieux,
David M. Lewis, University of Toronto
9:30AM Coffee Break and Poster Presentations
Session 2. Arithmetic
Chair: Tom Kean, Algotronix
10:30AM A Faster Distributed Arithmetic Architecture for FPGAs,
Radhika S. Grover, Weijia Shang, Qiang Li, Santa Clara University
10:50AM Efficient Architectures for Implementing Montgomery Modular
Multiplication and RSA Modular Exponentiation on
Reconfigurable Logic, Alan Daly, Liam Marnane, University
College, Cork
11:10AM A Flexible Floating-Point Format for Optimizing Data-Paths and
Operators in FPGA Based DSPs, J. Dido, N. Geraudie, L.
Loiseau, O. Payeur, Y. Savaria, École Polytechnique de Montréal;
D. Poirier, Miranda Technologies, Inc.
11:30 AM Poster Presentations
12:00 N Lunch
Session 3. Physical Design
Chair: Russ Tessier, University of Massachusetts - Amherst
1:30PM Efficient Circuit Clustering for Area and Power Reduction in
FPGAs, Amit Singh, Malgorzata Marek-Sadowska, University
of California, Santa Barbara
1:50PM Integrated Retiming and Placement for Field Programmable Gate
Arrays, Deshanand P. Singh, Stephen D. Brown, University of Toronto
2:10PM SPFD-Based Global Rewiring, Jason Cong, Yizhou Lin, Wangning
Long, University of California, Los Angeles
2:30PM Eve: A CAD Tool for Manual Placement and Pipelining Assistance
of FPGA Circuits, William Chow, Jonathan Rose, University of Toronto
2:50PM Coffee Break and Poster Presentations
Session 4. Cellular and Cryptographic Applications
Chair: Scott Hauck, University of Washington
3:50PM Application of FPGA Technology to Accelerate the
Finite-Difference Time-Domain (FDTD) Method, Ryan N. Schneider,
Laurence E. Turner, Michal M. Okoniewski, University of Calgary
4:10PM FPGA Implementation of Neighborhood-of-Four Cellular Automata
Random Number Generators, Barry Shackleford, Motoo Tanaka,
Richard J. Carter, Greg Snider, Hewlett-Packard
4:30PM Cryptographic Rights Management of FPGA Intellectual Property
Cores, Tom Kean, Algotronix
4:50PM Poster Presentations
6:30PM Busses Depart for Monterey Bay Aquarium
7:00PM-11:00PM Dinner at the Monterey Bay Aquarium
TUESDAY, February 26, 2002
7:30 AM Breakfast
Session 5. Synthesis, Verification and Test
Chair: Jason Cong, UCLA
8:30AM Constrained Clock Shifting for Field Programmable Gate Arrays,
Deshanand P. Singh, Stephen D. Brown, University of Toronto
8:50AM Timing Verification of Dynamically Reconfigurable Logic for
the Xilinx Virtex FPGA Series, Ian Robertson, University of
Strathclyde; David Robinson, The Alba Centre; James Irvine,
University of Strathclyde
9:10AM FPGA Test Time Reduction Through a Novel Interconnect Testing
Scheme, Stuart McCracken, Zeljko Zelic, McGill University
9:30AM Coffee Break and Poster Presentations
Session 6. Architecture Analysis and Automation
Chair: Vaughn Betz, Altera
10:30AM On the Sensitivity of FPGA Architectural Conclusions to
Experimental Assumptions, Tools and Techniques, Andy Yan, Rebecca
Cheng, Steven Wilton, University of British Columbia
10:50AM Dynamic Power Consumption in Virtex-II FPGA Family, Li Shang,
Princeton University; Alireza S. Kaviani, Kusuma Bathala, Xilinx, Inc.
11:10AM Automatic Layout of Domain-Specific Reconfigurable Subsystems
for System-on-a-Chip, Shawn Phillips, Scott Hauck,
University of Washington
11:30AM Poster Presentations
12:00 N Lunch
Session 7. Software for Reconfigurable Systems
Chair: Miriam Leeser, Northeastern University
1:30PM Performance-Constrained Pipelining of Software Loops onto
Reconfigurable Hardware, Greg Snider, Hewlett-Packard
1:50PM Configuration Prefetching Techniques for Partial Reconfigurable
Coprocessor with Relocation and Defragmentation, Zhiyuan Li,
Northwestern University; Scott Hauck, University of Washington
2:10PM Analysis of Quasi-Static Scheduling Techniques in a Virtualized
Reconfigurable Machine, Yury Markovskiy, Eylon Caspi, Randy
Huang, Joseph Yeh, Michael Chu, University of California
Berkeley; André DeHon, Caltech; John Wawrzynek, University of
California, Berkeley
2:30PM Incremental Reconfiguration of Multi-FPGA Systems, K.K. Lee,
Synopsys; D.F. Wong, University of Texas at Austin
2:50PM Coffee Break and Poster Presentations
Session 8. Innovative Applications
Chair: Ray Andraka, Andraka Consulting Group
3:50PM Parallel-Beam Backprojection: An FPGA Implementation Optimized
for Medical Imaging, Srdjan Coric, Miriam Leeser, Eric Miller,
Northeastern University; Marc Trepanier, Mercury Computer Systems
4:10PM A Dynamically Reconfigurable Adaptive Viterbi Decoder,
Sriram Swaminathan, Russell Tessier, Dennis Goeckel,
Wayne Burleson, University of Massachusetts, Amherst
4:30PM Data Reorganization Engines for the Next Generation of
System-On-a-Chip FPGAs, Pedro Diniz, Joonseok Park, University
of Southern California/ISI
4:50PM Closing Remarks, Martine Schlag, Steve Trimberger
Article: 38470> > 1) UART circuit to be implented on the FPGA. Look at http://www.opencores.org > 2) Interface software running on Windows 2000. > 3) Since the serial port cannot be addressed directly, an extra driver is > required. Serial port can be accessed like a file. No extra driver is required. JanArticle: 38471
kossyma ha scritto nel messaggio ... >when one is divided 64,how i do get the remainder? >wire [7:0] a,b; >assign a=b%6'b100000; >Both a and b are variable. >is it OK? >or how shoult i implement? Please, search with www.deja.com a thread named "Kindergarten Stuff" about one month ago. Regards LuigiArticle: 38472
Hamish, The peak to peak jitter from the DLL is purely random, so it adds quadratically (sum of the square root of the squares). Thus one can tandem two DLLs without violating the input requirements of the second DLL (presuming a reasonable input jitter value -- like less than 75 ps P-P). The resulting output jitter is also reasonable. Thus we do support the cascade of not more than two DLL's, using the CLK0/90/180 or 270 outputs fromt he first, to the second. If, for example, each DLL has ~ 150 ps P-P jitter alone, the tandem combination would have ~ 212 ps P-P jitter. But, I agree with Peter .... Austin hamish@cloud.net.au wrote: > Falk Brunner <Falk.Brunner@gmx.de> wrote: > > In general this cascade works. Make sure you reset the DLLs, especial the > > second. Have a look at the Xapps, there are good examples (including VDHL). > > It will suffer with clock jitter. If you have enough jitter on the input > clock to the first DLL, you might violate the input requirements of > the second. (I think.) > > Hamish > -- > Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 38473
Andreas, The values must be modified in the bitstream, and then the DCM must be reset. I suggest that you run two designs that are identical except for the M and D values. Generate the bitstreams (use the option that gives you that ascii .rbt file). Do a diff on the two files. You will see the different 32 bit frames with the two ten bit register values (not all ten bits are used). You may then generate a bitstream with the CRC turned off (bitgen option) so you may generate any bitstream values you wish for M and D by hacking the M and D bit locations. Email me directly with questions, austin@xilinx.com. Austin Andreas Kugel wrote: > Hello. > > We are using the Virtex-2 DCMs for clock synthesis. The output frequency > has to be modified during run time. Is there a way to dynamically change > the values of CLKFX_MULTIPLY and CLKFX_DIVIDE (e.g. connecting two > register to these signals). If not, can the addresses of the relevant > locations in the bitsream (XC2V3000-BF957CES) be documented or can we > somehow use JBITS to do it or do we have to reverse engineer them ? > > Thanks for your help. > Andreas > > -- > Andreas Kugel - University of Mannheim - Dept. of Computer Science V > FPGA-Processor Group > B6,23-29A - 68131 Mannheim - Germany > Phone:+(49)621 181 2632 - Fax:+(49)621 181 3580 > mailto:kugel@ti.uni-mannheim.de > http://www-li5.ti.uni-mannheim.de/fpga/index.shtmlArticle: 38474
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CALL FOR PAPERS
15th Annual IEEE International ASIC/SOC Conference
September 25-28, 2002
RIT Inn and Conference Center, Rochester, New York
Driven by the rapid growth of the Internet, communication
technologies, pervasive computing, and wireless and portable consumer
electronics, Systems-on-Chip (SoC) have become a dominant issue in
today's ASIC industry. The transition from traditional Application-
Specific Integrated Circuits (ASIC) to SoCs has created new
challenges in Design Methods, Design Tools, Design Automation,
Manufacturing, Technology and Test. The ASIC/SOC Conference provides
a forum for sharing advances in ASIC and SoC technology and
applications. The 2002 Conference will offer three days of technical
papers and a full day of technical workshops.
GENERAL INFORMATION
This year's ASIC/SOC Conference will be held at the Rochester Institute of
Technology Inn and Conference Center. Rochester New York is served by the
Greater Rochester International Airport and is within easy driving distance
of the Buffalo International Airport and most of New England.
Accommodations will be available for $79.00 a night at the RIT Inn.
Rochester, the third largest urban area in New York State, offers a wide
range of cultural, historic, and recreational activities within the relaxed
atmosphere of upstate New York.
TECHNICAL SCOPE
Papers are invited which address new and previously unpublished results in
the following categories or in related areas. Proposals for tutorial
papers, tutorials, workshops, and panel sessions are also invited. The
best paper will be acknowledged with a best paper award.
System on Chip Manufacturing Test and Verification
Design Tools Embedded Systems Novel Circuits & Structures
Design Methods Analog and Mixed Signal Computing Systems
Design Automation Applications Intellectual Property
PAPER SUBMISSION
Electronic paper submission requires a 25 word condensed abstract for the
Advance Program, and the full paper, limited to five double-column IEEE
format pages, including figures and references. Please refer to the
conference web page at http://asic.union.edu for paper formatting and paper
submission as an Adobe PDF file.
DEADLINE FOR PAPER SUBMISSION: APRIL 12, 2002
NOTIFICATION OF PAPER ACCEPTANCE: MAY 31, 2002
FINAL CAMERA-READY PAPERS DUE: JUNE 28, 2002
Please visit the Conference web site at http://asic.union.edu or contact
the ASIC/SOC Conference office at 301-527-0900 x104 for paper submission,
registration, and current conference information.
ORGANIZING COMMITTEE
General Chair Technical Program Chair Technical Program Co-Chair
P. R. Mukund John Chickanosky Dong Ha
RIT IBM Microelectronics Virginia Tech
prmeee@rit.edu chickano@us.ibm.com ha@vt.edu
Publications Chair Steering Committee Chair Workshop Chair
Richard Auletta Thomas Bochner Ram Krishnamurthy
LSI Logic IBM Boblingen Lab Intel
rauletta@lsil.com tbuechner@de.ibm.com ramk@hf.intel.com
Sponsored by the IEEE Circuits and Systems Society
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