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Thanks 'rickman'. The only problem I 'foresee' is the fact that IAR Kickstart doesn't have any capability of adding/editing BSDL files (or I missed something). Therefore, I don't see the way how to use debugging features of IAR Kickstart when _more_ than one chip is in the same chain. I guess, designers of IAR's tool-set didn't (intentionally?) though-out that possibility. Also, I guess, from Xilinx's perspective, having MSP430 in the same chain is no big deal, just add BSDL file for TI's part to Xilinx's 'JTAG programmer' tool. In the past I've used JTAG to chain-up devices (Xilinx, Lattice) but always from the same manufacturer, I've never mixed-up different chips, from different manufacturers, neither I added MPUs into the chain. now I guess the only way to check it up is to make the actual circuitry and then 'everything is in God's hands'. (Well, the same problem is applicable to Atmel AVmega128 to be chained-up with other JTAG-capable chips) "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3C414ACF.EA8194EA@yahoo.com... > DG_1 wrote: > > > > Hi there, > > Has anybody tried to chain-up a MSP430 with any of JTAG-capable > > Xilinx chips and be able to programm both of them without problem(s) > > (MSP430 via IAR KickStart, Xilinx via JTAG programmer)? > > Or (re-arranged question):: > > Does IAR Kick-Start still recognizes MSP430 and/or allows other > > devices (other than MSP430) to be chained-up via JTAG? > > > > Thanks in advance, > > -- D.G. > > > I will be doing exactly this in a month or two. I am building a board > with a TMS320C6711, an MSP430F148/9, an XC2S150E and an XCR3256XL all in > one JTAG chain. Actually, I may leave the MSP430F148/9 out of the chain > depending on the answers to the questions I will be asking the vendors. > But I really want the rest of it in a single chain so that I can do > boundry scan testing on it all. The MSP430F148/9 will not be quite so > integrated into the rest of the board, so it does not have to be tested > that way. It is also important to be able to burn software into it > regarless of the state of the board. This will be used for initial board > test too. I am even considering using the MSP430F148/9 as a JTAG > interface for the JTAG chain. But we will see if I can get it all to > work together. > > If you have any results yourself, please let me know. Thanks! > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAX >Article: 38401
axilon <axilon@attbi.com> wrote in message news:<3C3BE93D.8050002@attbi.com>...
> How can I relate the package pin names and Slice XY locations in Xilinx
> Virtex2 device? I need it to put LOC constraint to IOB.
> I looked into the pinout_text_files at DataSource CD-ROM but its
> Slice X/Y Location data doesn't match with Physical names appeared at
> FPGA editor screen. For an example, in 2v40cs144.txt file, X15Y14
> location has 6 pads (PAD21-PAD26) - that doesn't make sense since
> each Slice location can have max 4 pads. Am I just discovered
> documentation error?
> Can any Xilinx folks out there answer my question?
> TIA
> Ax
If you are writing in HDL, your top-level entity's ports are the "logical"
pin names.
The PAR tool-chain accepts a constraint file my_design.UCF, which can be
used (among other things) to set locations for both logic and I/O pins.
In my opinion, it is best to create the .UCF file manually using a standard
text editor, and then never allow the Xilinx tools to modify it (e.g.
floorplanner or Constraint Editor).
If your top-level entity contains the description
entity my_top
port (
....
MY_INPUT: std_logic;
MY_BUS: std_logic_vector(7 downto 4);
....
The .UCF file should contain the entries:
....
NET "MY_PORT" LOC = "AB21";
NET "MY_BUS<4>" = "AC19";
NET "MY_BUS<5>" = "AC21";
....
Notes:
* VHDL is not case-sensitive, Verilog and the PAR tools are. Even if you
write in VHDL, it is best to write your top-level ports in uppercase.
* Bus nets are sometimes named MY_BUS<n> and sometimes MY_BUS(n). I haven't
been able to find out the logic behind it - I just try and see what works.
* The pin names specifed in the LOC are the same as the pin names in the
package mechanical description.
* It is not required, but recommended to put net pin names in quotes; this
prevents misunderstandings between net names and reserved words (e.g. CLOCK).
Hope this helps
Regards
Assaf Sarfati
Article: 38402David Findlay <david_j_findlay@yahoo.com.au> wrote in message news:pan.2002.01.14.07.54.25.119281.7489@yahoo.com.au... > Well what I'd hope to be doing is creating a simple computer, but with specialised logic > sections to speed up certain operations that take a while on conventional processors. So I > suppose although it wouldn't be as fast on some functions, it could be much faster on others. > I'm after preformance on complex simulations so physics logic would be useful. > > David David, One thing I didn't mention about Altera's Nios processor in my last posting: the latest incarnation allows you to add custom instructions to the processor core. It's all integrated into the tool flow so it looks relatively painless (although I haven't used the custom instructions myself, so I can't speak from first-hand experience). Here's the web link: http://www.altera.com/products/devices/excalibur/features/exc-nios_cpu_archi tecture.html#custom_instructions -Pete-Article: 38403
I don't think I would leave this "in God's hands". I would contact IAR and get the straight scoop. If they don't give you a way to include BDSL files for the other chips in the chain, I don't think it will work. If nothing else, it has to know how many chips are in the chain. I think there is a way to put each chip in a state where it looks like a single FF. This would be the simplest way for the IAR debugger to deal with the other chips. I only need the JTAG on the MSP430 for debugging of the code in development and I need something to let me program the MSP430 flash in production. They have a "boot monitor" that will work as a 9600 bps serial port which I may use. But they did not use the same pins as the actual serial port, so it will be a little tricky to get this going without using up too many pins on the MSP430. I am using every last IO pin. I am also concerned with the same JTAG compatibility problem with the C67 DSP. I will need to contact TI about that. Oh yeah, I also have to check with Xilinx since I will need to program the XCR3256 after the board is built. Too bad JTAG is not more widely supported across vendors. It always seems to have trouble when the chains are mixed. I just don't have the board space to have three separate JTAG connectors. DG_1 wrote: > > Thanks 'rickman'. > The only problem I 'foresee' is the fact that IAR Kickstart doesn't > have any capability of adding/editing BSDL files (or I missed something). > Therefore, I don't see the way how to use debugging features > of IAR Kickstart when _more_ than one chip is in the same chain. > I guess, designers of IAR's tool-set didn't (intentionally?) > though-out that possibility. Also, I guess, from Xilinx's perspective, > having MSP430 in the same chain is no big deal, just add BSDL > file for TI's part to Xilinx's 'JTAG programmer' tool. > In the past I've used JTAG to chain-up devices (Xilinx, Lattice) > but always from the same manufacturer, I've never mixed-up > different chips, from different manufacturers, neither I added MPUs > into the chain. now I guess the only way to check it up is to make > the actual circuitry and then 'everything is in God's hands'. > (Well, the same problem is applicable to Atmel AVmega128 > to be chained-up with other JTAG-capable chips) > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3C414ACF.EA8194EA@yahoo.com... > > DG_1 wrote: > > > > > > Hi there, > > > Has anybody tried to chain-up a MSP430 with any of JTAG-capable > > > Xilinx chips and be able to programm both of them without problem(s) > > > (MSP430 via IAR KickStart, Xilinx via JTAG programmer)? > > > Or (re-arranged question):: > > > Does IAR Kick-Start still recognizes MSP430 and/or allows other > > > devices (other than MSP430) to be chained-up via JTAG? > > > > > > Thanks in advance, > > > -- D.G. > > > > > > I will be doing exactly this in a month or two. I am building a board > > with a TMS320C6711, an MSP430F148/9, an XC2S150E and an XCR3256XL all in > > one JTAG chain. Actually, I may leave the MSP430F148/9 out of the chain > > depending on the answers to the questions I will be asking the vendors. > > But I really want the rest of it in a single chain so that I can do > > boundry scan testing on it all. The MSP430F148/9 will not be quite so > > integrated into the rest of the board, so it does not have to be tested > > that way. It is also important to be able to burn software into it > > regarless of the state of the board. This will be used for initial board > > test too. I am even considering using the MSP430F148/9 as a JTAG > > interface for the JTAG chain. But we will see if I can get it all to > > work together. > > > > If you have any results yourself, please let me know. Thanks! > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX > > -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 38404
Good Morning,
I'm using the following code to arrange a pair of two CLKDLL one that
divide the clock by two and the other that divide it by 3 to obtain
the final result of a clock divided by 6 , the problem is that I could
have the clock divided by two while the output at the following clock
divider is always 0, there's a special reason for this ?? I've to
arrange this cascade in another way ??
By the way also another question, I still haven't understand if vhdl
have this degree of freedom :
I would want to change at runtime the value of the divider factor of
the two CLKDLL depending for example on the value of an input port.
Thanks for your help and here's the code :
library IEEE;
use IEEE.std_logic_1164.all;
-- other libraries declarations
-- synopsys translate_off
library VIRTEX;
library IEEE;
use IEEE.vital_timing.all;
-- synopsys translate_on
entity b is
port(
clk : in std_ulogic;
reset : in std_ulogic;
clk_div_2 : out std_ulogic;
clk_div_6 : out std_ulogic
);
end b;
architecture b of b is
---- Component declarations -----
component BUFG
-- synopsys translate_off
generic(
InstancePath : STRING := "*";
MsgOn : BOOLEAN := TRUE;
TimingChecksOn : BOOLEAN := false;
Xon : BOOLEAN := TRUE;
tipd_I : VitalDelayType01 := (0 ns,0 ns);
tpd_I_O : VitalDelayType01 := (0 ns,0 ns)
);
-- synopsys translate_on
port (
I : in std_ulogic;
O : out std_ulogic
);
end component;
component CLKDLL
-- synopsys translate_off
generic(
CLKDV_DIVIDE : REAL := 2.000000;
DUTY_CYCLE_CORRECTION : BOOLEAN := TRUE;
InstancePath : STRING := "*";
MAXPERCLKIN : TIME := 100 ns;
MsgOn : BOOLEAN := false;
TimingChecksOn : BOOLEAN := TRUE;
Xon : BOOLEAN := TRUE;
tipd_CLKFB : VitalDelayType01 := (0 ns,0 ns);
tipd_CLKIN : VitalDelayType01 := (0 ns,0 ns);
tipd_RST : VitalDelayType01 := (0 ns,0 ns);
tpd_CLKIN_LOCKED : VitalDelayType01 := (0 ns,0 ns);
tperiod_CLKIN : VitalDelayType := 0.01 ns;
tpw_CLKIN_negedge : VitalDelayType := 0.01 ns;
tpw_CLKIN_posedge : VitalDelayType := 0.01 ns;
tpw_RST_posedge : VitalDelayType := 0.01 ns
);
-- synopsys translate_on
port (
CLKFB : in std_ulogic := '0';
CLKIN : in std_ulogic := '0';
RST : in std_ulogic := '0';
CLK0 : out std_ulogic := '0';
CLK180 : out std_ulogic := '0';
CLK270 : out std_ulogic := '0';
CLK2X : out std_ulogic := '0';
CLK90 : out std_ulogic := '0';
CLKDV : out std_ulogic := '0';
LOCKED : out std_ulogic := '0'
);
end component;
---- Signal declarations used on the diagram ----
signal clk_2 : std_ulogic;
signal NET616 : std_ulogic;
---- Configuration specifications for declared components
-- synopsys translate_off
for U1 : CLKDLL use entity VIRTEX.CLKDLL;
-- synopsys translate_on
-- synopsys translate_off
for U2 : CLKDLL use entity VIRTEX.CLKDLL;
-- synopsys translate_on
-- synopsys translate_off
for U3 : BUFG use entity VIRTEX.BUFG;
-- synopsys translate_on
begin
---- Component instantiations ----
U1 : CLKDLL
-- synopsys translate_off
generic map (
CLKDV_DIVIDE => 2.0
)
-- synopsys translate_on
port map(
CLKDV => NET616,
CLKIN => clk,
RST => reset
);
U2 : CLKDLL
-- synopsys translate_off
generic map (
CLKDV_DIVIDE => 3.0
)
-- synopsys translate_on
port map(
CLKDV => clk_div_6,
CLKIN => clk_2,
RST => reset
);
U3 : BUFG
port map(
I => NET616,
O => clk_2
);
---- Terminal assignment ----
-- Output\buffer terminals
clk_div_2 <= clk_2;
end b;
Article: 38405
cjwang_1225@hotmail.com (chris) wrote in message news:<24a13eb0.0201111713.7f9af7b5@posting.google.com>...
> i am trying to do a speech recognition application and i need a clean
> input voice signal to a microphone. my problem is that i need to get
> rid of ambient noise in a room without affecting the voice signal at
> all. i have thought about doing an adaptive filter like application,
> but i cannot think of a way to isolate just the ambient noise without
> touching the voice. my main goal would be to come up with some kind of
> active noise control setup that would be able to phase-cancel the
> ambient noise while keeping the voice signal clean. does anyone know
> how this can be done? i have seen something similar from andreas
> electronics, but their product doesn't exactly fit my requirement. any
> help would be appreciated. thanks.
> chris wang
Hi chris,
You can isolate the ambient Guassian noise (white or
coloured) from the signal if you are able to work out an adaptive
filter based on Higher Order Statistics. I will try to give you some
background in this particaular HOS application, but I am not aware of
its practical implementation, though various papers on HOS claim its
viability.
Problem Statement: Let y(n) be a noise corrupted signal x(n).
Mathematically, y(n) = x(n) + v(n) where x(n) and v(n) are
independent; Your algorithm should be able to cancel out the v(n)'s
contribution.
Definitions: The k-th order cumulant of a process {X(t)} is given as
Cum_k(x)=E{x(t+T_1)x(t+T_2)...x(t+T_k-1)} where T_i are time lags. You
can easily make out that auto-correlation is nothing but second-order
cumulant. We need to work at third-order cumulant and the effort
includes extending auto-correlation based algo to third order cumulant
given by
Cum_3(x)=E{x(t+T_1)x(t+T2)x(t+T3)}
Property: The particular property of cumulant that is being exploited
here is that for all gaussian processes, third or higher cumulants are
identically zero.
Solution: x(n) and v(n) are independent processes. Thus, for
y(n)=x(n)+v(n), Cum_k(y)=Cum_k(x)+Cum_k(v).
While, Cum_2(v) for Gaussian processes is not zero, thereby
rendering the estimates or results, noisy. But Cum_3(v) is identically
zero for all Gaussian processes.
Thus, Cum_3(y)=Cum)_3(x)
So, all algos you develop based on HOS are immune to Gaussian noise.
PS:- For non-Gaussian noise you ought to know degree of Gaussiannity
and then may be you will have to go to even higher order.
Various researchers have worked on HOS in the last decade. Jerry
Mendel and C.L. Nikias have some very good Tutorial Papers. Harish
Parthasarathy has worked towards extending algorithms like MUSIC and
ESPRIT to higher orders.
References:
[1]. J.M.Mendel "Tutorial on higher order statistics in signal
processing and system theory" Proc. IEEE vol.79 Mar. 1991.
[2] Harish Parthasarathy, Surendra Prasad and Shiv Dutt Joshi "An
ESPRIT Like Method for Quadratic Phase Estimation" IEEE Trans. on
Signal Processing pp. 2436 - 2360 Oct.1995.
Regards
Raman Arora
Hughes Software Systems
--
I stay my haste, I make delays, For what avails this eager pace?
Article: 38406I'm producing some back-annotated simulation using .sdf file, what you suggest me to use, minimal, average or maximal ???Article: 38407
Hi, I'm involved in design of board,we planned to use SPARTAN-II and SPARTAN-XL seies device, For configuration we planned to use slave serial mode and Boundary scan(this will be used only during testing phase of the board) , I have following doubt regarding Boundary scan, I am going to use 2 spartan-II and 2 spartan-XL device First and second device in the chain is spartan-II ,third and fourth device in the chain is spartan-XL device 1.Can spartan-II and spartan-XL can be connected in JTAG chain(like TDO of Spartan-II connected to TDI of Spartan-XL device). 2.If the above is possible,then while i'm using Boundary scan mode for configurtaion what should be the mode pin setting for all device in the chain (spartan-II device has mode pin seeting for Boundary scan mode where as Spartan-XL device does not have any setting what should i do) Regards, BalaArticle: 38408
i do a divider,(a/b),the result is c.should i declare the c is wire or reg or integer?Article: 38409
Hi, you should at least run a min and a max simulation. Min usually checks for hold time violations, max for setup violations. To be sure your design works properly you should run simulations with all 3 different timings. You can also verify your timing statically with the timing analyzer which comes with your FPGA place and route software. At least Xilinx Tools have this ability, I'm not sure about other FPGA vendor tools since I only use Xilinx FPGAs. HTH Ansgar -- Attention reply address is invalid. Please remove _xxx_ Antonio <dottavio@ised.it> schrieb in im Newsbeitrag: fb35ea96.0201140030.35ac53d0@posting.google.com... > I'm producing some back-annotated simulation using .sdf file, what you > suggest me to use, minimal, average or maximal ???Article: 38410
> The smallest reconfiguration unit of a Xilinx Virtex is a frame. True, check XAPP 151 for even more info on Configuration Architecture. Alex :)Article: 38411
Hello,
I don't understand why an Signal toggles at the rising
edge, because I want to toggle it at an falling edge.
Can someone help me ?
Thanks
Martin.Fischer@fzi.de
Phasen : process (MSP_CLK, Befehl_Empfangen)
Begin
if (Befehl_Empfangen='0' and Empfangs_Buffer(3 downto 0)="0000") then
Zustand <= Zustand0; Speicherdummy(3 downto 0)<="0000";
elsif falling_edge(Befehl_Empfangen) then
case Zustand is
when Zustand0 => Speicherdummy(3 downto 0)<="0001";
if Empfangs_Buffer(3 downto 0)="0001" then Zustandsfehler<='0';
Speicherdummy(3 downto 0)<="0001";
Zustand <= Zustand1;
else Zustandsfehler<='1';
end if;
when Zustand1 => ...
Article: 38412Hi there, I am designing functions in VHDL for a Virtex II, that are likely to be re-used (FPGAExpress+Xilinx 4.1i). I have seen that it is possible to do hard macros with the Xilinx FPGA Editor. The procedure is quite long. It consists in 'unplacing' the pads and inserting macro internal pins. Once it is all done, then you can reuse it by instantiating a black box in some VHDL code. That's the procedure I have found in a Xilinx application note. When unplacing existing pads, the tool also removes some routing and inserts a green dot where the removed routes starts from. The main problem is to find the green dot, to replace it by macro internal pins. Sometimes, it is almost impossible to find those dots when there are inout pads or when Flip-Flops are inserted in pads. The procedure is really long, especially when there are about 100 I/O on the block to be turned into a hard macro. Does anyone know any alternative way to generate hard macros, or similar blocks ? Thanks. Philippe.Article: 38413
> The pieces mentioned as missing are only really missing if you are > trying to do all this at design time using mainstream tools. If you > defer routing to run-time and use JBits, then the fact that routes run > through the section you want to use doesn't really matter - it's like > implementing your design on an FPGA with more limited routing > resources. The router will find a way. Ok, I admitt, if you go all way using JBits and no conventional design tools, you won't have this problem. But what if you want to use conventional tools? For implementing large circuits, which are not primarily dataflow oriented, but have also a larger controler part, you might be forced to use conventional tools. Otherwise you will have to do all statemachine implementation (state encoding, implementationo and minimization of transition- and output-functions) yourself.. which is very tedious even for small statemachines.. Is there a way to let the VHDL/Verilog design tools synthesize your circuit, and than read back the resulting netlist into JBits and use JBits for implementation and routing? For instance by instantiating the netlist primitives and using JRoute2 for routing? Has anybody done this in an automated way? What about timing? The standard synthesis tools can check for meeting all timing constraints. If I do all routing using JBits, how can I guarantee, that the timing constraints are met? Regards, ChristianArticle: 38414
Philip and Alex, thanks for your explanation and your correction concerning the smallest reconfiguration unit of a Xilinx Virtex. Best Regards MichaelArticle: 38415
On Mon, 14 Jan 2002 16:15:17 +1000, Peter Ormsby wrote: > David Findlay <david_j_findlay@yahoo.com.au> wrote in message > news:pan.2002.01.14.07.54.25.119281.7489@yahoo.com.au... >> Well what I'd hope to be doing is creating a simple computer, but with > specialised logic >> sections to speed up certain operations that take a while on conventional > processors. So I >> suppose although it wouldn't be as fast on some functions, it could be > much faster on others. >> I'm after preformance on complex simulations so physics logic would be > useful. >> >> David > > David, > > One thing I didn't mention about Altera's Nios processor in my last posting: the latest > incarnation allows you to add custom instructions to the processor core. It's all integrated > into the tool flow so it looks relatively painless (although I haven't used the custom > instructions myself, so I can't speak from first-hand experience). Here's the web link: Sounds cool. Thanks, DavidArticle: 38417
a) I implemented my design and during back annotation I've the following error from Aldec 5.1, what I've to do ?? # : Time: 540114466 ps, Iteration: 0, Instance: /U1_U1_U2_out_mult_4_Q. # : WARNING: */X_SUH SETUP High VIOLATION ON I WITH RESPECT TO CLK; # : Expected := 1.678 ns; Observed := 0 ns; At : 540208.728 ns # : Time: 540208728 ps, Iteration: 0, Instance: /GSUH_to_SRRC_I_clk_1. # : WARNING: */X_FF SETUP Low VIOLATION ON I WITH RESPECT TO CLK; # : Expected := 0.511 ns; Observed := 0.06 ns; At : 540211.434 ns # : Time: 540211434 ps, Iteration: 0, Instance: /U1_U1_U2_out_mult_4_Q. # : WARNING: */X_SUH SETUP Low VIOLATION ON I WITH RESPECT TO CLK; # : Expected := 1.678 ns; Observed := 0 ns; At : 540596.6 ns # : Time: 540596600 ps, Iteration: 0, Instance: /GSUH_to_SRRC_I_clk_1. # : WARNING: */X_FF SETUP High VIOLATION ON I WITH RESPECT TO CLK; # : Expected := 0.511 ns; Observed := 0.06 ns; At : 540599.306 ns b) What is the right flow, I use Aldec 5.1 together with Synplify 7.02 but if I choose to use the GUI instead of the batch no folders are created when I close Synplify.Article: 38418
Dear Sir, I am facing the problem in Xilinx3.1i Floorplanning tool,I am not giving any constraints But tool reporting - " Unable to obey design constraints (LOC = CLB_R13C30.S0) which require the combination of the following symbols into a single I/O component: PAD symbol "Y<2>.PAD" (Pad Signal = Y<2>) BUF symbol "U99" (Output Signal = n104) PAD symbol "Y<3>.PAD" (Pad Signal = Y<3>) The symbol Y<2>.PAD has a constraint (LOC=CLB_R13C30.S0) that specifies an illegal physical site for the component. Please correct the constraint value. Please correct the design constraints accordingly." Pls give solution regards ChandrakiranArticle: 38419
test.Article: 38420
Just to mention... BSDL file for ATmega128 is available. Damir "DG_1" <dgacina@san.rr.com_no.spam> wrote in message news:lbp08.100459$AI.26190323@typhoon.san.rr.com... > Thanks 'rickman'. > The only problem I 'foresee' is the fact that IAR Kickstart doesn't > have any capability of adding/editing BSDL files (or I missed something). > Therefore, I don't see the way how to use debugging features > of IAR Kickstart when _more_ than one chip is in the same chain. > I guess, designers of IAR's tool-set didn't (intentionally?) > though-out that possibility. Also, I guess, from Xilinx's perspective, > having MSP430 in the same chain is no big deal, just add BSDL > file for TI's part to Xilinx's 'JTAG programmer' tool. > In the past I've used JTAG to chain-up devices (Xilinx, Lattice) > but always from the same manufacturer, I've never mixed-up > different chips, from different manufacturers, neither I added MPUs > into the chain. now I guess the only way to check it up is to make > the actual circuitry and then 'everything is in God's hands'. > (Well, the same problem is applicable to Atmel AVmega128 > to be chained-up with other JTAG-capable chips) > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > news:3C414ACF.EA8194EA@yahoo.com... > > DG_1 wrote: > > > > > > Hi there, > > > Has anybody tried to chain-up a MSP430 with any of JTAG-capable > > > Xilinx chips and be able to programm both of them without problem(s) > > > (MSP430 via IAR KickStart, Xilinx via JTAG programmer)? > > > Or (re-arranged question):: > > > Does IAR Kick-Start still recognizes MSP430 and/or allows other > > > devices (other than MSP430) to be chained-up via JTAG? > > > > > > Thanks in advance, > > > -- D.G. > > > > > > I will be doing exactly this in a month or two. I am building a board > > with a TMS320C6711, an MSP430F148/9, an XC2S150E and an XCR3256XL all in > > one JTAG chain. Actually, I may leave the MSP430F148/9 out of the chain > > depending on the answers to the questions I will be asking the vendors. > > But I really want the rest of it in a single chain so that I can do > > boundry scan testing on it all. The MSP430F148/9 will not be quite so > > integrated into the rest of the board, so it does not have to be tested > > that way. It is also important to be able to burn software into it > > regarless of the state of the board. This will be used for initial board > > test too. I am even considering using the MSP430F148/9 as a JTAG > > interface for the JTAG chain. But we will see if I can get it all to > > work together. > > > > If you have any results yourself, please let me know. Thanks! > > > > -- > > > > Rick "rickman" Collins > > > > rick.collins@XYarius.com > > Ignore the reply address. To email me use the above address with the XY > > removed. > > > > Arius - A Signal Processing Solutions Company > > Specializing in DSP and FPGA design URL http://www.arius.com > > 4 King Ave 301-682-7772 Voice > > Frederick, MD 21701-3110 301-682-7666 FAX > > > >Article: 38421
The buttons don't work in the main window, they do work in the editor windows. Bryan "Duane Clark" <junkmail@junkmail.com> wrote in message news:3C3F99BE.5020904@junkmail.com... > Bryan wrote: > > ... I am now doing all of my routes and fpga_editor work on the linux box > > and saving a lot of time. > > Just out of curiosity, do the toolbar buttons in the main window of > fpga_editor work for you? If they do, what version of wine and Linux are > you using? > > For me (current wine cvs and RH 6.2), the toolbar buttons in the main > window do not work, and there does not appear to be any other way to > select the particular pips and lines etc that are desired. Oddly enough, > the toolbar buttons do work in the popup windows for the slices and > iobs. Everything else in fpga_editor seems to work fine. > > I had not tried a run time comparison, but since I can dual boot the > same machine, maybe I will try that one of these days. > > Duane >Article: 38422
No, the new grid system is only for RPM macro creation. You can locate the resulting macro using an RLOC_ORIGIN constraint, but this must be done using a site name. Bret Kevin Neilson wrote: > Hmmm, this sounds really promising. I might have to wait for the > documentation though. So I can use this alternative grid system for > location constraints in the UCF? > > -Kevin > > "Bret Wade" <bret.wade@xilinx.com> wrote in message > news:3C3CEAB2.50CF73DF@xilinx.com... > > Hi Kevin, > > > > The 4.1i release (SP2 needed) contains a new feature that you may find > useful. > > It supports a new grid system called the RPM Grid. It's a combined grid > system > > that allows you to create heterogeneous relocatable RPMs. With the > standard > > grid, if you created an RPM with BRAMs , Slices and IOBs, the relative > locations > > between the different component types would shift as the macro was moved. > This > > doesn't occur with the RPM Grid. > > > > To use the new grid system, create the RPM as usual, but using the > alternative > > coordinate system. The RPM needs to also contain the attribute > "RPM_GRID=GRID" > > to identify the coordinate system. This attribute can be placed on any > symbol in > > the macro. The coordinate system can be viewed in FPGA Editor. If you > select a > > Site in FED, note that an RPM_GRID coordinate is printed in the history > window. > > > > Sorry, there's no documentation yet. I'm working on an appnote. > > > > Regards, > > Bret Wade > > Xilinx Product Applications > > > > Kevin Neilson wrote: > > > > > In my opinion, Xilinx messed up when creating their coordinate systems. > > > They could have easily created a system in which the BRAM, slice, and > IOB > > > coordinates were all related, but they refused to do so. The result > makes > > > the creation of placement scripts extremely difficult. For example, if > you > > > wish to make a script that places registers next to a BRAM, it is very > > > difficult, because there is no relation between the BRAM at x,y and the > > > coords of the slice that surround it. In fact, this is even different > for > > > every part. The same is true for the IOBs that sit next to slices. A > > > better coordinate system would have helped a lot in the development of > cores > > > which can be placed anywhere in any part. Instead, if you have a core > that > > > requires IOBs close to core slices, you can't include the IOB relative > > > locations in the core and have to hand-place for each situation. That's > not > > > how a core is supposed to work. > > > > > > "axilon" <axilon@attbi.com> wrote in message > > > news:3C3BE93D.8050002@attbi.com... > > > > How can I relate the package pin names and Slice XY locations in > Xilinx > > > > Virtex2 device? I need it to put LOC constraint to IOB. > > > > I looked into the pinout_text_files at DataSource CD-ROM but its > > > > Slice X/Y Location data doesn't match with Physical names appeared at > > > > FPGA editor screen. For an example, in 2v40cs144.txt file, X15Y14 > > > > location has 6 pads (PAD21-PAD26) - that doesn't make sense since > > > > each Slice location can have max 4 pads. Am I just discovered > > > > documentation error? > > > > Can any Xilinx folks out there answer my question? > > > > TIA > > > > Ax > > > > > >Article: 38423
This is a Map error indicating that you have LOC constraints on one or more pads that constrain them to slice locations. That's not a valid location for pads. Bret Neither of these Chandrakiran wrote: > Dear Sir, > I am facing the problem in Xilinx3.1i Floorplanning tool,I am not giving any constraints But tool reporting - > " Unable to obey design constraints (LOC = CLB_R13C30.S0) which require the combination of the following symbols into a single I/O component: > PAD symbol "Y<2>.PAD" (Pad Signal = Y<2>) BUF symbol "U99" (Output Signal = n104) PAD symbol "Y<3>.PAD" (Pad Signal = Y<3>) The symbol Y<2>.PAD has a constraint (LOC=CLB_R13C30.S0) that specifies an illegal physical site for the component. Please correct the constraint value. Please correct the design constraints accordingly." > Pls give solution > regards > ChandrakiranArticle: 38424
I've taken over a project mid-stride for another engineer who has taken ill, and I have a problem. Basically I have a schematic capture produced in Protel 99SE which represents the logic which needs to be implimented by a Xilinx XC2S200 FPGA on the new board we are building. In previous projects I believe the schematics were saved from Protel as Xilinx XNF 5.0 files then implimented using XACT Step 2.1. XACT Step 2.1. however doesn't seem to support the chip we are now using, as it does not show up in the "Set Part" dialog. Could some one point me in the right direction of what I need to do to impliment this design? Thanks in advance!
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