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Hi, I Have to design a complex prototype with LATTICE isp chips. For to begin I draw a very simple schematic (a NAND gate) with the starter software for to learn to use the development system, and to test it. Then I compiled and downloaded the JEDEC into the isp Chip with a cable done by myself. The download and the verify process seems to be o.k. but the chip don't work: all input-output pin of the chip (output-nand of my example included) seems to be in a 3V floating state. (supply is 5V) What is wrong? The chip I have used is an LSI 1032E-70LJ The compiler is set to a 1032EA-100 because I have not foud the 70LJ in the device's list. maybe this wrong? thank you in advance Mariani Raffaele.Article: 35726
On the LATTICE web site I found ispDesignEXPERT Starter software but I couldn't download the 4 files (54Mbytes).So I am looking for the sofware for ispLSI 1016 that was include in the Starter kit describes by ELEKTOR (french version n° 197 november 1994) : pDS 1016 (pLSI / ispLSI development system ) ispCODE hermine.kowka@laposte.netArticle: 35727
Leo Breuss <lbreuss-nospam@scs.ch> wrote in message news:3BCB0754.68DA27D7@scs.ch... > But: the path from Reg1 to Reg3 has even more delay than 4 ns. It should be > allowed to take 8ns. > I think your solution works. > I have to try an even more elegant and precise idea: > TIMESPEC "TS_Sel_path" = FROM FFS(Reg1*) 8.000; > this sets on all pathes originating at FFs Reg1* a TIMESPEC of 8 ns. > Do you think this could work? (I do not care if setup/hold of Reg3 is violated) Sorry Leo, I am losing the direction here a bit, but: I think you can only allow 8ns if you are unconcerned about cycle be cycle mux control and just want the tool to give you correct delay from Reg2 to Reg3 > > Maybe it would be better to treat even the the > > inverse clock as a totally asynchrous one and synchronise the enable to the > > clk2 domain before applying it to the mux chain using 2 regs as per Mikes > > suggestion. > > You're right. If only I had enough ressources in the FPGA... But the question > for timing constraints would be the same. The problem is just shifted in front > of the synchronizing FFs. Sure, but then the 'tricky' signal only has a fan out of 1 - much easier for the tools to place then feeding all the muxes (32) Regards, FredArticle: 35728
Falk wrote: > The PLL in the ALTERA ICs is a (P)hase locked loop, which uses a VCO to generate the output signal. A PLL can do clock rate conversion with (almost) any arbitrary conversion factor, where the DLL (D)elay locked loop in the Xilinx devices can only divide by 1.5,2,2.5,3,4,5,8,16 and double the input frequency. <snip> Let me correct some misconceptions here. PLLs or DLLs had to be added to the ever larger FPGAs to combat ( = completely eliminate ) the clock distribution delay. Without PLL/DLLs, the larger chips would have unpredictable input set-up/hold times, and abominably long clock-to-output delays. But that is all fixed now; big chips can be as fast as small ones, since the clock distribution delay can be eliminated. As to the difference between PLL and DLL, it is undisputed that a well-designed PLL in a low-noise environment ( the caveats show my Xilinx background here ) can reduce input jitter, while a DLL inherently passes the jitter on. It is also undisputed that a DLL is inherently more robust, less sensitive to ground and Vcc noise, and does not require its private supply connections. I just finished writing an article for our techXclusives and we just updated the Virtex-II Handbook ( data sheet and user guide. See it on the web next week ). So, here is what the Virtex-II Digital Clock Manager can do ( and there are between 4 and 12 identical but independent DCMs on a Virtex-II chip ): •eliminate the clock distribution delay and, with clock mirroring, perhaps even the board delay, •correct the clock duty cycle to 50-50, •provide four clock phases ( 0, 90, 180, 270 degrees ) •provide two double-frequency outputs with opposite phase •keep all these independent outputs phase-aligned •on a separate output divide the clock by either 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16. •on another output multiply and divide the input frequency simultaneously by any integer multiplier and divisor from 2 to 32. ( for example multiply a 200 MHz input by 32 and divide it by 25 for a 256 MHz output ) •and - best of all- create a programmable phase shift, described as a multiple of the clock period divided by 256, that affects all outputs simultaneously. And this phase shift can even be incremented and decremented during operation. Interesting possibilities to adjust input or output clocks either by configuration, or adaptively, to optimize I/O performance. Sorry for the long posting, but I find this really exciting. It's more than just a DLL. And, please, don't accuse me of marketing. This is meant to be engineering information ! Peter Alfke, Xilinx ApplicationsArticle: 35729
--------------1B7FE0667DBB1029B584DBC2 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit I wish to emphasize Peter's point, "We have not come to bury PLL's, but to praise them." But when it comes down to the dirty real world, PLL's are fussy, and DLL's are not. That doesn't mean that PLL's are any less useful: they are required in many cases. http://www.icst.com/pdf/ics8735-01.pdf Is a good example of a PLL. Separate package, can control the singal integrity, power supplies, etc. Drop that 100 to 300 ps of jitter from that FPGA based PLL right down to practically nothing for those timing critical signals. http://www.xilinx.com/products/virtex/techtopic/vtt013.pdf Oh, and even better for getting rid of the residual jitter from a DCM. The DCM jitter is all random at extremely high frequencies which get attenuated 100 fold by a good PLL. Austin Peter Alfke wrote: > Falk wrote: > > > The PLL in the ALTERA ICs is a (P)hase locked loop, which uses a VCO to generate the output signal. A PLL can do clock rate conversion with (almost) any arbitrary conversion factor, where the DLL (D)elay locked loop in the Xilinx devices can only divide by 1.5,2,2.5,3,4,5,8,16 and double the input frequency. <snip> > > Let me correct some misconceptions here. > > PLLs or DLLs had to be added to the ever larger FPGAs to combat ( = completely eliminate ) the clock distribution delay. Without PLL/DLLs, the larger chips would have unpredictable input set-up/hold times, and abominably long clock-to-output delays. But that is all fixed now; big chips can be as fast as small ones, since the clock distribution delay can be eliminated. > > As to the difference between PLL and DLL, it is undisputed that a well-designed PLL in a low-noise environment ( the caveats show my Xilinx background here ) can reduce input jitter, while a DLL inherently passes the jitter on. It is also undisputed that a DLL is inherently more robust, less sensitive to ground and Vcc noise, and does not require its private supply connections. > > I just finished writing an article for our techXclusives and we just updated the Virtex-II Handbook ( data sheet and user guide. See it on the web next week ). > > So, here is what the Virtex-II Digital Clock Manager can do ( and there are between 4 and 12 identical but independent DCMs on a Virtex-II chip ): > > •eliminate the clock distribution delay and, with clock mirroring, perhaps even the board delay, > •correct the clock duty cycle to 50-50, > •provide four clock phases ( 0, 90, 180, 270 degrees ) > •provide two double-frequency outputs with opposite phase > •keep all these independent outputs phase-aligned > •on a separate output divide the clock by either 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16. > •on another output multiply and divide the input frequency simultaneously by any integer multiplier and divisor from 2 to 32. ( for example multiply a 200 MHz input by 32 and divide it by 25 for a 256 MHz output ) > •and - best of all- create a programmable phase shift, described as a multiple of the clock period divided by 256, that affects all outputs simultaneously. And this phase shift can even be incremented and decremented during operation. Interesting possibilities to adjust input or output clocks either by configuration, or adaptively, to optimize I/O performance. > > Sorry for the long posting, but I find this really exciting. It's more than just a DLL. > And, please, don't accuse me of marketing. This is meant to be engineering information ! > > Peter Alfke, Xilinx Applications --------------1B7FE0667DBB1029B584DBC2 Content-Type: text/html; charset=iso-8859-1 Content-Transfer-Encoding: 8bit <!doctype html public "-//w3c//dtd html 4.0 transitional//en"> <html> I wish to emphasize Peter's point, <p>"We have not come to bury PLL's, but to praise them." <p>But when it comes down to the dirty real world, PLL's are fussy, and DLL's are not. <p>That doesn't mean that PLL's are any less useful: <b>they are required in many cases.</b> <p> <a href="http://www.icst.com/pdf/ics8735-01.pdf">http://www.icst.com/pdf/ics8735-01.pdf</a> <p>Is a good example of a PLL. Separate package, can control the singal integrity, power supplies, etc. Drop that 100 to 300 ps of jitter from that FPGA based PLL right down to practically nothing for those timing critical signals. <p> <a href="http://www.xilinx.com/products/virtex/techtopic/vtt013.pdf">http://www.xilinx.com/products/virtex/techtopic/vtt013.pdf</a> <p>Oh, and even better for getting rid of the residual jitter from a DCM. The DCM jitter is all random at extremely high frequencies which get attenuated 100 fold by a good PLL. <br><br> Austin <p>Peter Alfke wrote: <blockquote TYPE=CITE>Falk wrote: <p>> The PLL in the ALTERA ICs is a (P)hase locked loop, which uses a VCO to generate the output signal. A PLL can do clock rate conversion with (almost) any arbitrary conversion factor, where the DLL (D)elay locked loop in the Xilinx devices can only divide by 1.5,2,2.5,3,4,5,8,16 and double the input frequency. <snip> <p>Let me correct some misconceptions here. <p>PLLs or DLLs had to be added to the ever larger FPGAs to combat ( = completely eliminate ) the clock distribution delay. Without PLL/DLLs, the larger chips would have unpredictable input set-up/hold times, and abominably long clock-to-output delays. But that is all fixed now; big chips can be as fast as small ones, since the clock distribution delay can be eliminated. <p>As to the difference between PLL and DLL, it is undisputed that a well-designed PLL in a low-noise environment ( the caveats show my Xilinx background here ) can reduce input jitter, while a DLL inherently passes the jitter on. It is also undisputed that a DLL is inherently more robust, less sensitive to ground and Vcc noise, and does not require its private supply connections. <p>I just finished writing an article for our techXclusives and we just updated the Virtex-II Handbook ( data sheet and user guide. See it on the web next week ). <p>So, here is what the Virtex-II Digital Clock Manager can do ( and there are between 4 and 12 identical but independent DCMs on a Virtex-II chip ): <p>•eliminate the clock distribution delay and, with clock mirroring, perhaps even the board delay, <br>•correct the clock duty cycle to 50-50, <br>•provide four clock phases ( 0, 90, 180, 270 degrees ) <br>•provide two double-frequency outputs with opposite phase <br>•keep all these independent outputs phase-aligned <br>•on a separate output divide the clock by either 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16. <br>•on another output multiply and divide the input frequency simultaneously by any integer multiplier and divisor from 2 to 32. ( for example multiply a 200 MHz input by 32 and divide it by 25 for a 256 MHz output ) <br>•and - best of all- create a programmable phase shift, described as a multiple of the clock period divided by 256, that affects all outputs simultaneously. And this phase shift can even be incremented and decremented during operation. Interesting possibilities to adjust input or output clocks either by configuration, or adaptively, to optimize I/O performance. <p>Sorry for the long posting, but I find this really exciting. It's more than just a DLL. <br>And, please, don't accuse me of marketing. This is meant to be engineering information ! <p>Peter Alfke, Xilinx Applications</blockquote> </html> --------------1B7FE0667DBB1029B584DBC2--Article: 35730
On the LATTICE web site I found ispDesignEXPERT Starter software but I couldn't download the 4 files (54Mbytes).So I am looking for the sofware for ispLSI 1016 that was include in the Starter kit describes by ELEKTOR (french version n° 197 november 1994) : pDS 1016 (pLSI / ispLSI development system ) ispCODE hermine.kowka@laposte.netArticle: 35731
Hi Mariani - the 1032E and 1032EA do not use the same programming algorithm - I would suggest contacting the local Lattice FAE or Distributor - the FAE can help with getting the tool to recognize the 1032E - Michael Thomas LSC SFAE New York/New Jersey >The chip I have used is an LSI 1032E-70LJ >The compiler is set to a 1032EA-100 because I have not foud the 70LJ >inArticle: 35732
Jan Gray wrote: <snip> > If you figure a CMOS 2-input NAND is four transistors, then at 200 > transistors per NAND, it works out to a 50-1 'transistor overhead' for > programmability. That sounds bad, but remember that FPGA transistors are > typically manufactured in the latest and greatest processes, so often they > are smaller, faster, and cheaper than ASIC transistors. <cut> > Jan Gray, Gray Research LLC > (A student of FPGA device architecture, not a practitioner.) Four other factors come into play when calculating effective gates. 1) FPGA's don't handle wide logic well. A 4 input multiplexer requires 3 LUT's yet a complex term of 4 variables is no problem. 2) Many FPGA's have built in fast ripple carry and flip/flops and block ram giving the illusion of free logic or larger resources than given FPGA has. A 32 bit hand placed RISC will fit but not a 8 bit HDL cpu design. 3) Routing logic often needs 1/3 to 1/4 of the LUT's wasted do to routing constraints. 4) Anti-fuse FPGA's are a whole different ballpark again. Ben Franchuk.Article: 35733
Hi,
What library component can I use for a SpartanXL bidirectional buffer? I
can't use IOBUF's with an XL, and I'm not sure what to use instead.
Thanks,
Dave
Article: 35734
The system gates are nothing more than a marketing figure to indicate how
much logic can go in the part. In the marketeer's ideal world, a circuit
done in an FPGA using 315K equivalent gates is equivalent to a 315K gate
ASIC. Read carefully the 10 paragraphs of small print that flash up on
the screen for 270 milliseconds.
The truth is, these marketing gates have been badly perverted by
oneupsmanship, to the point that on chip memory and extra features more or
less dominates the figure. A better measure of FPGA capability is a count
of the number of logic elements (consisting of a 4-LUT and flip-flop in
many devices), and then season that with any special features to the
extent that they BENEFIT YOUR application.
Dennis wrote:
> I am an ASIC Designer trying to understand FPGAs. While going through
> Xilinx Datasheets, I got some clues (although not fully understood)
> about the definition of System Gates Capability of a particular
> product. I wish to understand, How much Silicon is sacrificed for the
> sake of Programmability? , for example: For a 315K equivalent Gates in
> XC2V300, How Many ASIC Gates(2 input NAND) have been put in the
> Silicon????
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 35735
Yes, like your own PCI IP core, mine also worked fine at 33MHz even
though it didn't meet 33MHz PCI's timings.
I know that PCI bus running at 25MHz will give the PCI card more
timing margin, but already a lot of motherboards don't support 25MHz
PCI, and the specification asks for all 5V PCI cards to run at 33MHz,
so I am still trying to meet 33MHz PCI's timings.
Like you mentioned, I have noticed a lot of PCI chipsets (core
logic) or add-in cards don't implement data parity checking.
For example, a lot of Intel chipsets don't bother to implement data
parity checking.
In my own PCI IP core, I implemented data checking capability which
took some time to implement (because the data parity checker runs two
cycles behind the target sequencer), but during the implementation I
really felt stupid implementing it knowing that no one uses it.
Regards,
Kevin Brace (don't respond to me directly, respond within the
newsgroup)
Kolja Sulimma <kolja@sulimma.de> wrote in message news:<3BC837A6.EB7F5ABE@sulimma.de>...
> The timings you get from the timing analyzer are based on worst case supply voltage,
> temperature and the maximum load capacitance allowed on a PCI bus.
> Additionally the setup and clock-to-out specifications of the PCI standard are based on a PCI bus with maximum trace length,
> maximum number of slots and all slots populated.
>
> If you want to sell a PCI core you better have it meet the worst case timing specifiaction, but for your own experiments that
> is not necessary.
> The last compile of my own PCI core has a clock-to-pad of 13.5ns and a setup time of 9.3ns and runs stable at 33 MHz in a fully
> populated
> PCI-Bus.
>
> If you want to be on the safe side you can change the PCI clock frequency of you mainboard to 25MHz which will give you an
> extra 10ns margin that can be devided between setup and clock-to-out times.
> Also leaving some PCI slots empty should give you a couple of extra nanosecods.
> See chapter 4.3.5 of the PCI standard.
>
> Do not be too paranoid. It is perfectly normal for PCI boards to not to comply with the standard.
> (Thats probably one of the reasons why many PCs run unreliably.)
> - For example there existed PCI boards that only decoded 16-Bit of the IO address space.
> - Many boards do not signal parity errors.
> - I have an old VGA boards from a Compaq 75 MHz Pentium system. The board will only run at 25 MHz.
> - I have not seen a single 5V board that fulfilled the decoupling requirements of chapter 4.4.2.2
> an so on, and so on....
>
> Kolja Sulimma
Article: 35736Hello, I'm trying to multiplex Phillips I2C lines with either xilinx or altera. For those familiar with the protocol, during a byte transfer the receiver must send ACKs by pulling down the SDA line. Also, wait states can be inserted by holding down the SCL line. So basically i'm trying to build a bidirectional multiplexor which has open-drain pins. Currently, I use a bidir pin for the master, and inside the chip it is connected to an input and output buffer. The output buffer is a tristate buffer with its input tied to ground and an active low enable driven by the output logic. The input and output paths are demuxed and muxed, respectively, to "n" I2C in/outs. The problem with using open drain outputs in the fpga is that during an ACK phase, the master will drive the clock and wait to see if the SDA line is driven low by the slave. However, if the last transmitted data bit happened to be a zero, the zero will feed back to the tristate buffer of the transmitter and keep it low. Right now I have to implement some complex logic to "turn around" the bus and enable/disable the input buffers accordingly in anticipation of the slave device responding (or more importantly, not responding) with an ACK. Is there an easier way around this? Can I declare open drain bidirs in verilog and let Altera take care of the rest? :) Andy likes: brie oreos speeding in my $8k car dislikes: timing constraints waking up before noon having head on backwardsArticle: 35737
Nope, all FFs are being mapped into IOBs. I, however, have since managed to fix the problem be relaxing the Timing constraints to 5ns. It hence mapped the design to under 3.4ns, what I initially wanted!!!! adrian > It sounds like in the first case the output FFs were being mapped into the IOBs > but when you added the 20-bit output they weren't. Could you be in the > situation now where both the test output and the LS 6 bits of the real output > are being driven from the same FFs ? i.e. a victim of over-enthusiastic > optimisation by the synth/P&R tool(s). >Article: 35739
Peter If the input clock to the Digital Clock Manager is removed for a time greater than 100 ms (say 60 sec) , will the DCM output a locked clock when the input clock is re-applied ?. The Virtex and Virtex-E cannot handle an input clock which has been stopped for 100ms or more, without the DLL needing to be reset On Mon, 15 Oct 2001 10:00:16 -0700, Peter Alfke <peter.alfke@xilinx.com> wrote: > > >Falk wrote: > >> The PLL in the ALTERA ICs is a (P)hase locked loop, which uses a VCO to generate the output signal. A PLL can do clock rate conversion with (almost) any arbitrary conversion factor, where the DLL (D)elay locked loop in the Xilinx devices can only divide by 1.5,2,2.5,3,4,5,8,16 and double the input frequency. <snip> > >Let me correct some misconceptions here. > >PLLs or DLLs had to be added to the ever larger FPGAs to combat ( = completely eliminate ) the clock distribution delay. Without PLL/DLLs, the larger chips would have unpredictable input set-up/hold times, and abominably long clock-to-output delays. But that is all fixed now; big chips can be as fast as small ones, since the clock distribution delay can be eliminated. > >As to the difference between PLL and DLL, it is undisputed that a well-designed PLL in a low-noise environment ( the caveats show my Xilinx background here ) can reduce input jitter, while a DLL inherently passes the jitter on. It is also undisputed that a DLL is inherently more robust, less sensitive to ground and Vcc noise, and does not require its private supply connections. > >I just finished writing an article for our techXclusives and we just updated the Virtex-II Handbook ( data sheet and user guide. See it on the web next week ). > >So, here is what the Virtex-II Digital Clock Manager can do ( and there are between 4 and 12 identical but independent DCMs on a Virtex-II chip ): > >•eliminate the clock distribution delay and, with clock mirroring, perhaps even the board delay, >•correct the clock duty cycle to 50-50, >•provide four clock phases ( 0, 90, 180, 270 degrees ) >•provide two double-frequency outputs with opposite phase >•keep all these independent outputs phase-aligned >•on a separate output divide the clock by either 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16. >•on another output multiply and divide the input frequency simultaneously by any integer multiplier and divisor from 2 to 32. ( for example multiply a 200 MHz input by 32 and divide it by 25 for a 256 MHz output ) >•and - best of all- create a programmable phase shift, described as a multiple of the clock period divided by 256, that affects all outputs simultaneously. And this phase shift can even be incremented and decremented during operation. Interesting possibilities to adjust input or output clocks either by configuration, or adaptively, to optimize I/O performance. > >Sorry for the long posting, but I find this really exciting. It's more than just a DLL. >And, please, don't accuse me of marketing. This is meant to be engineering information ! > >Peter Alfke, Xilinx Applications > > > GraemeArticle: 35740
"AH" <akha@home.com> writes: <snpi> > Can I declare open drain bidirs in verilog and let > Altera take care of the rest? :) > You should be able to. I've done it thusly in VHDL (using two internal signals may not be strictly necessary). The signals are std_ulogic and the pin is INOUT stdlogic. Perhaps a verilogger can assist you further if required - sorry! SCL_IN_signal <= SCL_pin; SCL_pin <= '0' when SCL_OUT_signal = '0' else 'Z'; This synthesises to a birdirectional pin with an open-drain driver. > Andy > > likes: brie oreos speeding in my $8k car > > dislikes: timing constraints waking up before noon having head on > backwards My timing constraints are always up too early as well :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Automotive Technical Centre, Solihull, UKArticle: 35741
Dennis ha scritto nel messaggio <24f80317.0110152020.5d055699@posting.google.com>... >I am an ASIC Designer trying to understand FPGAs. While going through >Xilinx Datasheets, I got some clues (although not fully understood) >about the definition of System Gates Capability of a particular >product. I wish to understand, How much Silicon is sacrificed for the >sake of Programmability? , for example: For a 315K equivalent Gates in >XC2V300, How Many ASIC Gates(2 input NAND) have been put in the >Silicon???? Take a glance here http://209.67.241.58/reg/1998/080398/16cs.htmArticle: 35742
Dear Peter Your Explanations on DLL & PLL clarified most of my doubts barring a few: 1. Are the Features(mentioned by You) Unique to DLL(or Xilinx)? 'coz Recently I read somewhere that ALTERA also provides Fine Phase Shifting capabilities in its APEX II Family......PLEASE COMMENT.... 2. What is the Usage of the 50% Duty-Cycle Correction Capability offered by Virtex II DCM? Regards Gautam Peter Alfke <peter.alfke@xilinx.com> wrote in message news:<3BCB161F.6E691E11@xilinx.com>... > Falk wrote: > > > The PLL in the ALTERA ICs is a (P)hase locked loop, which uses a VCO to generate the output signal. A PLL can do clock rate conversion with (almost) any arbitrary conversion factor, where the DLL (D)elay locked loop in the Xilinx devices can only divide by 1.5,2,2.5,3,4,5,8,16 and double the input frequency. <snip> > > Let me correct some misconceptions here. > > PLLs or DLLs had to be added to the ever larger FPGAs to combat ( = completely eliminate ) the clock distribution delay. Without PLL/DLLs, the larger chips would have unpredictable input set-up/hold times, and abominably long clock-to-output delays. But that is all fixed now; big chips can be as fast as small ones, since the clock distribution delay can be eliminated. > > As to the difference between PLL and DLL, it is undisputed that a well-designed PLL in a low-noise environment ( the caveats show my Xilinx background here ) can reduce input jitter, while a DLL inherently passes the jitter on. It is also undisputed that a DLL is inherently more robust, less sensitive to ground and Vcc noise, and does not require its private supply connections. > > I just finished writing an article for our techXclusives and we just updated the Virtex-II Handbook ( data sheet and user guide. See it on the web next week ). > > So, here is what the Virtex-II Digital Clock Manager can do ( and there are between 4 and 12 identical but independent DCMs on a Virtex-II chip ): > > •eliminate the clock distribution delay and, with clock mirroring, perhaps even the board delay, > •correct the clock duty cycle to 50-50, > •provide four clock phases ( 0, 90, 180, 270 degrees ) > •provide two double-frequency outputs with opposite phase > •keep all these independent outputs phase-aligned > •on a separate output divide the clock by either 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6, 6.5, 7, 8, 9, 10, 11, 12, 13, 14, 15, or 16. > •on another output multiply and divide the input frequency simultaneously by any integer multiplier and divisor from 2 to 32. ( for example multiply a 200 MHz input by 32 and divide it by 25 for a 256 MHz output ) > •and - best of all- create a programmable phase shift, described as a multiple of the clock period divided by 256, that affects all outputs simultaneously. And this phase shift can even be incremented and decremented during operation. Interesting possibilities to adjust input or output clocks either by configuration, or adaptively, to optimize I/O performance. > > Sorry for the long posting, but I find this really exciting. It's more than just a DLL. > And, please, don't accuse me of marketing. This is meant to be engineering information ! > > Peter Alfke, Xilinx ApplicationsArticle: 35743
Hi,
if anybody wants to use coregen (ise4.1) under Linux, I have a modified
Solaris startup-script. With that patch, it runs with jdk1.3 (1.2
should work also, haven't tried it...). No wonder, a cheap 1.2GHz Athlon it
is much faster than a 296MHz Sun Enterprise...
http://wwwbode.cs.tum.edu/~acher/xilinx/
--
Georg Acher, acher@in.tum.de
http://www.in.tum.de/~acher/
"Oh no, not again !" The bowl of petunias
Article: 35744luigi funes wrote: > Dennis ha scritto nel messaggio > <24f80317.0110152020.5d055699@posting.google.com>... > >I am an ASIC Designer trying to understand FPGAs. While going through > >Xilinx Datasheets, I got some clues (although not fully understood) > >about the definition of System Gates Capability of a particular > >product. I wish to understand, How much Silicon is sacrificed for the > >sake of Programmability? , for example: For a 315K equivalent Gates in > >XC2V300, How Many ASIC Gates(2 input NAND) have been put in the > >Silicon???? > > Take a glance here > http://209.67.241.58/reg/1998/080398/16cs.htm Or here: http://www.fpgacpu.org/log/jan01.html#marketing_gates Also note, that it is common to count gate inputs, not gates. Your 2-Input NAND often counts as 2 "gates". This is true for ASIC and FPGA. Kolja SulimmaArticle: 35745
In comp.arch.fpga Ray Andraka <ray@andraka.com> wrote: > hamish@cloud.net.au wrote: >> In my experience, you can't instantiate Xilinx macros in your >> HDL code. Ngdbuild doesn't know anything about them (only >> primitives). > You can, but the edif files for any macros you use have to be found by > ngdbuild. That makes sense. Do you get netlists for each macro with the tools? I couldn't find them in Alliance 3.x, but they could be in Foundation. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 35746
Are there any hardware reference designs available for Virtex-II devices? I'm thinking recommended voltage regulators, JTAG connectors, serial connections for configuration connectors and EEPROMS, suggested status LEDs eg on /DONE; basically, everything that is automatically included by those who have been bitten once and are twice shy...I realise some of these are design dependant (eg supply current, PCB real estate), but nonetheless... I've had a bit of a search thru the Xilinx site & google'd, but nothing leapt out at me. Some suggestions as to extra bells & whistles would also be appreciated (eg interfacing AC coupled clocks to FPGA, etc) Any info/recommended devices on voltage level changing from 5V logic to the Virtex II devices also appreciated. The evauation boards are also attractive, but are feature overkill in many situations. Maybe a schematic for one of them?? regards, Paul T. CAE IncArticle: 35747
Hi folks, Is there a simple explanation beween those ? what are the advantages between them ? Links to implementations ? Thanks for your kind help ThiloArticle: 35748
"Dennis" <sacrosantus@yahoo.com> wrote in message news:24f80317.0110152020.5d055699@posting.google.com... > I am an ASIC Designer trying to understand FPGAs. While going through > Xilinx Datasheets, I got some clues (although not fully understood) > about the definition of System Gates Capability of a particular > product. I wish to understand, How much Silicon is sacrificed for the > sake of Programmability? , for example: For a 315K equivalent Gates in > XC2V300, How Many ASIC Gates(2 input NAND) have been put in the > Silicon???? I agree with Ray. But see also my weblog entry, marketing gates redux, at http://www.fpgacpu.org/log/jan01.html#marketing_gates. And read Peter Alfke's definitive posting on this subject at http://www.fpga-faq.com/archives/24400.html#24422. There Peter figured each logic cell would be worth about 12 ASIC gates (6 for the LUT and 6 for the FF). I thought a ballpark answer to the question might be interesting. Here follow some educated guesses, but none based upon actual data from actual shipping devices. In the book "Architecture and CAD for Deep-Submicron FPGAs", Betz, Rose, and Marquardt, Appendix B, pp.207-220, the authors provide a design for a generic CLB 'cluster' of four 4-LUTs and FFs that occupies 1678 'minimum width transistors'. (Each 4-LUT is 167 'MWT's.) That doesn't count the myriad transistors in each cluster's programmable interconnect (routing channels) -- configuration SRAM cells, switches, buffers etc.-- which I have read (somewhere) can be 4X more transistors than the CLB cluster itself. So let's say a tile with 4 4-LUTs, and its programmable interconnect, could require 8,000 transistors -- that's to implement about 40-something ASIC gates of logic and wiring -- call it 200 transistors per ASIC gate. If you figure a CMOS 2-input NAND is four transistors, then at 200 transistors per NAND, it works out to a 50-1 'transistor overhead' for programmability. That sounds bad, but remember that FPGA transistors are typically manufactured in the latest and greatest processes, so often they are smaller, faster, and cheaper than ASIC transistors. Let's check our figures another way. Last year, Steve Young of Xilinx was quoted [http://www.eetimes.com/story/OEG20000612S0025] as saying that *this year* Xilinx Virtex-II designs would get up into the 500 million transistors zone. Doing the math with a 2V6000 or a 2V10000 type device, this too indicates that several thousand transistors go into each logic cell (plus its share of the routing and RAM), or several hundred per equivalent ASIC gate. And here's a third approach. A 2V10000 requires a 33.5 Mb configuration bitstream. Assuming each bit is stored in a 6 transistor SRAM cell, and each configuration bit drives only a single pass transistor, (way too conservative), that's 33.5M*7 = at least 250 million transistors for the 123,000 LUTs = >2000 transistors per LUT, or again several hundred transistors per ASIC gate. Jan Gray, Gray Research LLC (A student of FPGA device architecture, not a practitioner.)Article: 35749
hi Has anybody stumbled upon vhdl code for a non-complex 1024 point FFT for a Spartan2? I am not sure that the SPARTAN2 has enough logic for this but then there might be an implementation out there?! Cheers Mo
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