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I missed something here. It seems that the original poster asked if multiple bit streams can be downloaded to a board, not a part. Since he said board I would say "Yes" is the correct answer. Download as many bit streams as you can fit memory on your board and then select between them. Bryan "Peter Alfke" <peter@xilinx.com> wrote in message news:3D6539C8.27BD703F@xilinx.com... > "No" is the correct answer. > The FPGA can only hold one configuration at any time. > Ramakrishnan wrote: > > > Hi, > > Is there a way i could download two bit streams to a single Xilinx > > FPGA board when starting up ?.Article: 46251
"Falk Brunner" <Falk.Brunner@gmx.de> schrieb im Newsbeitrag news:ak3327$1fip07$2@ID-84877.news.dfncis.de... > "dross" <zjuzhou@yahoo.com.cn> schrieb im Newsbeitrag > news:183113ed.0208220412.b2723e1@posting.google.com... > > Hello all: > > > > I want to make a develop board for Xilinx's FPGA(SP-II). > > Where can get s simple design use these chips? > > Why not buy one. They are cheap and ready to use. > > www.nuhorizon.com > www.burched.com > Hello, why not one from http://www.digilentinc.com/Catalog/system_boards.html . They have boards with XCS200(99$) and XCS200E(109$) including powersupply. I couldn't find anything cheaper. They have the schematics on the web. So you know exactly what you will get. By the way, I purchased one a few weeks ago and it runs without any problems. I am using the JTAG port for download with the Parallel Cable III Pod from Xilinx. The board has a switch to directly use the parallel port for download and/or interface, too. Best Regards HelmutArticle: 46252
Bryan, We are understandably chip-centric around here. You are right, nothing prevents you from downloading a thousand bitstreams to some memory, and then using them as you like. Peter is right is stating that the part doesn't have a shadow memory for another bitstream, and is not able to switch to a new bitstream, except through the reconfiguration feature, or complete configuration, which takes time to do. Austin Bryan wrote: > I missed something here. It seems that the original poster asked if > multiple bit streams can be downloaded to a board, not a part. Since he > said board I would say "Yes" is the correct answer. Download as many bit > streams as you can fit memory on your board and then select between them. > > Bryan > > "Peter Alfke" <peter@xilinx.com> wrote in message > news:3D6539C8.27BD703F@xilinx.com... > > "No" is the correct answer. > > The FPGA can only hold one configuration at any time. > > > Ramakrishnan wrote: > > > > > Hi, > > > Is there a way i could download two bit streams to a single Xilinx > > > FPGA board when starting up ?.Article: 46253
The question can misinterpreted easily. I am not sure what the original poster was after. Bryan "Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3D655E2E.114B7AA7@xilinx.com... > Bryan, > > We are understandably chip-centric around here. > > You are right, nothing prevents you from downloading a thousand bitstreams to > some memory, and then using them as you like. > > Peter is right is stating that the part doesn't have a shadow memory for > another bitstream, and is not able to switch to a new bitstream, except > through the reconfiguration feature, or complete configuration, which takes > time to do. > > Austin >Article: 46254
I have had private exchanges with Ram, who posted originally. I am sure that he means on-chip when he says on-board. Dangerous double-meaning, depending on whether you are a pc-board guy or a naval type... Peter Alfke ==================== Bryan wrote: > The question can misinterpreted easily. I am not sure what the original > poster was after. > > Bryan > > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message > news:3D655E2E.114B7AA7@xilinx.com... > > Bryan, > > > > We are understandably chip-centric around here. > > > > You are right, nothing prevents you from downloading a thousand bitstreams > to > > some memory, and then using them as you like. > > > > Peter is right is stating that the part doesn't have a shadow memory for > > another bitstream, and is not able to switch to a new bitstream, except > > through the reconfiguration feature, or complete configuration, which > takes > > time to do. > > > > Austin > >Article: 46255
Ramakrishnan wrote: > Is there a way i could download two bit streams to a single Xilinx > FPGA board when starting up ?. and also is it possible for a > controller to switch between the two bit streams while in operation?. Peter Alfke <peter@xilinx.com> writes: > "No" is the correct answer. [...] > And don't ask the other manufacturers, most of them cannot even do the > partial reconfiguration that Virtex offers. Actually, it appears that the latest family of parts from Lattice can do exactly what Ramakrishnan wants (aside from not being a "Xilinx FPGA board"). They have both SRAM and Flash configuration on board. At powerup, they load the SRAM from the flash, but you can download a new config to SRAM or Flash at any time. (Presumably downloading to SRAM will disrupt operation for the duration.) So he could download one config to SRAM, another to Flash, and then on demand have the part quickly load the Flash config into RAM. If he wants to be able to switch back and forth between configs, it's not going to be great for that, since he'll use up a cycle of Flash endurance every time he swaps.Article: 46256
"reply in the newsgroup" <deepfry.a.spammer.today@abuse.org> wrote in message news:ak3440$17a$1@slb6.atl.mindspring.net... >design a digital edge detector clocked > by the fast clock, use an instance for each slow clock input, and then > use the result as a clock enable for everything previously clocked by > the slow clocks but actually use the fast clock to drive all three clock > inputs of the IP? > That is a pretty clever way around the problem. Are the timing analyzers in the synthesis and vendor tools able to figure out the correct path delays? Or do you also have to go in and set a bunch of multi-cycle path constraints?Article: 46257
Hi all,
A question, what the fpga "speed level" as "...-5" means exactly?
"-5" device runs at more high speed than "-6" speed device or the
opponent?
How about the same speed level devices from different manufacturer?
Thanks in advance?
Daryl
Article: 46258Thanks. But I guess the problem is due to the fact that delay between source and destination pad is different. To explain say the delay between address to data is different between oe and data. And if oe delay is smaller than address delay then it may present old data first followed by new data. But how do I avoid this. I cannot get the same delay for everything. Also I cann't use in a clock process owing to the fact that the DSP timing doesn't allow this. Can you please suggest Anjan "Alan Fitch" <alan.fitch@doulos.com> wrote in message news:<6zlJQIcSCHA.2704@lucy.doulos.com>... > "Anjan" <anjanr@yahoo.com> wrote in message > news:5a5faf7b.0208220112.6f795975@posting.google.com... > > I am interfacing virtex to a DSP over io port. The read process > is as > > follows > > > > if(oe) then > > data=output(conv_integer(address_input)) > > else > > data=z > > > > > > This is fine in behavioral simulation(expected) but when I do a > PR > > simulation, I see some of the data lines going to X before > reaching > > the final value. How can I eliminate this. Also will this cause > any > > problem in the hardware. Any help is appreciated > > I guess it's a timing problem. If the tristate buffer is > implemented in the pin > and the OE signal is coming from the core, there is a long > propagation delay > from OE to the buffer. Hence there may be a difference between > when OE > changes and when the data changes. > > If you can register OE, then you can synchronise OE in the pin, as > in Virtex there is a flip-flop in the pin for the tristate control > line > as well as for the data. You would need to describe your "if" > statement in a clocked process to get that effect, and also make > sure > the P & R actually used the flip-flops in the pad. > > Alternatively, you should add a constraint to the P&R tools on the > time > from OE changing to the pin output to make it as small as > possible. > > Regarding problems, you will get transient current if both the > virtex > and the DSP drive the bus at the same time - I don't know if this > will do > any permanent damage to the devices. > > regards > > AlanArticle: 46259
hello friends i have stuck at a problem and need ur help.... i am trying to program xc9536xl using webpack. i am not getting any warnings or error messages from webpack at time of synthesis but when i download the design into the chip the design doesnot gives the expected results i.e. its functionality, is different where as everything works fine in simulation. What i mean to say is the tool is putting the hardware differently than expected..... please guide me how do i debug the code or how do i obtain the exactr resultsArticle: 46260
Hi there. The PPC405 core used e.g. in the PPC405CR device has a built-in SD-RAM controller. If we would choose to use a Virtex-2Pro instead of the 405CR how could we attach external SD-RAM (e.g. 64MByte) and what would be the memory bandwidth to the SD-RAM compared to the one of the 405CR ? What about using Linux on the 405 core in the Virtex-2Pro ? Regards, AndreasArticle: 46261
hi i'm new in this game need all the help I can get. I'm trying to do an optimised decimation filter design in VHDL using the DSP builder by Altera. does anyone have any information on this type of design,any books to recomend? papers? or existing designs I can modify. Thanks Shujah shujah10@yahoo.co.ukArticle: 46262
i think u have taken this as a homework. i just want to know is there any means to reduce the statements. CASE statement will not work since its not on the change in the values that i am concentrating but i am concentrating on how to write a design that will give me different widths to a array. the width of the array changes with some condition. for example a simple design is shown with if else statements. i just want to know is there any other way to assign different width to same array in the same design. if u can please help me.(do not do any homework for me) maimuna Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3D6499B9.42CF@designtools.co.nz>... > maimuna wrote: > > > > thanx for the reply. but the case statment will not work since this > > also will be lenthier. i want is there any option like table or > > anything else which will reduce the design statements. if there is no > > other option then i have to write code with if..else statement which > > will be too longer. > > plese help me out > > Is this homework ? ( sure looks like it ) > > Perhaps your tutor is looking for you to scan the logic, and > find the overlaping / redundant instances, and so simplify it that > way. > > Or, he may give more marks to someone who can extract the logic, > and completely re-write, to create a much smaller expression ? > > - jgArticle: 46263
Austin Franklin wrote: > > > If you want a legally binding statement, > > please contact Philips Intellectual Property & Standards. > > Thank you, Iwo, for taking the initiative to provide some information. Do > you have the contact information for Phillips Intellectual Property & > Standards? > > Regards, > > Austin Austin, I asked them and the answer was: The person listed as responsible for licensing out I2C is Gert Jan Hesselmann. Tel. NL +31 40 2743261 I don't want to inundate him with spam, so the email address is Gert dot Jan dot Hesselmann at philips dot com Note the spelling of Philips ;^) Kind regards, IwoArticle: 46264
> This works fine in Synplify, but for ModelSim I have to comment out the two > lines... > > --library virtex; > --use virtex.components.all; > > Does anyone know a better way to "hide" these from ModelSim? Create a package called virtexdummy that is just an empty shell: package components is -- empty end components; Within modelsim compile virtexdummy into a library called "dummy". Use the library mapping tools to map the name virtex to library "dummy". Now modelsim will have something to map the library name to and will not complain and you don't have to comment stuff in/out when going from synthesis to simulation. Back when I was using Synplicity, I had to do the same thing with the library "unisim" when synthesizing. JCArticle: 46265
While we're on this topic, has anyone else noticed that the order of ports in the component declarations in the Synplify virtex*.vhd files varies from file to file? And they don't match the unisim library either. Not that I'm suggesting that anyone use positional mapping of ports, but if you did, you'd be hosed if you used the Synplify libraries. Regards, Allan.Article: 46266
Daryl <e@eastday.com> wrote in message news:<ak4731$1fdoj1$1@ID-155928.news.dfncis.de>... > Hi all, > A question, what the fpga "speed level" as "...-5" means exactly? > "-5" device runs at more high speed than "-6" speed device or the > opponent? > How about the same speed level devices from different manufacturer? > > Thanks in advance? > > Daryl Hi, These speed grades are to differentiate the FPGA speeds. But the meaning will vary depends on the family of the device. In xilinx's Virtex-2 family, -4 is the slowest speed FPGA and -6 is the Fastest speed FPGA. Best regards, MuthuArticle: 46267
"suchitra" <ssbhide@rediffmail.com> schrieb im Newsbeitrag news:110cc2fe.0208222108.53d71cd3@posting.google.com... > hello friends > > i have stuck at a problem and need ur help.... > > i am trying to program xc9536xl using webpack. > i am not getting any warnings or error messages from webpack at time > of synthesis but when i download the design into the chip the design > doesnot gives the expected results i.e. its functionality, is Welcome to the real world. If the simulation runs fine, this does not mean the real hardware will do so. Are the signals (especially clocks) supplied to the chip correctl? Correct timing? And many more . . . -- MfG FalkArticle: 46268
Hi, I've searched all over in a bunch of xilinx documents. I'm looking for the state of i/o pins of an erased device. I'm using a coolrunner XPLA3 3064. Are they inputs, outputs, pulled up,tristated?? ThanksArticle: 46269
In addition to Klaus' suggestion, make sure that you're checking your post-fit timing. You may also try slowing down the input clock to the chip if it's possible on your board, it really depends upon your design and the problems you're having whether or not this will help. Typically, if the equations are correct from both the fitter report and simulation, and the pins are correctly assigned, then there's a timing problem somewhere. Klaus is also correct in that we could use some more detail on your problem. One other suggestion is to open a case with Xilinx Support at http://support.xilinx.com if the previous suggestions don't solve your problem. Hope this helps! Ryan Falser Klaus wrote: > In article <110cc2fe.0208222108.53d71cd3@posting.google.com>, > ssbhide@rediffmail.com says... > >>.... >>but when i download the design into the chip the design >>doesnot gives the expected results i.e. its functionality, is >>different where as everything works fine in simulation. >>.. > > > If you explain better what does not work maybe someone can > help you better. > In the mean time I would : > - check the fitter report to see if the implemented equations > are reasonable > - check if the signals are assigned to the correct pins. > > If this does not help I would simplify the design until it works > and then slowly add all the functionality. > > Good luck >Article: 46270
--------------BFC64CDFC1425278CA955DDE Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Andreas, Since the 405PPC is a core inside, surrounded by the FPGA fabric, one can design an SDRAM controller for arbritrary bandwidth (say 256 bits wide, clocking at 133 MHz). Then one would be much faster than the 405PPC which needs 32 bits and can clock at 300 + MHz. Basically, since all the 32 bit busses are pinned out internally to the Virtex II Pro, I believe that the processing power of the 405PPC is maybe four to eight times that of the discrete 405CR part which has only 256 pins in its package. The 405PPC primitive has 900+ pins. The OCM (on chip memory) management cores and features with the interconnect and CLB fabric make the Virtex II Pro with the 405PPC an especially powerful part. If the speed of the standard packaged processor can not be utilized due to the rest of the system bandwidth (a common situation today), the Virtex II Pro offers a way to break through that barrier. Now, perhaps for the first time in 5 years, the processor speed is the limiting factor again. We have basically divided the processor world into three use models: embedded (all inside, using BRAM, the internal 16K memory blocks for instructions and data, custom control c program), mixed medium (some off chip memory and specialized peripherals, no OS, larger programs), and mixed large (e.g. runing Linux, or some RTOS). Each use model has its own requirements. Each can be targeted to solve a specific problem. Using a Viretx II Pro as a Linux workstation is only one possibility. It is tempting, however, imagine a 4 CPU Linux workstation with no memory bandwidth issues ...... Austin Andreas Kugel wrote: > Hi there. > > The PPC405 core used e.g. in the PPC405CR device has a built-in SD-RAM > controller. If we would choose to use a Virtex-2Pro instead of the 405CR > how could we attach external SD-RAM (e.g. 64MByte) and what would be the > memory bandwidth to the SD-RAM compared to the one of the 405CR ? > > What about using Linux on the 405 core in the Virtex-2Pro ? > > Regards, > > Andreas --------------BFC64CDFC1425278CA955DDE Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit Andreas, Since the 405PPC is a core inside, surrounded by the FPGA fabric, one can design an SDRAM controller for arbritrary bandwidth (say 256 bits wide, clocking at 133 MHz). Then one would be much faster than the 405PPC which needs 32 bits and can clock at 300 + MHz. Basically, since <b>all the 32 bit busses are pinned out internally</b> to the Virtex II Pro, I believe that the processing power of the 405PPC is maybe four to eight times that of the discrete 405CR part which has only 256 pins in its package. The 405PPC primitive has 900+ pins. The OCM (on chip memory) management cores and features with the interconnect and CLB fabric make the Virtex II Pro with the 405PPC an especially powerful part. <b>If</b> the speed of the standard packaged processor can not be utilized due to the rest of the system bandwidth (a common situation today), the Virtex II Pro offers a way to break through that barrier. Now, perhaps for the first time in 5 years, the processor speed is the limiting factor again. We have basically divided the processor world into three use models: embedded (all inside, using BRAM, the internal 16K memory blocks for instructions and data, custom control c program), mixed medium (some off chip memory and specialized peripherals, no OS, larger programs), and mixed large (e.g. runing Linux, or some RTOS). Each use model has its own requirements. Each can be targeted to solve a specific problem. Using a Viretx II Pro as a Linux workstation is only one possibility. It is tempting, however, imagine a 4 CPU Linux workstation with no memory bandwidth issues ...... Austin <br> Andreas Kugel wrote: <blockquote TYPE=CITE>Hi there. The PPC405 core used e.g. in the PPC405CR device has a built-in SD-RAM <br>controller. If we would choose to use a Virtex-2Pro instead of the 405CR <br>how could we attach external SD-RAM (e.g. 64MByte) and what would be the <br>memory bandwidth to the SD-RAM compared to the one of the 405CR ? What about using Linux on the 405 core in the Virtex-2Pro ? Regards, Andreas</blockquote> </html> --------------BFC64CDFC1425278CA955DDE--Article: 46271
This is a multi-part message in MIME format. --------------3641ACF32E82EA5645E6ACD4 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Steve, The IOs of an erased/unconfigured XPLA3 device is 3-stated with a weak pullup. Stephan steve synakowski wrote: > Hi, I've searched all over in a bunch of xilinx documents. > I'm looking for the state of i/o pins of an erased device. > I'm using a coolrunner XPLA3 3064. > Are they inputs, outputs, pulled up,tristated?? > ThanksArticle: 46272
Hi, I think i got lost in the response to my original query. I have access to Xilinx FPGA Demo board which contains Xc4003E and XC3020. Now after looking at the description of the board, i don't know whether XC3020 is a FLASH or not . People in this thread have said that i could store the two bit streams to a FLASH and download the appropriate bitstream to the FPGA as and when required. Now my question is whether i need to plug in an external FLASH to Xilinx demo board ?. If i want to do that, i think it would be quite similar like connecting a host computer to the FPGA board and downloading bitstreams as and when required and this is what i have seen in a lot of research papers. Thanks, Ram. "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<ak3fo4$1f99rt$1@ID-84877.news.dfncis.de>... > "Ramakrishnan" <rxv20@po.cwru.edu> schrieb im Newsbeitrag > news:15cf85fc.0208220811.101ec55c@posting.google.com... > > Hi, > > Is there a way i could download two bit streams to a single Xilinx > > FPGA board when starting up ?. and also is it possible for a > > controller to switch between the two bit streams while in operation?. > > Sure. just store the two bitstreams in FLASH/RAM, and choose (and download) > the appropiate to the FPGA.Article: 46273
Thankyou very much! "Stephan Neuhold" <stephan.neuhold@xilinx.com> wrote in message news:3D665289.D8309818@xilinx.com... > Hi Steve, > > The IOs of an erased/unconfigured XPLA3 device is 3-stated with a weak > pullup. > > Stephan > > steve synakowski wrote: > > > Hi, I've searched all over in a bunch of xilinx documents. > > I'm looking for the state of i/o pins of an erased device. > > I'm using a coolrunner XPLA3 3064. > > Are they inputs, outputs, pulled up,tristated?? > > Thanks >Article: 46274
Sorry Ken, but these are all good reasons to not use the synplify virtex
library at all. We ran into too many frustrations with it early on and
decided to use only the unisims like I described earlier.
Allan Herriman wrote:
> While we're on this topic, has anyone else noticed that the order of
> ports in the component declarations in the Synplify virtex*.vhd files
> varies from file to file?
>
> And they don't match the unisim library either.
>
> Not that I'm suggesting that anyone use positional mapping of ports,
> but if you did, you'd be hosed if you used the Synplify libraries.
>
> Regards,
> Allan.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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