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Hi,
I am using a Spartan-II 100K to do some experiments on clock multiplication.
I successfully made a X2 and X4, then problem occurs when I coded one extra
DLL to make it 8. Following is the bug,
Whats your comments?
ERROR:Place:1726 - Could not find an automatic placement for the following
components:
CLKIN of type GCLK IOB is placed at P77.
dll2x of type DLL is unplaced.
clk2xg of type GCLK BUFFER is unplaced.
dll4x of type DLL is unplaced.
clk4xg of type GCLK BUFFER is unplaced.
dll8x of type DLL is unplaced.
clk8xg of type GCLK BUFFER is unplaced.
lckpad of type GCLK BUFFER is unplaced.
ERROR:Place:1727 - Xilinx requires using locate constraints to preplace such
connected GCLK/GCLKIO/DLL components.
Total REAL time to Placer completion: 2 secs
Total CPU time to Placer completion: 1 secs
-----------------------------------------------------------------
Following are the codes:
module dll_standard (CLKIN, CLK2X, CLK4X, CLK8X, LOCKED);
input CLKIN;
output CLK2X, CLK4X, CLK8X, LOCKED;
wire RESET;
wire CLKIN_w, RESET_w, CLK2X_dll, CLK4X_dll, LOCKED2X, LOCKED4X;
wire LOCKED2X_delay, RESET4X;
wire LOCKED4X_delay, RESET8X;
wire logic1;
assign RESET = 1'b0;
assign logic1 = 1'b1;
assign CLKIN_w = CLKIN;
assign RESET = RESET_w;
CLKDLL dll2x (.CLKIN(CLKIN_w), .CLKFB(CLK2X), .RST(RESET_w),
.CLK0(), .CLK90(), .CLK180(), .CLK270(),
.CLK2X(CLK2X_dll), .CLKDV(), .LOCKED(LOCKED2X));
BUFG clk2xg (.I(CLK2X_dll), .O(CLK2X));
SRL16 rstsrl (.D(LOCKED2X), .CLK(CLK2X), .Q(LOCKED2X_delay),
.A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1));
assign RESET4X = !LOCKED2X_delay;
CLKDLL dll4x (.CLKIN(CLK2X), .CLKFB(CLK4X), .RST(RESET4X),
.CLK0(), .CLK90(), .CLK180(), .CLK270(),
.CLK2X(CLK4X_dll), .CLKDV(), .LOCKED(LOCKED4X));
BUFG clk4xg (.I(CLK4X_dll), .O(CLK4X));
SRL16 rstsr2 (.D(LOCKED4X), .CLK(CLK4X), .Q(LOCKED4X_delay),
.A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1));
assign RESET8X = !LOCKED4X_delay;
// assign CLK4X_B = ~ CLK4X;
CLKDLL dll8x (.CLKIN(CLK4X), .CLKFB(CLK8X), .RST(RESET8X),
.CLK0(), .CLK90(), .CLK180(), .CLK270(),
.CLK2X(CLK8X_dll), .CLKDV(), .LOCKED(LOCKED_dll));
BUFG clk8xg (.I(CLK8X_dll), .O(CLK8X));
BUFG lckpad (.I(LOCKED_dll), .O(LOCKED));
endmodule
Article: 44476anyone have ballpark info on how long it takes to design, develop, debug a 2 million gate design. complexity and throughput both high.Article: 44477
Forgot to mention, my CLKIN = 16.0 MHz. CLK8X will yield 128 MHz. "XU QIJUN" <qijun677@oki.com> wrote in message news:3d12919d$1@news.starhub.net.sg... > Hi, > > I am using a Spartan-II 100K to do some experiments on clock multiplication. > I successfully made a X2 and X4, then problem occurs when I coded one extra > DLL to make it 8. Following is the bug, > Whats your comments? > > ERROR:Place:1726 - Could not find an automatic placement for the following > components: > CLKIN of type GCLK IOB is placed at P77. > dll2x of type DLL is unplaced. > clk2xg of type GCLK BUFFER is unplaced. > dll4x of type DLL is unplaced. > clk4xg of type GCLK BUFFER is unplaced. > dll8x of type DLL is unplaced. > clk8xg of type GCLK BUFFER is unplaced. > lckpad of type GCLK BUFFER is unplaced. > ERROR:Place:1727 - Xilinx requires using locate constraints to preplace such > connected GCLK/GCLKIO/DLL components. > Total REAL time to Placer completion: 2 secs > Total CPU time to Placer completion: 1 secs > > ----------------------------------------------------------------- > > Following are the codes: > > module dll_standard (CLKIN, CLK2X, CLK4X, CLK8X, LOCKED); > input CLKIN; > output CLK2X, CLK4X, CLK8X, LOCKED; > > wire RESET; > wire CLKIN_w, RESET_w, CLK2X_dll, CLK4X_dll, LOCKED2X, LOCKED4X; > wire LOCKED2X_delay, RESET4X; > wire LOCKED4X_delay, RESET8X; > wire logic1; > assign RESET = 1'b0; > > assign logic1 = 1'b1; > > assign CLKIN_w = CLKIN; > assign RESET = RESET_w; > > CLKDLL dll2x (.CLKIN(CLKIN_w), .CLKFB(CLK2X), .RST(RESET_w), > .CLK0(), .CLK90(), .CLK180(), .CLK270(), > .CLK2X(CLK2X_dll), .CLKDV(), .LOCKED(LOCKED2X)); > BUFG clk2xg (.I(CLK2X_dll), .O(CLK2X)); > SRL16 rstsrl (.D(LOCKED2X), .CLK(CLK2X), .Q(LOCKED2X_delay), > .A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1)); > assign RESET4X = !LOCKED2X_delay; > > CLKDLL dll4x (.CLKIN(CLK2X), .CLKFB(CLK4X), .RST(RESET4X), > .CLK0(), .CLK90(), .CLK180(), .CLK270(), > .CLK2X(CLK4X_dll), .CLKDV(), .LOCKED(LOCKED4X)); > BUFG clk4xg (.I(CLK4X_dll), .O(CLK4X)); > SRL16 rstsr2 (.D(LOCKED4X), .CLK(CLK4X), .Q(LOCKED4X_delay), > .A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1)); > assign RESET8X = !LOCKED4X_delay; > // assign CLK4X_B = ~ CLK4X; > > CLKDLL dll8x (.CLKIN(CLK4X), .CLKFB(CLK8X), .RST(RESET8X), > .CLK0(), .CLK90(), .CLK180(), .CLK270(), > .CLK2X(CLK8X_dll), .CLKDV(), .LOCKED(LOCKED_dll)); > BUFG clk8xg (.I(CLK8X_dll), .O(CLK8X)); > > BUFG lckpad (.I(LOCKED_dll), .O(LOCKED)); > > endmodule > > >Article: 44478
On Mon, 10 Jun 2002 12:57:14 +0200, "Noddy" <g9731642@campus.ru.ac.za> wrote: >Hi, > >I know that one should place 0.1uF and 0.01uF caps on all power supply pins >on the FPGA... does this include both Vcco and Vccint, or can one get away >with just Vccint and then put only 0.1uF on Vcco. I am seriously running out >of room on my PCB, and increasing the PCB size is not an option! > >adrian > > I've done some pretty serious TDR testing of multilayer boards with different bypass caps installed. Most of my boards have a solid ground plane and a solid Vcc plane separated by a thin (0.005 inch or so) dielectric. Sometimes the power plane is chopped up: say, +5 mostly but a few islands of 3.3 or whatever for FPGAs. I generally use four bypass caps *per FPGA*. At high frequencies, the planes themselves are the cap, and the ceramic caps just help out at lower frequencies and are the gross charge storage reservoir. Actual cap placement doesn't seem to matter as long as the planes are solid, the dielectric is thin, and the caps are somewhere - basicly anywhere - on the planes. 0.1 uf 0805 or 0603 is probably as good as any. I've done lots of boards with way too many bypass caps, but so far I've never done a multilayer board that had too few. JohnArticle: 44479
Ya, but the more people enter the job pool in your specific field, the cheaper the salaries for everyone in that field will be. Just simple supply and demand. Lets just call H1-B what it is: a labor subsidy for high tech, approved by corrupt politicians. Good for employers, bad for employees (unless of course you're the one getting the visa). And don't buy that stupid ad in the paper BS. The company placing the ad already knows who they want to hire, and are just playing the game so they don't get in trouble with a govt agency that doesn't give a squat. I don't blame the applicants, heck, I'd be first line if I lived in the second world and someone offered me a way out. I'm all for open borders and free trade, but its got to be for everyone, not just MY specific field. Otherwise my salary is bid down (or equivalently held steady when it should be rising) while I have to purchase goods and services in the higher priced controlled market. (e.g. If I have to compete with a guy from India at my job, when I go home I should be able to hire a house keeper from Mexico for $5/hr.) "jakab tanko" <jtanko@ics-ltd.com> wrote in message news:<aet1vn$msc$1@news.storm.ca>... > Relax, Hater, if you are as qualified as this guy is > you will get the job..... > > jakab > > Spam Hater <spam_hater_7@email.com> wrote in message > news:3d101eab.4925791@64.164.98.7... > > > > Notice to potential employers: > > > > You will be displacing a US citizen who is qualified, and willing to > > work for that salary. > > > > Make sure that you put a statement to that effect on the H1-B transfer > > application. > > > > Nothing personal Farhad. I have a family to feed. > > > > > > > > On 17 Jun 2002 21:18:46 -0700, farhad@everdream.com (Farhad Abdolian) > > wrote: > > > > >Hi, > > >I am currntly on H1-B visa, and since my current employer has decided > > >to close our office, I am looking for a new job, and a company to take > > >over my H1-B visa while my green card application goes through (my > > >wife is American). > > > > >Article: 44480
It may be overpriced but can you design, build, debug ONE card for that price? As engineers I think we get caught up sometimes in part cost or tend to be optimists on our ability to finish a task quickly. You kind of have to be to tackle some of the problems we get handed. kolja@bnl.gov (Kolja Sulimma) wrote in message news:<25c81abf.0206161242.261776e4@posting.google.com>... > This card will likely do the job for you. > But for your simple application it is extremely overpriced. > > If I understand your application correctly, 24 counters of 24 Bits > should fit into a Spartan-II 200 Device together with a PCI core and a > FIFO. > > Kolja Sulimma > > > > "Pat Ford" <pat.ford@nrc.ca> wrote in message news:<aeco9f$oi8$1@moonstone.imsb.nrc.ca>... > > They do BUT each card will only do 8 channels and the cost is high, and > > they don't support the range of OS's that we are looking at. > > We are looking at the Nallatech > > Strathnuey kit with the XCV1000 fpga, any have opinions on this card? > > http://www.nallatech.com/products/dime_select/strathnuey/index.asp > > thanks for your help so far > > Pat > > > > "Jay" <kayrock66@yahoo.com> wrote in message > > news:d049f91b.0206131216.10a6fa2d@posting.google.com... > > > I don't want to spoil your fun but this sounds like something that > > > might already be available. Look at those PC intrumentation guys like > > > National Instruments and the like, they may have something you can use > > > or that can be gated.Article: 44481
Yes tt is this output that I wan't but from the ISE4.2 tool kit. Using the simprims libraries I do not have any timing info turned on so I should get the same functional simulation as per the VHDL code. "Ray Andraka" <ray@andraka.com> wrote in message news:3D12109A.4460F72B@andraka.com... > YOu can get a mapped synthesis output from the synthesizer which is > constructed of unisim library elements. In Synplify you turn on mapped > output and it produces a .vhm (mapped VHDL or .vm mapped verilog output) > which is a unisim primitive only realization of your design. This can be > useful to check the results of synthesis before going into the XIlinx > tools, and it runs a bunch faster than the simprim xilinx output files. > > newman wrote: > > > Anthony, > > Good questions. I have not thought too deeply about Unisim, but my > > general belief is that they are there to allow instantiation of > > functionality into your VHDL/ Verilog/ Schematic design, and provide > > functional simulation capabilities. After synthesis, one uses the > > Simprim libraries, and I have never questioned that approach. I > > suspect that this library is required in order to back-annotate timing > > delays from the Standard Delay Format (SDF) file for timing simulation > > purposes. > > > > Getting the X's out of a synthesized design may frusterate the new > > user, and sometimes the veteran user as well. One needs to be > > cognisant of the timing constraints placed on the design by the UCF > > file. When one does functional simulations, one is almost dealing > > with an ideally fast part. After place and route, there are real > > world timing delays, and the design may not work at 200 Mhz any more. > > Other issues to consider are: > > Are your memory storage elements getting initialized at the start > > of your simulation? > > Is the setup and hold time of your testbench compliant with the UCF > > file? > > Is your simulator default resolution set correctly? > > Are the Xilinx tools optimizing away portions of your design > > because of coding errors? > > > > One thing you could try would be to put in a divide by two test > > circuit, and see if you can make that simulate after synthesis, and > > gradually debug the circuits that are giving you problems. > > > > Hope this helps, > > > > Newman > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 44482
HI Thanks for the pointer. I have downloaded the file but I am having difficulty opening each Nios core, ie SOPC won't load up. Any suggestions? Thanks Ryan "Vincent JADOT" <vjadot@digitalsurf.fr> wrote in message news:3d119950$0$24013$4d4eb98e@read.news.fr.uu.net... > Hi > > there is an example to download of 2 nios on a chip (excalibur kit) at this > address: > http://cnfm.cnfm.fr/ALTERA/ExcaliburN/Arbitrage.zip > > it 's on a french site, http://cnfm.cnfm.fr/ALTERA/Excalibur.htm, it's for > examples and update for the ALTERA french university program. So it's in > french, but i think it's understandable for english people. > > Excuse my english, i'm a french student. > > > > > > "Ryan" <ryans@cat.co.za> a écrit dans le message news: > 3d12031a.0@obiwan.eastcoast.co.za... > > Hi > > > > I am working with an Altera Excalibur Nios development board version 1.1. > Is > > it possible to configure the PLD (20K200) with more than 1 Nios cpu? What > I > > would like to do is configure 1 cpu to be a master and the others as > slaves. > > The master will then control the processess executed on the slaves etc. > > Ideally the slaves will not have to make use of external SRAM of FLASH. Is > > this concept possible and how can it be implemented? If not, have you any > > suggestions on what other route to consider? > > > > Thanks > > Ryan > > > > > >Article: 44483
Hi, where can i get the xilinx's 4.1i's Latest webpack? and how to updatae the webpack? Thanks and regards, MuthuArticle: 44484
Hi, In synplify_pro, to disable retiming option of a particular register i did the below: ######################################################## reg [1:0] data/* syn_allow_retiming=0 */; ######################################################### But still synplify_pro is retiming this register data. How can i avoid this? Thanks and regards, MuthuArticle: 44485
Hi Antonio,
By default, DK1 will build a RAM out of distributed RAM, which it
appears to be doing here. If you want to use block RAM, then you need
to say so explicitly:
ram unsigned char RAM[160*120] with {block = 1};
That should solve your problem.
Ashley
Antonio Martínez Álvarez <amartinez@atc.ugr.es> wrote in message news:<3D0DC7A6.1010108@atc.ugr.es>...
> Hello.
> I can't work with a ram defined as:
> ram unsigned char RAM[160*120];
>
> dk1.1 gives an enormous EDIF an uses 10e6 logical gates. ???
> Xilinx Foundation crushes when attempting to do the mapping.
> We have VirtexE 2000ebg560-6 FPGA on a RC1000, and we use
> DK1.1.
>
> I really need to use the internal FPGA RAM. I know how to use
> the external RC1000 SRAM (4 modules)... but don't know what's
> wrong with my code.
>
> Could you please contact me or give me an example for doing that.
> I work on image processing. I can send my little code.
>
> What I attempt to do:
> 1.- I have a frame in the host program. a 160*120 matrix if unsigned
> bytes.
> 2.- I send this matrix to SRAM
> 3.- I want to read the SRAM and write the matrix to the FPGA's RAM
> 4.- Manipulate the frame... for example adding 1 to every pixel...
> whatever (then we need to write a filter)
> 5.- Pass the new rewritten frame to the SRAM
> 6.- Then the host program loades the frame.
>
> I've do that with SRAM. But FPGA's RAM doesn't work. Any suggestion
>
> Thank you.
Article: 44486Hi, I can open each NIOS core with SOPC Builder on my system (win 2k and quartus1.1). I have install nios111 update (13 Mo) and quartus1.1 sp1full (91Mo) . Probably, it's a nios 1.11 conflict (i'm not sure). You can download the nios1.11 update on ALTERA site: https://www.altera.com/support/software/download/sof-download_center.htmlArticle: 44487
Hello. Does anyone know about an StrongARM - 110 VHDL behavioral model? If possible a free model and available from the web. We have one from 1996 and it doesn't seem to be doing what I was expecting according to the SA-110 datasheet. I checked on Intel (http://appzone.intel.com/toolcatalog/arch.asp?architecture=10) but couldn't find what I was looking for. Thank you very much. -- Ulises HernandezArticle: 44488
Hello, One of the major difference is going to be the programming speed. The parallel mode would be faster... regards, Cyrille "emanuel stiebler" <emu@ecubics.com> wrote in message news:3D127698.39F5AE01@ecubics.com... > Hi, > I was planning to download the bitstream from a uController > via JTAG. (XAPP058). Because the uController has the databus (d0..d7) > already connected to the d0..d7 pins of the FPGA (Spartan2e), would the > slave parallel mode be the better solution ? > > Any problems I should expect from this ? > > cheers & thanksArticle: 44489
Muthu wrote: > Hi, > In synplify_pro, to disable retiming option of a particular register i > did the below: > > > ######################################################## > > reg [1:0] data/* syn_allow_retiming=0 */; Should have been: reg [1:0] data/* synthesis syn_allow_retiming=0 */; You could also apply this in the constraint file. > > ######################################################### > > But still synplify_pro is retiming this register data. > > How can i avoid this? > > Thanks and regards, > Muthu >Article: 44490
Hello, I have an Autosite programmer acquired on Ebay. Because of their business model, Data I/O is fairly tight with technical information. I am sure that there are a lot of autosites out there (it is the programmer component of the the ProMaster production models). Has anyone ever successfully self-upgraded one of these for (1) more memory, or (2) a hard disk (MSM=mass storage module)? I would imagine that these are standard parts. I'd be very interested in information anyone may have. Thanks for any reply, David.Article: 44491
Hi, you should switch to NIOS V2.0 or V2.1, the board is the same, you just need the new SW. The newer versions have full SOPC builder support for integrating multiple NIOS processors into a single system. Check out application note 184 which is available on the Altera website. It discusses the implementation of multiple masters into a NIOS system. These multiple masters can also be multiple NIOS processors. For each processor you get your own directory structure for SW development. With some mouse clicks you can add multiple processors and specify what slaves they should share. Slave side arbitration gets automatically built in for those slaves that can be accessed by multiple masters and the arbitration scheme is configurable. Furhtermore each master gets it's own Avalon bus segment and so mutliple masters can simultaneously talk to different slaves. Arbitration only takes place if multiple masters try to access the same slave in the same cycle. When using V2.0 or newer and once you understood the concept it's really just a question of minutes to put together a complex system with multiple processors. For your application you could have one master CPU that runs from external memory. The slave CPUs could run from on-chip RAM or ROM. You could implement a common on-chip memory that can be accessed from all CPUs in the system and that's being used to exchange data between the CPUs. Alternatively you could also make the data memories from the slave CPUs accessible to the master. The possible combinations are infinite and what you described is certainly possible. V2.0 and newer supports a multi master avalon bus structure and so it's a lot easier to implement than with 1.1 or 1.1.1. Regards Wolfgang http://www.elca.de "Ryan" <ryans@cat.co.za> schrieb im Newsbeitrag news:3d12031a.0@obiwan.eastcoast.co.za... > Hi > > I am working with an Altera Excalibur Nios development board version 1.1. Is > it possible to configure the PLD (20K200) with more than 1 Nios cpu? What I > would like to do is configure 1 cpu to be a master and the others as slaves. > The master will then control the processess executed on the slaves etc. > Ideally the slaves will not have to make use of external SRAM of FLASH. Is > this concept possible and how can it be implemented? If not, have you any > suggestions on what other route to consider? > > Thanks > Ryan > >Article: 44492
Using slave parallel, you have to make sure your uc has the control on the other specific slave parallel mode signals like program signal, cclk signal ... (done to check the download). Without these signals you will be not able to build a slave parallel configuration access. Laurent www.amontec.com emanuel stiebler wrote: > Hi, > I was planning to download the bitstream from a uController > via JTAG. (XAPP058). Because the uController has the databus (d0..d7) > already connected to the d0..d7 pins of the FPGA (Spartan2e), would the > slave parallel mode be the better solution ? > > Any problems I should expect from this ? > > cheers & thanks >Article: 44493
Hi, I would like to have some feed-bak regarding of the accuracy of the XPower tool from Xilinx. I have been working on a high-level power estimator for a few month, and I wish I could get some figure to compare with Xpower with my model (I remember someone who said that the accuracy was about 5-10% but I can't find any reference). Thanks, StevenArticle: 44494
Hi, Does anyone know if there are premade packages for Orcad capture chipscale CPLD's XCR3064XL-CP56 and XCR3128XL-CS144. I couldn't find any, but could just make them. Pads footprints would be nice too, but again could make them, just saves time. Thanks, SteveArticle: 44495
newman wrote: > Oops, I meant to say: After MAP. > > > functional simulation capabilities. After synthesis, one uses the > > Newman In fact you can, with 3.3i and later, use NGD2VER or NGD2VHDL to get a simprims based simulation netlist from the .ngd file produced by NGDBUILD. No SDF of course. You can also get simprims based netlists for any of the submodules linked together by NGDBUILD by going NGDBUILD: .edn -> .ngo -> .ngd NGD2<VER | VHDL>: .ngd -> <.v |.vhd> but I've never tried using them. This might also work with XST's brain-dead-binary output as well as the - 10% - sane EDIF.Article: 44496
Russell wrote: > Muthu wrote: > > > > Hi, > > > > where can i get the xilinx's 4.1i's Latest webpack? and how to updatae the webpack? > > Isn't it 4.2i on the xilinx site? Its a bit point & click tedious to get all the different packages so you might want to consider using ``wget'' [available on Linux some modern Unix systems, its an FSF tool] to do the HTTP downloads via a script (many thanks to the original poster on this NG who suggested it) wget --http-user <your user ID> --http-passwd <your passwd> http://direct.xilinx.com/direct/webpack/FILE where: FILE = WebPACK_42wp20_installer.exe or FILE = WebPACK_42wp20_<a | b | c | ...>.xwpArticle: 44497
I guess this is really a design flow question. I am using ISE and implementing a PCI interface in a VirtexE. I have now gotten to the stage where I need to add some timing constraints. The question is, should those timing constraints be added to the .UCF file under "Design Entry Utilities>User Constraints>Edit Implementation Constraints File" or some other file. I have tried using Constraints Editor, somewhat unsuccessfully to add constraints so maybe part of the issue is I dont really know how to add them properly. I can add IOSTANDARD's and LOC's with no problem to the UCF, but now timing has become an issue. As always, any suggestions will be greatly appreciated. CharlesArticle: 44498
Jim napisal(a): >But I can't find the driver. > >I try to use the setup application under the directory "drivers" in the path >where I installed MaxPlus+II >but it looked useless. > >any other ideas? or Maxplus just doesn't support WinXP? Try searching Altera website. I had the same problem with ByteBlaster and I found good info on their www. -- Pozdrowienia, Marcin E. Hamerla "Watch carefully, I will do it only once."Article: 44499
Hi,
I am trying to find a way to prevent the Max+Plus II 9.4 compiler from
performing any logic minimization on a VHDL design similar to the one
below:
A B C
input ----|>*-------|>*--------|>*----- output
Using Synplify 7.1, I can synthesize the design and keep all the
appropriate nets. However, even after specifying a WYSIWYG global
logic synthesis compilation option in Max+PlusII; taps A, B, and C are
no longer connected together and appear as separate input and output
paths. The logic for B and C are also minimized as B is driven purely
by the input (and the internal and-or-xor structure) without the
presence of the two inverters before it and C is driven by a single
inverter instead of three. Therefore, A, B, and C in a time
simulation all change value at the same time without any delay between
them (since they are no longer connected). Are there any other options
that I can try for preventing logic minimization? I am compiling for
an Altera Max7000AE chip. Thanks.
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