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"David Horner" <dhorner@med-web.com> wrote in message news:b67cf57a.0209251129.129fc6f1@posting.google.com... > I am very interested in programming and running the fpgas from a microcontroller. > > Does anyone know where I can find a good book or tutorial on the net? > > Know any good evaluation/proto boards? I've done this with an Altera FPGA, configuring it from an ADI DSP and then communicating with the FPGA using one of the DSP SPORTs. All the information I needed was in the Altera application notes. It wasn't straightforward, mainly because of problems with the ADI development tools. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 47451
Simon wrote: > > Just in case anyone else is stuck with this: > > If you want to run webpack binaries under Linux/Wine, and don't have the > windows DLL's to make Wine's life easier, none of the binaries from the > CVS version of Wine will work out-of-the-box on a stock Redhat 7.3 machine. > > If, however, you go to www.dll-files.com and locate "msvcirt.zip" (I > found it searching google for "msvcirt"), and install the msvcirt.dll > file into the '~/c/windows/system32' directory (or wherever you placed > Windows' home directory), the commandline tools (at least) seem to work > ok :-) > > I tried the gui environment (I assume "webpack.exe" is the gui tool) but > it chokes when it can't find mfc42.dll, and the one at www.dll-files.com > doesn't really help. Shame. Still, at least par, map, etc. work ok :-)) > > Now I can try putting together a Linux development environment :-) A trouble-free linux install of webpack is the only thing stopping me from ditching windoze and an extra PC on my desk;)Article: 47452
hi, I need to read/write to hard disk using FPGA, consenquently developing IDE core. But I have not been able to find any VHDL/verilog simulation models for hard disk or even just the ATA interface. I need the models to test the interface only. Even only the PIO mode will do. Are there any such models? Thanks brijeshArticle: 47453
No, the design is only half empty (optimist!). What I have learned today is that the place and route tool is passing constraints onto the Xilinx flow, and this has been probably constraining the design where it should not be so stringent. I had some help today from a resource that is getting me on my way to properly constraining the design. It does appear that the varying number of logic levels is coming from the Xilinx P/R and not the synthesis tool. Clyde Marc Randolph wrote: > "Clyde R. Shappee" <clydes@world.std.com> wrote in message news:<3D910893.3ACBCF64@world.std.com>... > > Hello, all, > > > > I am working a design with the Xilinx Spartan IIe, using ISE 4.2 sp3, > > Sinplicity 7.1 for synthesis. > > > > My design is relatively minimally constrained and meets static timing. > > In my report I see 8 levels of logic associated with my system clock. > > > > Today, I removed some unused logic, and reduced the length of some shift > > registers in my design, dropping about 32 flip-flops. > > > > Now the design fails to make static timing and the number of levels of > > logic associated with my clock has gone up to 12! > > > > What is at work here? > > > > Is the synthesis tool shooting me in the foot, or is it in the Xilinx > > tool, or my constraints. > > Howdy Cylde, > > Is this device pretty full? We've only run into this type of problem > when things are pretty packed. > > When this occurs, our typical mode of operation has been to do a > multi-pass place and route if it is close to meeting timing (say a > timing score of under 10000). One of the passes will usually hit on > an overnight session. > > If the timing is further out than that, we just continue improving the > code where we can (often times in areas completely unrelated), and the > next time around, it often meets timing, or gets very close (and will > meet with a multi-pass session). > > Good luck, > > MarcArticle: 47454
Running the Xilinx ISE 4.2i tools, I get a warning ERROR:NgdBuild:455 - logical net 'N812' has multiple drivers Now the meaning is obvious enough, but the problem is, how to locate this net (it is a synthesiser-generated name) in the hierarchy. The tools don't give any indication where it is located. It is a large project, with over 40 VHDL design elements in a deep hierarchy. A search of the output files shows none of them contain this string, except the NGD log, which only contains the error as above. This error causes no post-synthesis VHDL file to be generated, else one could search that file for the net. Any ideas?Article: 47455
John_H <johnhandwork@mail.com> wrote in message news:<3D91F52F.A89F0BBA@mail.com>... > Jay wrote: > > > The package is a really a small part of the cost of these chips. The > > die are very large (and hence the circumfrence and associated I/O > > ring), so I/O is cheap and easy to add, so they do. A smaller package > > pin count, while technically producable, may only reduce the cost a > > few percent. In contrast, on a small high yield die, package cost can > > be a big part of the cost, but we're in the opposite end of the > > spectrum with FPGAs. > > > > So if the cost is nearly the same for a high or low I/O package, the > > only advantage is ease of assembly for a larger pitch part. Products > > that use FPGAs tend to be low volume, high value, so theres not much > > pressure to have a lower tech soldering process either. > > > > So these are some of the reasons people end up doing like use and > > using 40% of the pins in an 1152 pin package. > > > > Keep in mind that the lower-cost devices such as the Spartan-IIE (and the > Cyclone?), the package *is* a significant portion of the overall cost, not > single digit percent. In the enormous xc2v6000, it's hard to imagine how > any package would impact the price. > > I've been buying the bigger devices for pin count with low logic utilization > in my current designs compared to the telecom centric stuff I was doing a > few years back where I/O wasn't a big concern. > > It takes all kinds... > Indeed it does. This discussion has been quite interesting to me - we've heard from people from all corners of the spectrum. For the record, although the cost incurred in going with the larger package is a factor, by far the bigger factor in going with a larger package is the area it takes up. The FG676 package is the best compromise in area and pin density of any of the packages, in my opinion. We simply don't have room for the larger packages, but we would sure be willing to pay for more LUT's in the FG676 package... Have fun, MarcArticle: 47456
SH7, Thank you. Reala "Spam Hater" <spam_hater_7@email.com> wrote in message news:3d912b04.3353020@64.164.98.7... > Hi Reala, > > comp.lsi.cad has the most traffic regarding IC layout But most of it > seems to be centered aroung the program 'magic'. > > Still at it, eh? ;) > > SH7 > > On Fri, 20 Sep 2002 09:41:08 +0800, "Reala" <-> wrote: > > >Hi, > > > >Sorry that I ask the question about IC layout, but I cannot find any > >newsgroup about IC layout. > >Sorry for any inconvinence. > > > >Anyone can tell me some homepage or newsgroup talk about IC layout? > >Thank you. > > > >Reala > > > > > > >Article: 47457
Dan wrote: > Petter Gustad <newsmailcomp1@gustad.com> wrote in message news:<m3k7mbz4ks.fsf@scimul.dolphinics.no>... > >>Is ISE 5.1 a native Linux port or does it run under Wine like 4.2? >> >>Petter > > > How well does ISE work under linux ? I am considering using it in the > WINE environment, but I'm hesitant that it might be unstable or slower > due to the extra software layer due to WINE. Does anyone have > experience with this ? The command line tools are completely stable and just as fast as under Windows. And there are several of us involved in the Wine community who test the latest Wine with the Xilinx tools on a very frequent basis, to make sure no bugs are allowed to creep in ;) The command line method is also the method officially "supported" by Xilinx. The GUI tools are a little more "experimental", and unsupported by Xilinx. The main ISE project manager pretty much works, at least using the HDL flows (I have not tried the schematic editor). The only exception I am aware of is that when source code files are added to the project, they do not get written to the project file, project.npl. This file is plain text, so the files can be added by hand with a text editor, and everything works. This sure would be a lot easier to fix if someone with the ISE source code took a look at it (uh, Xilinx?). The fpga_editor also works quite well and is very fast.. well at least if you apply this patch to a recent version of wine: http://www.leewardfpga.com/fpga.diff The iMPACT tool does not work. -- My real email is akamail.com@dclark (or something like that).Article: 47458
The Altera App Note is: http://www.altera.com/literature/an/an122.pdf Additional references can be found in: http://www.altera.com/support/devices/programming/jam/embedded/dev-jam_ep.ht ml http://www.altera.com/support/devices/programming/jam/dev-isp_jam.html http://www.altera.com/support/devices/programming/overview/sup-pgm_hdw.html - DS "David Horner" <dhorner@med-web.com> wrote in message news:b67cf57a.0209251129.129fc6f1@posting.google.com... > I am very interested in programming and running the fpgas from a microcontroller. > > Does anyone know where I can find a good book or tutorial on the net? > > Know any good evaluation/proto boards? > > Thanks > --DaveArticle: 47459
Peter Wallace wrote: > Its pretty trivial, but you will probably need a RC filter > followed by a Schmitt trigger to clean up the strobe (=config > clock) at the FPGA end > of the cable. You dont need to connect to the FPGA's BUSY since > you have no chance to send data faster than the 50 or so MHz that > requires looking at the FPGA's BUSY. You will probably want to > connect one of the parallel ports output handshaking lines to > PROGRAM, and two of the input handshaking lines to DONE and INIT > so you can determine if the FPGA configured properly from the host > side... > > > Peter Wallace Thank you, Peter, My link works fine now: I connected data and strobe lines via serial resistors. BUSY is linked to an FPGA ready signal, thus delaying pending bytes until the FPGA is configured with the correct design. Thanks for your hints. Bernhard -- before sending to the above email-address: replace deadspam.com by foerstergroup.deArticle: 47460
Hi! > I am very interested in programming and running the fpgas from a > microcontroller. > > Does anyone know where I can find a good book or tutorial on the net? > > Know any good evaluation/proto boards? You can visit http://www.johann-glaser.at/projects/X2S_USB/ This is a download program for the X2S_USB eval board from CESYS http://www.cesys.com/ebene2/x2s_usb.htm The program is GPLed, so sources are included and it is free software. Look at it for a simple example. The board uses a Cypress AN2131Q EZ-USB microcontroller, which has an 8051 core. The 8051 firmware as well as the FPGA configuration is downloaded via the USB bus. The software runs on Linux (and probably *BSD and MacOS X). Bye HansiArticle: 47461
I am finding a object file of fpga which can map cells of library to the hardware cells of fpga.thanksArticle: 47462
Hi I am finding a object file of fpga which can map cells of library to the hardware cells of fpgaArticle: 47463
Hi I am finding a object file of fpga which can map cells of library to the hardware cells of fpga. who can tell me where to find it? thanks.Article: 47464
Dear group members, I am using Dual Port BlockRAM (of CoreGen IP)in my design (Xilinx Virtex device). Now my system requirement is such that the DPRAM should reside outside the FPGA. I am searching for a Dual Port SRAM IC which is similar to the Dual Port Block RAM (of CoreGen IP). Except for the functionality (enable,reset etc.), other things like memory size, physical size,cost,timing doesn't matter for me. Could somebody please help in knowing the availability of an IC atleast close to my requirement? Regards, Nagaraj CSArticle: 47465
Thanks to all of you for the tips and suggestions... Peter, the multiplier is (Sign+15) bits in x (Sign+15) bits in = (Sign+29) bits out. -rajeev-Article: 47466
I attach only 5V power ang ground to the chip(that's all). I think the problem raised after my attempt to configure the device manually. The download cable was not functioning and I wanted to stimulate the device manually resetting the boundry scan controller (TRST sequence) and capturing (all 1s) instruction as described in Xilinx Troubleshooting guide (http://toolbox.xilinx.com/docsan/3_1i/data/common/jtg/dppc/appc.htm#BHAICAB I). And now the chip is consuming so much power that LED on the power supply stops ligting.Article: 47467
You could always use a second FPGA to do that. If you need just 1 memory,
then an XC2S15 should do the trick. I suspect a second small FPGA with
just enough size to fit the number of BRAMs you need is going to be less
costly than a special purpose dual port (read low volume and therefore
expensive) memory. Question is, why can't that be integrated into the
FPGA? If the issue is that you need a large bank of dual port memory,
then you would be better off using a traditional single ported memory plus
some logic in the FPGA to make it appear as a dual port memory.
Nagaraj wrote:
> Dear group members,
> I am using Dual Port BlockRAM (of CoreGen IP)in my design (Xilinx
> Virtex device). Now my system requirement is such that the DPRAM
> should reside outside the FPGA.
> I am searching for a Dual Port SRAM IC which is similar to the Dual
> Port Block RAM (of CoreGen IP). Except for the functionality
> (enable,reset etc.), other things like memory size, physical
> size,cost,timing doesn't matter for me.
> Could somebody please help in knowing the availability of an IC
> atleast close to my requirement?
>
> Regards,
> Nagaraj CS
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47468
When you consider all of the costs ( the extra parts -the passives and the HC04, extra
board space, inventory costs, pick and place cost, increased failure rate costs, etc) the
price does get closer to parity. Engineering involves tradeoffs of course, but that is
not done properly unless all the costs and potential problems are considered. Using the
FPGA for the inverting gain in an oscillator is not good practice because of the
sensitivity to circuit parameters that you can't control.
Jay wrote:
> The costs are the same? Au contrair mon friar. According to my price
> book the crystal by itself is about 50 cents and the full up
> oscillator is $1.50, thats a dollar difference. So if is a low
> quantity, $1000 Vertex kinda thing, buy the can, but its high volume
> and real price sensitive, engineer and test your own.
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3D8C886A.5EC5478C@andraka.com>...
> > Not reliably. The HC7404 works because it is used as an amplifier, which can
> > be done with a simple inverter. An FPGA has too many gain stages between the
> > pins to be abused as an amplifier in an oscillator circuit. While it may work
> > on the bench, it will not reliably start and maintain the fundamental
> > frequency with variations in temp, process, and voltage. Why not use an
> > integrated xtal oscillator instead of a simple crystal? The costs are nearly
> > the same.
> >
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47469Hello, I'm looking for a really dead virtex. Is anybody have one or several dead virtex to give to me ? Thanks in advance. DavidArticle: 47470
I have a design that will interface an XC2V1000 to a block of SDRAM running at 133MHz as well as a DVI (Digital Video Interface) chip requiring a 24 bit bus at up to 165MHz. I'm looking for guidance as to what speed grade VirtexII device should work for such a design. I can always start with the fastest and then try lower speed grades and see. I'm just wondering if anyone with experience in similar designs might have a bit of advise to offer. Thank, -- Martin E. To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 47471
Dali is right, Depending on what Synthesis tool you are using, you should be able to search for the net inside it. I had a couple of similar problems, but using Leonardo Insight and using the schematic viewer helped me to find the nets and from there it was easy. Another way to do it (if you do not have any EDIF viewer) is to look into the edif file by yourself, and search for the net, and when you find it, try to find everywhere the net is connected and go backwards until you find a name you recognize, it will take a lot of time, but it is much easier than doing it inside Xilinx environment. Another important issue to remember is that Xilinx has internal tri-state busses, so it is not illegal to have multiple drives as long as they are of that type, so maybe someone "hought they made a tri-state buffer, but id didn't work out (believe me it happens :) ) so it is worth checking it out as well, it may or may not be the problem, but who knows. just my 2c, /Farhad Dali <dadicool@ifrance.com> wrote: >I would look in the file generated by your synthesis tool (edif for >synplicity) because that's where the nets are named with such generic names. > >Then you can then look at the net drivers. What you can do also is to >ask the synthesis tool to preserve hierarchy so you can locate the net >into a module easily. > >Dali > >David R Brooks wrote: >> Running the Xilinx ISE 4.2i tools, I get a warning >> ERROR:NgdBuild:455 - logical net 'N812' has multiple drivers >> >> Now the meaning is obvious enough, but the problem is, how to locate >> this net (it is a synthesiser-generated name) in the hierarchy. The >> tools don't give any indication where it is located. It is a large >> project, with over 40 VHDL design elements in a deep hierarchy. >> >> A search of the output files shows none of them contain this string, >> except the NGD log, which only contains the error as above. >> >> This error causes no post-synthesis VHDL file to be generated, else >> one could search that file for the net. >> >> Any ideas? >> >Article: 47472
Ray, I agree. Using an FPGA IOB as an amplifier is something you can make work one time, maybe dozens of times, but with changes in process the parameters can change, and the oscillator may sometimes not start up. The Gain and Phase (and delay) of an IOB ->LUT->IOB is pretty hard to characterize! Fairchild actually has a series of CMOS logic that consists of logic elements in tiny packages (for those pesky need an inverter problems in a cell phones). Austin Ray Andraka wrote: > When you consider all of the costs ( the extra parts -the passives and the HC04, extra > board space, inventory costs, pick and place cost, increased failure rate costs, etc) the > price does get closer to parity. Engineering involves tradeoffs of course, but that is > not done properly unless all the costs and potential problems are considered. Using the > FPGA for the inverting gain in an oscillator is not good practice because of the > sensitivity to circuit parameters that you can't control. > > Jay wrote: > > > The costs are the same? Au contrair mon friar. According to my price > > book the crystal by itself is about 50 cents and the full up > > oscillator is $1.50, thats a dollar difference. So if is a low > > quantity, $1000 Vertex kinda thing, buy the can, but its high volume > > and real price sensitive, engineer and test your own. > > > > Ray Andraka <ray@andraka.com> wrote in message news:<3D8C886A.5EC5478C@andraka.com>... > > > Not reliably. The HC7404 works because it is used as an amplifier, which can > > > be done with a simple inverter. An FPGA has too many gain stages between the > > > pins to be abused as an amplifier in an oscillator circuit. While it may work > > > on the bench, it will not reliably start and maintain the fundamental > > > frequency with variations in temp, process, and voltage. Why not use an > > > integrated xtal oscillator instead of a simple crystal? The costs are nearly > > > the same. > > > > > > > > > -- > > > --Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com > > > > > > "They that give up essential liberty to obtain a little > > > temporary safety deserve neither liberty nor safety." > > > -Benjamin Franklin, 1759 > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 47473
Can you elaborate on this? Vendor? entry method? anything? "help me" <xiong_mao@std.uestc.edu.cn> wrote in message news:ee79351.-1@WebX.sUN8CHnE... > Hi > > I am finding a object file of fpga which can map cells of library to the hardware cells of fpga. > who can tell me where to find it? > thanks.Article: 47474
Well if cost is no object, just buy another Xilinx part and program it as a DP ram. Why does it have to be external? And regarding the gentleman's question about needing dual port ram... In yet another incarnation, a single port memory is deposed to use a databus with twice the data word width. Since accesses are known to be sequential in nature, both writing and reading, pairs of words are alternately written/read at the 1x clock frequency. The main advantage of course being single port memory (mute in Xilinx realization since you've alredy paid for the larger dual port bit cell structure) and of course being able to run at a 1x clock. Regards nagaraj@accord-soft.com (Nagaraj) wrote in message news:<9c782518.0209260147.31279e0c@posting.google.com>... > Dear group members, > I am using Dual Port BlockRAM (of CoreGen IP)in my design (Xilinx > Virtex device). Now my system requirement is such that the DPRAM > should reside outside the FPGA. > I am searching for a Dual Port SRAM IC which is similar to the Dual > Port Block RAM (of CoreGen IP). Except for the functionality > (enable,reset etc.), other things like memory size, physical > size,cost,timing doesn't matter for me. > Could somebody please help in knowing the availability of an IC > atleast close to my requirement? > > Regards, > Nagaraj CS
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z