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Hi Nicholas, Visit http://www.insight-electronics.com/cgi-bin/bvutf8/memec/scripts/local/mc_loc_b.jsp?Div=INSIGHT&Reg=AMERICAS&Country=UNITED_STATES&Lang=EN&isDetailPage=true&EDOID=194160&Manu=XILINX You'll get the board. Regards, SANKET. nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote in message news:<am82id$39f$1@agate.berkeley.edu>... > Are there any Virtex 2 pro development boards available yet, > which provide Gb ethernet interfaces? > > Thanks.Article: 47126
Bernhard, Our Chameleon POD Package comes with a complet VHDL source of our EPP Slave core and of our I2C Master Controler Core. (Normally, the EPP core will become a free IP on our website before the end of Oktober. Maybe visit http:/www.amontec.com/chameleon.shtml in some weeks.) Regards, Laurent Bernhard Holzmayer wrote: > Hello, > > for configuration purposes, I have to connect a PC to my FPGA board. > It's a Spartan2 device. PC must write, not read. > My idea is to connect 8bit data, strobe and busy lines to the FPGA > and serve the PC with usual line printer handshaking. > > This is so fundamental, that I'm quite sure someone did this before. > I'm interested in VHDL code or Simulink/SystemGenerator source > which either gives me hints or (best case) does the job of > handshaking and storing the received data > into a memory/buffer/fifo inside the FPGA. > > > Thanks in advance > Bernhard > >Article: 47127
Also, a 3V battery (or two 1.5's together) will start to drop voltage under load and when it begins to drain. If you use three 1.5V batteries and a regulator you will have a much more stable power source. Watch the dropout voltage though. Of course if this is a lab project and you just want it to work long enough to get it checked off ... Anything goes. -Ryan "Laurent Gauch" <laurent.gauch@amontec.com> wrote in message news:3D881642.2030200@amontec.com... > Normally you have to follow the specification ! > > On our Chameleon POD (CPLD Development board in a dongle format), we > tested and ran the Coolrunner XPLA3 CPLD at 2.8V. All was OK at 2.8V ! ... > > But, for industrial product, respect the Xilinx specification! > > Laurent Gauch, Amontec > http://www.amontec.com > > John wrote: > > > I'm planning on using a Xilinx CoolRunner XPLA3 which requires a 3.3V > > supply (the datasheet says 3.0-3.6V). Would a 3V battery be okay for > > this? > > >Article: 47128
"Alan Fitch" <alan.fitch@doulos.com> wrote in message news:<k0pFl7kWCHA.4780@lucy.doulos.com>...
> Firstly, you might want to try this option.
>
> A for loop
>
> for (i = 0; i<10; i++)
> {
> statements;
> }
>
> can be replaced with
>
> for (i = 0; i < 10) par {
> i++;
> statements;
> }
>
> which speeds up the execution of a for loop.
That's something I didn't know... I was always recoding as a 'while'
loop. Your solution is much easier to follow.
> Secondly, if you use the value of i inside a nested loop, you need
> to be very
> careful to make sure that if you use the outer loop variable in an
> inner loop,
> you are using the correct value (because in Handel-C the variables
> may update
> in parallel rather than sequentially as in C).
>
> <snip complicated code>
>
I solved this by recoding the loop so a shift is performed on each
iteration instead of an increment.
I am getting a new problem though concerning calling a macro procedure
within this complicated loop: see new thread.
> > Also the compiler is throwing up width errors, for instance
> width '8'
> > doesn't match width '4'. For instance
> >
> > while (j<(1<<i))
> >
I solved this by recoding the loop so a shift is performed on each
iteration instead of an increment.
> However the value '1' is not known. Try using
>
> while (j < (unsigned 8)(1 << i))
>
> or declaring a constant to represent the number 1 of the correct
> width, e.g.
>
> static const unsigned 8 ONE = 1;
>
> and then using
>
> ONE << i
>
I like this idea though - will try and make use of it.
Govind
Article: 47129
I've discovered that if I try and call a macro proc within a
complicated loop I get the following error (compiling for Debug):
mini_test.hcc
0 errors, 0 warnings
mini mdct
NAND gates after compilation : 5764272 (17062 FFs, 10752 memory bits)
[Bomb icon] C:\Development\Tools\Compiler\hccompile\main\main.cpp(232)
: Unhandled exception
[Bomb icon] uncaught exception in compiler [CCompilerDll::Compile,
D:\Tools\ide\esl\vhc\CompilerDll.cpp]
Ignoring the mammoth gate count for now (will need to optimise
somehow), here is the offending snippet of code:
/*
* Following lines are a little tricky:
* originally stated:
*
* for (i=1; --stages>0; i++){
* for (j=0; j<(1<<i);j++)
* mdct_butterfly_generic(T,x+(points>>i)*j),points>>i,4<<i);
* }
*/
i = 2;
k = points >> 1; /* points = 128, so k = 64 */
#ifdef SIMULATE
printf("mdct_butterflies: k = points >> 1 = %d",k);
/* prints 64 correctly */
#endif
do{
par
{
j=0;
do{
par
{
/* params are T [w=9], x [w=8], points [w=8], trigint [w=9]*/
/*
* call macro proc
*/
mdct_butterfly_generic(T,x+(k*j),k,0 @ (4*i) );
j++;
}
}while(j < i);
stages--;
i = i << 1;
k = k >> 1;
} /* end of par */
}while(stages>1);
Now if I comment out the call to mdct_butterfly_generic the uncaught
exception is not generated and the code works as it ought to.
mdct_butterfly_generic expects four parameters T, x, points, trigint
of the widths shown, and i, j and k are all unsigned 8
In case anyone would like to play with the full code it is at
http://www.sli-institute.ac.uk/~gk/mdct.zip
(the project is mini mdct and the hcc file is mini_test.hcc)
Cheers,
Govind
Article: 47130Bernhard Holzmayer wrote: > Hello, > > for configuration purposes, I have to connect a PC to my FPGA board. > It's a Spartan2 device. PC must write, not read. > My idea is to connect 8bit data, strobe and busy lines to the FPGA > and serve the PC with usual line printer handshaking. > > This is so fundamental, that I'm quite sure someone did this before. > I'm interested in VHDL code or Simulink/SystemGenerator source > which either gives me hints or (best case) does the job of > handshaking and storing the received data > into a memory/buffer/fifo inside the FPGA. > > > Thanks in advance > Bernhard > Its pretty trivial, but you will probably need a RC filter followed by a Schmitt trigger to clean up the strobe (=config clock) at the FPGA end of the cable. You dont need to connect to the FPGA's BUSY since you have no chance to send data faster than the 50 or so MHz that requires looking at the FPGA's BUSY. You will probably want to connect one of the parallel ports output handshaking lines to PROGRAM, and two of the input handshaking lines to DONE and INIT so you can determine if the FPGA configured properly from the host side... Peter WallaceArticle: 47131
yep, you can even order industrial parts and run down to 2.7v John wrote: > I'm planning on using a Xilinx CoolRunner XPLA3 which requires a 3.3V > supply (the datasheet says 3.0-3.6V). Would a 3V battery be okay for > this?Article: 47132
On Wed, 18 Sep 2002 16:29:29 +1000, Jason Crawford <jace@cisco.com> wrote:
>
>I'm wondering whether Xilinx(or 3rd party) provide an IP
>linear-log converter function. I'm specifically after a
>32-bit linear (input) to 8-bit log (output) converter.
I know nothing about available IP. If what you want is
5 bits of exponent, 3 bits of mantissa, any of the wizened
old experts in this group should be able to throw together
a 7-stage pipelined datapath that fits in about 130 4-LUT
cells. The final mantissa lookup is very easy, since the
accuracy is so low. The conditional shifting to generate
the exponent is what eats up the pipeline stages and LUTs.
- Larry
Article: 47133In article <43d33245.0209180629.4139094b@posting.google.com>, Sanket Xilinx FAE Insight <sanket_b@indiatimes.com> wrote: >Hi Nicholas, >Visit >http://www.insight-electronics.com/cgi-bin/bvutf8/memec/scripts/local/mc_loc_b.jsp?Div=INSIGHT&Reg=AMERICAS&Country=UNITED_STATES&Lang=EN&isDetailPage=true&EDOID=194160&Manu=XILINX > >You'll get the board. Thanks. It doesn't have Gb magnetics on it, which is what I'm largely interested in. How well can Gb ethernet magnetics be hooked up though the breakout pins? -- Nicholas C. Weaver nweaver@cs.berkeley.edu Nick's Design Rule: When in doubt, cheatArticle: 47134
I'm going to use a Xilinx CoolRunner XPLA3, and am planning on making an oscillator circuit do drive the clock. The circuit is a basic one I've found for a 32.768kHz signal and consists of the crystal, two resistors, two capacitors, and an inverter. I am aiming for a low-power, low-cost design, and it seems that external inverters cost around 50 cents. Would it be okay to use one of the CPLD's inverters? I know that for my oscillator circuit the inverter must be unbuffered (ie one inverter in the package instead of the standard three) to avoid distortion. Would I have too much distortion using the CPLD? If so, is anyone aware of any alternate solutions (aside from a pre-built oscillator circuit.. these seem to require too much power)? Thanks a lot!Article: 47135
From personal experience years ago, let me warn you. It might work, but you will be using a multi-stage amplifier biased in the linear region. Plenty of opportunity for high power consumption and strange behavior, like overtone oscillation, poor start-up when Vcc is applied fast of slowly, etc. Investigate it well, for people have been "burnt". I would go for a canned oscillator package. Look at Maxim's ( formerly Dallas) ultra-accurate oscillator. Peter Alfke ============================== John wrote: > I'm going to use a Xilinx CoolRunner XPLA3, and am planning on making > an oscillator circuit do drive the clock. The circuit is a basic one > I've found for a 32.768kHz signal and consists of the crystal, two > resistors, two capacitors, and an inverter. > I am aiming for a low-power, low-cost design, and it seems that > external inverters cost around 50 cents. Would it be okay to use one > of the CPLD's inverters? I know that for my oscillator circuit the > inverter must be unbuffered (ie one inverter in the package instead of > the standard three) to avoid distortion. Would I have too much > distortion using the CPLD? If so, is anyone aware of any alternate > solutions (aside from a pre-built oscillator circuit.. these seem to > require too much power)? Thanks a lot!Article: 47136
All the pins that are not involved in the configuration are 3-stated (tristated) with a weak internal pull-up in the tens of kilohms. And they stay that way until configuration is completed. Peter Alfke, Xilinx Applications. ====================== Stamatis Sotiropoulos wrote: > Hi all, > I use a Xilinx XC4010XL FPGA. Before programming the FPGA I need to > precisely know the state of all its I/O pins. Where can I find this piece of > info? I have looked in the relative FPGA datasheet but there is no such > info. > Please advise. > > thanks in advance! > StamatisArticle: 47137
John wrote: > > I'm going to use a Xilinx CoolRunner XPLA3, and am planning on making > an oscillator circuit do drive the clock. The circuit is a basic one > I've found for a 32.768kHz signal and consists of the crystal, two > resistors, two capacitors, and an inverter. > I am aiming for a low-power, low-cost design, and it seems that > external inverters cost around 50 cents. In what volumes ? HEF4069 show appx 12c / 2500 ? > Would it be okay to use one > of the CPLD's inverters? I know that for my oscillator circuit the > inverter must be unbuffered (ie one inverter in the package instead of > the standard three) to avoid distortion. Would I have too much > distortion using the CPLD? If so, is anyone aware of any alternate > solutions (aside from a pre-built oscillator circuit.. these seem to > require too much power)? Thanks a lot! Using CPLD inverter : Quick answer NO. ( which will actually be much more than THREE inverters .. ) Besides the main issue of stability, there are also ones of phase margin, and linear-region current. Options: For 32KHz, you need low drive, to get the correct phase margin. Depending on your Vcc, look at the HEF4069, or AHCU04 ( same pinout, try both ? ). Use one inverter to make the OSC, and the other 5 to squareup the sine wave to edges fast enough to clock the CPLD. You need fast edges to miminise the linear region current, as well as avoid ground bounce multiple clocking effects. With a little care, you can also use HEF40106 (Schmitt) - choose a large Rfb, so it oscillates < 32KHz in RC mode, and then the XTAL will 'lock' the oscillation once it starts. 32KHz xtals have a long startup time. - jgArticle: 47139
What's the status of Spartan II pins before and during configuration? Are all the I/O pins tri-stated? Regards, TDArticle: 47140
The single transistor oscillator portion of this app note might be of some use to you: http://www.maxim-ic.com/appnotes.cfm/appnote_number/181 The remaining challenge is to find a cheap, low-power way to amplify and square up the slow oscillator output so it can be used as a clock. The Coolrunner 3 seems to want rise/fall times of less than 20 ns on its clocks. You MIGHT think about trying to use a CPLD inverter to do this - biasing the AC-coupled input to VCC/2 and driving the clock pin with the inverter output, but since the inverter input spends so much time in the linear region it will likely consume significant amounts of power - possibly several mA. Maybe another transistor gain stage would help? regards, Tom John wrote: > I'm going to use a Xilinx CoolRunner XPLA3, and am planning on making > an oscillator circuit do drive the clock. The circuit is a basic one > I've found for a 32.768kHz signal and consists of the crystal, two > resistors, two capacitors, and an inverter. > I am aiming for a low-power, low-cost design, and it seems that > external inverters cost around 50 cents. Would it be okay to use one > of the CPLD's inverters? I know that for my oscillator circuit the > inverter must be unbuffered (ie one inverter in the package instead of > the standard three) to avoid distortion. Would I have too much > distortion using the CPLD? If so, is anyone aware of any alternate > solutions (aside from a pre-built oscillator circuit.. these seem to > require too much power)? Thanks a lot!Article: 47141
--------------2D46051E91D5C3F955D95482 Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353" Content-Transfer-Encoding: 7bit >From the Spartan-II Data Sheet (Archtectural Description, Input/Output Block, fifth paragraph): Prior to configuration all outputs not involved in configuration are forced into their high-impedance state. Pull-down resistors and week keeper circuits are inactive, but inputs may optionally be pulled up. And a few pages later on: Table 8 describes the ways to select or deselect the internal pull-ups before configuration. During configuration the pins behave the same way as before configuration. Hope that helps Peter Alfke, Xilinx Applications ======================= Test wrote: > What's the status of Spartan II pins before and during configuration? Are all the I/O pins tri-stated? > > Regards, > TDArticle: 47142
Giuseppe, This is correct. Windows XP and Windows 2000 will be the only supported Microsoft operating systems for 5.1i, although 5.1i should still install and run fine on Windows NT. Regards, Kamal Patel Xilinx AppsArticle: 47143
You don't mention the required performance. It makes a huge difference.
Particularly, you need to state the sample rate as well as the
coefficient update rate. It would also help to know the precision (bits)
of the inputs and coefficients. There are ways to do this, subject to
certain restrictions. Let's see what your requirements are first.
Dongho wrote:
> Hi,
>
> I'd like to implement adaptive FIR filter with 100 tap in FPGA.
> To implement this, I need 100 multiplier to multiply weight.
> How to measure the area(or gate?) to measure this filter so that I
> can find appropriate chip?
> Thanks in advance for your response.
>
> -Regards
>
> dongho
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47144
We have two versions of linear to log conversion in our IP
library. One gets roughly 1/2 dB, the other is
parameterized to get as much precision as you want (We're
using it in one project that has a requirement for the log
to be accurate to 0.005 dB. Both can be modified for
arbitrary log base.
Jason Crawford wrote:
> Hi,
>
> I'm wondering whether Xilinx(or 3rd party) provide an IP
> linear-log converter function. I'm specifically after a
> 32-bit linear (input) to 8-bit log (output) converter.
>
> Any help appreciated.
>
> tks
> Jason.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 47145
Peter, your early TTL roots are showing through.
Yes, ripple counters do have their place, especially in devices that don't have a carry chain. Several years back, we did a CRT display design that had to meet NTSC color timing exactly using a 2064 and an external RAM. We used several ripple counters in that design in order to get it to fit in. I think we had 2 or 3 luts left when we finished (it was a retrofit), where synchronous counters would have exceeded the device by a good 10%.
Peter Alfke wrote:
> Since I started this suggestion of using ripple clocks, I might as well answer:
> The clocks are not combinatoril outputs, they are the MSB flip-flop in each decade.
> Clock skew between nets is not an issue, since this is a ripple design. Every downstream clock is inherently later than the upstream clock, and the delay is irrelevant. The only concern would be that each clock must reach its four flip-flops "simultaneously", i.e. with less skew than the clock-to-out plus set-up. Since the four flip-flops fit naturally in one CLB, this is not an issue.
> Unconventional? Yes. Unreliable? No. And simple to design and low power.
> Not good for every application, but good for some.
>
> Peter Alfke, Xilinx Applications
>
> Andreas Loew wrote:
>
> > I would avoid using the (combinatorical) output of one devider stage as a clock for the next one, If you do this you have to look at the clock skew of all those clock nets. Your devider counters may not function proper if there is a skew on the clock. The only solution that works worst case is a syncronous design, all running with the highest clock and the devider modules provide a CE for the next stage. The CE should be generated with Look Ahead and a FF.
> > Regards
> > Andreas
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47146I can't claim to be an expert, but what I think you want to do isn't going to work. You can't take any arbitrary C/C++ program and convert it into VHDL code that will run on an FPGA. For making something like a hardware mp3 player, you may want to look at something like a programmable DSP board. Also, you should check on what, if any, analog outputs are avilable from the FPGA you're using. For example, on the Altera student board, the only analog output is for a VGA monitor, so if you wanted to make an mp3 player using one you'd need to build an interface to convert the decoded digital audio into analog audio. Mike On Tue, 17 Sep 2002 09:27:21 +0000, DJohn wrote: > Hi all VHDL experts, > Is there any tools which can convert a C\C++ source file to VHDL . For > example If I have a C source code for a MP3 decoder , Can any tool can > convert it into VHDL equivalent. There is some facility in FPGA > Advantage to generate a wrapper VHDL for a C File , what exactly is > that ? Does that mean I can synthesize a C\C++ file by creating a VHDL > Wrapper. Please helpArticle: 47147
Thanks for all your comments. -- Pete Dudley Arroyo Grande Systems "Pete Dudley" <pete.dudley@comcast.net> wrote in message news:1tah9.65472$gf6.2187070@bin4.nnrp.aus1.giganews.com... > Hello All, > > Before you guys jump all over me I should state up front that I do not want > to synthesize any floating point operations. If you want to give the obvious > answer that reals don't synthesize you can find that already at this link. > http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&threadm=3B15A80F.4239026F > %40uoguelph.ca&rnum=1&prev=/groups%3Fq%3Dmath_real%2Bgroup:comp.arch.fpga%26 > hl%3Den%26lr%3D%26ie%3DUTF-8%26selm%3D3B15A80F.4239026F%2540uoguelph.ca%26rn > um%3D1 > > My question relates to computing the integer values of a look up table by > using real operations and rounding to the desired integer values. Something > like you would do in matlab or C but I want to do it right in my code to > have a single source that's parameterizable for word width and table depth. > In other words I want to > include a little initialization loop like this. > > for i in 0 to 255 loop > table(i) <= signed(round(64.0*sin(2*pi*i/256))); > end loop; > > What I'm finding is that XST errors out, saying "Undefined symbol 'real'" > when I include the math_real library. > > Can anyone tell me if this is possible in vhdl? > > I'm starting to think about using a general purpose language for synthesis > so little tasks like this are not so trying. See www.jhdl.org for one > possibility. > > -- > Pete Dudley > > Arroyo Grande Systems > > > > >Article: 47149
Not exactly. There are several vendors that have C to hardware compilers,
but don't expect to take plain vanilla C and compile it directly to hardware.
For the most part, these tools use subsets and extensions to C to permit
description of hardware and all the parallelism that implies in a C-like
environment. It raises the level of abstraction, and as a result you tend to
get a design that is more bloated and slower than one done closer to the
hardware. The point is that there is no free lunch, there is a considerable
engineering effort to convert your software to something that will run at a
reasonable speed in an FPGA that you can afford to buy.
mike wrote:
> I can't claim to be an expert, but what I think you want to do isn't
> going to work. You can't take any arbitrary C/C++ program and convert it
> into VHDL code that will run on an FPGA. For making something like a
> hardware mp3 player, you may want to look at something like a
> programmable DSP board. Also, you should check on what, if any, analog
> outputs are avilable from the FPGA you're using. For example, on the
> Altera student board, the only analog output is for a VGA monitor, so if
> you wanted to make an mp3 player using one you'd need to build an
> interface to convert the decoded digital audio into analog audio.
> Mike
>
> On Tue, 17 Sep 2002 09:27:21 +0000, DJohn wrote:
>
> > Hi all VHDL experts,
> > Is there any tools which can convert a C\C++ source file to VHDL . For
> > example If I have a C source code for a MP3 decoder , Can any tool can
> > convert it into VHDL equivalent. There is some facility in FPGA
> > Advantage to generate a wrapper VHDL for a C File , what exactly is
> > that ? Does that mean I can synthesize a C\C++ file by creating a VHDL
> > Wrapper. Please help
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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