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Hi, Doing a floating-point operation (add/sub/mult) takes around 5-6 clock cycles in a FPGA at 125 MHz clock frequency. That will give you something around 15-20 MFLOPS. How much does a 50MHz DSP produce? G=F6ran William Hall wrote: > I'm looking at using the Xilinx V2PRO / PowerPC for some floating point= > work. > > I gather that this has no floating point hardware. Is it > sensible/practical to have an FP Multiplier/Divider on the FPGA? > > How good is it anyway at FP operations? If one can clock it at 300MHz > perhaps it will keep up with a 50MHz DSP (?) > > William Hall > Remove any X in my email addressArticle: 46101
When I simulates the following code this warning message is displayed at time 0ns. # ** Warning: Invalid ADDRESS: XXXXXXXXXX. Memory contents will be set to 'X'. # Time: 0 ps Iteration: 3 Instance: /theram This means that I can't simulate with correct INIT values!! All addresses and control signals are constant but the clock inputs are toggled. Have I done anything stupid? Is there an error in the simulation model? This code is a debug version of my real design just to track the simulation error. I thought that if WEx is de-asserted nothing should happen to the memory contents whatever the other signals looks like. /Patrik Eriksson ----------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; -- synthesis translate_off library unisim; -- synthesis translate_on entity bram_tb is end entity bram_tb; architecture sim of bram_tb is component BUFG port ( I : in std_logic; O : out std_logic); end component; component IBUFGDS_LVPECL_33 port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic); end component; component DCM -- synthesis translate_off generic ( DLL_FREQUENCY_MODE : string := "LOW"; CLKOUT_PHASE_SHIFT : string := "NONE"; PHASE_SHIFT : integer := 0; CLKFX_MULTIPLY : integer := 4; CLKDV_DIVIDE : real := 2.0 ); -- synthesis translate_on port ( CLKIN : in std_logic; CLKFB : in std_logic; DSSEN : in std_logic; PSINCDEC : in std_logic; PSEN : in std_logic; PSCLK : in std_logic; RST : in std_logic; CLK0 : out std_logic; CLK90 : out std_logic; CLK180 : out std_logic; CLK270 : out std_logic; CLK2X : out std_logic; CLK2X180 : out std_logic; CLKDV : out std_logic; CLKFX : out std_logic; CLKFX180 : out std_logic; LOCKED : out std_logic; PSDONE : out std_logic; STATUS : out std_logic_vector(7 downto 0) ); end component; component RAMB16_S9_S9 -- synthesis translate_off generic ( WRITE_MODE_A : string; WRITE_MODE_B : string; INITP_00, INITP_01, INITP_02, INITP_03, INITP_04, INITP_05, INITP_06, INITP_07, INIT_00, INIT_01, INIT_02, INIT_03, INIT_04, INIT_05, INIT_06, INIT_07, INIT_08, INIT_09, INIT_0A, INIT_0B, INIT_0C, INIT_0D, INIT_0E, INIT_0F, INIT_10, INIT_11, INIT_12, INIT_13, INIT_14, INIT_15, INIT_16, INIT_17, INIT_18, INIT_19, INIT_1A, INIT_1B, INIT_1C, INIT_1D, INIT_1E, INIT_1F, INIT_20, INIT_21, INIT_22, INIT_23, INIT_24, INIT_25, INIT_26, INIT_27, INIT_28, INIT_29, INIT_2A, INIT_2B, INIT_2C, INIT_2D, INIT_2E, INIT_2F, INIT_30, INIT_31, INIT_32, INIT_33, INIT_34, INIT_35, INIT_36, INIT_37, INIT_38, INIT_39, INIT_3A, INIT_3B, INIT_3C, INIT_3D, INIT_3E, INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000" ); -- synthesis translate_on port ( DIA : in std_logic_vector(7 downto 0); DIPA : in std_logic_vector(0 downto 0); DIB : in std_logic_vector(7 downto 0); DIPB : in std_logic_vector(0 downto 0); ENA : in std_ulogic; ENB : in std_ulogic; WEA : in std_ulogic; WEB : in std_ulogic; SSRA : in std_ulogic; SSRB : in std_ulogic; CLKA : in std_ulogic; CLKB : in std_ulogic; ADDRA : in std_logic_vector(10 downto 0); ADDRB : in std_logic_vector(10 downto 0); DOA : out std_logic_vector(7 downto 0); DOPA : out std_logic_vector(0 downto 0); DOB : out std_logic_vector(7 downto 0); DOPB : out std_logic_vector(0 downto 0) ); end component; constant INITP : bit_vector := X"1041000100001400010000100040100001400010004100041000100004000104"; constant INIT : bit_vector := X"1001000100001000010000100000100001000010000100001000100001000100"; signal clk_p, clk_n, clk, rst : std_logic; signal clk_ibufg, clk_bufg : std_logic; begin -- architecture sim INBUF: IBUFGDS_LVPECL_33 port map ( O = clk_ibufg, I = clk_p, IB = clk_n); GLOBALBUFFER: BUFG port map ( I = clk_ibufg, O = clk_bufg); clk <= clk_bufg; THERAM: RAMB16_S9_S9 generic map ( WRITE_MODE_A = "WRITE_FIRST", WRITE_MODE_B = "READ_FIRST", INITP_00 = INITP, INITP_01 = INITP, INITP_02 = INITP, INITP_03 = INITP, INITP_04 = INITP, INITP_05 = INITP, INITP_06 = INITP, INITP_07 = INITP, INIT_00 = INIT, INIT_01 = INIT, INIT_02 = INIT, INIT_03 = INIT, INIT_04 = INIT, INIT_05 = INIT, INIT_06 = INIT, INIT_07 = INIT, INIT_08 = INIT, INIT_09 = INIT, INIT_0A = INIT, INIT_0B = INIT, INIT_0C = INIT, INIT_0D = INIT, INIT_0E = INIT, INIT_0F = INIT, INIT_10 = INIT, INIT_11 = INIT, INIT_12 = INIT, INIT_13 = INIT, INIT_14 = INIT, INIT_15 = INIT, INIT_16 = INIT, INIT_17 = INIT, INIT_18 = INIT, INIT_19 = INIT, INIT_1A = INIT, INIT_1B = INIT, INIT_1C = INIT, INIT_1D = INIT, INIT_1E = INIT, INIT_1F = INIT, INIT_20 = INIT, INIT_21 = INIT, INIT_22 = INIT, INIT_23 = INIT, INIT_24 = INIT, INIT_25 = INIT, INIT_26 = INIT, INIT_27 = INIT, INIT_28 = INIT, INIT_29 = INIT, INIT_2A = INIT, INIT_2B = INIT, INIT_2C = INIT, INIT_2D = INIT, INIT_2E = INIT, INIT_2F = INIT, INIT_30 = INIT, INIT_31 = INIT, INIT_32 = INIT, INIT_33 = INIT, INIT_34 = INIT, INIT_35 = INIT, INIT_36 = INIT, INIT_37 = INIT, INIT_38 = INIT, INIT_39 = INIT, INIT_3A = INIT, INIT_3B = INIT, INIT_3C = INIT, INIT_3D = INIT, INIT_3E = INIT, INIT_3F = INIT) port map ( DIA = "00000000", DIPA = "0", DIB = "00000000", DIPB = "0", ENA = '1', ENB = '1', WEA = '0', WEB = '0', SSRA = '0', SSRB = '0', CLKA = clk_p, CLKB = clk, ADDRA = "00000000000", ADDRB = "00000000000", DOA = open, DOPA = open, DOB = open, DOPB = open); -- CLK process process begin clk_p <= '0'; clk_n <= '1'; loop wait for (10 ns); clk_p <= not clk_p; clk_n <= not clk_n; end loop; end process; MAIN: process begin -- process MAIN rst <= '1'; wait for 10 ns; rst <= '0'; wait; end process MAIN; end architecture sim; -- Patrik Eriksson | patrik.eriksson@netinsight.net Net Insight AB | phone: +46 8 685 04 89 Västberga Allé 9 | fax: +46 8 685 04 20 SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.netArticle: 46102
-- You want :
-- clk -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_
-- x _______________-----_____------_____
-- x_reg ________________-----_____------____
-- x_pulse _______________-_________-__________
-- The easy way
process (rst,clk) -- rst for reset
begin
if rst = '1' then
x_reg <= '0';
elsif rising_edge(clk) then
x_reg <= x;
end if;
end process;
-- rising detection
x_pulse <= '1' when (x = '1' and x_reg = '0') else '0' ;
-- falling detection
--x_pulse <= '1' when (x = '0' and x_reg = '1') else '0' ;
-- both edge detection
--x_pulse <= '1' when ((x = '1' and x_reg = '0') or
(x = '0' and x_reg = '1')) else '0' ;
---------------
Laurent Gauch
Amontec
http://www.amontec.com
_______________________
Your FPGA Design Partner
shay wrote:
> Hellow!
> I want generate pulse when detect rising_edge of specific signal,
> and supply this pulse to enother box and execute command due to this
> pulse & after off some flag & wait to next rising_edge.
> Note: the 2 boxes (detect rising_edge and execute command) are use
> with different sync.
> (in VHDL)
> Thanks in advance!!!
>
Article: 46103nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote in message > Use LCC, its much easier to retarget. > > Also, how much do you REALLY gain vs having more established tools? While it is true that LCC is easier to retarget than gcc, you should take a long hard look at SUIF. A group at my former university produced a retargetable backend for SUIF that would generate code for hypothetical ISA (for ISA comparisons with an associated processor simulator). When that typeof flexibility is not required, retargeting SUIF to output code for a single ISA is not much work. (Sorry, no links - the WWW server is still down due to the flood in Dresden.) Achim.Article: 46104
Hi, Can someone tell me whether it is possible to dynamically reconfigure the contents of the memory in FPGA ,without connecting to a external PROM or a host computer ?. Thanks, Ram.Article: 46105
I am an experienced ASIC designer with a little bit of DSP coursework and I would like to learn more about implementing DSP algorithms in hardware. I think that implementing various hardware architectures in FPGA's would be a useful learning exercise which could be done fairly quickly and cheaply using my available PC resources at home and work. I have access to Verilog/VHDL simulation tools and am familiar with the available Web baseline FPGA tools. The pieces I think I am missing are the visualization and verification portion of the development: Visualization - I want to be able to take input and output data streams in both the time and frequency domain and graphically display them. Verification - I need a baseline with which I can compare my hardware implementation to verify it is working correctly. I know something like Matlab or Mathcad would probably do what I am looking for, but they seem rather expensive. Can anyone offer other ideas? Does what I am planning sound reasonable? TomArticle: 46106
That is about right for a one size fits all ieee FPU. We've done quite a bit
with custom partial floating point units at higher speeds. For example,
we've got a radar system that has a wide dynamic range coming out of the
correlator, but the precision only needs to be about 10 bits. By converting
to a float with something like 12e5, we can do the post processing in
floating point at quite high rates (160 MHz in this case, a virtexE-6).
FPGAs also give you the freedom to separate the mantissa off, treat that as
fixed point for a series of operations then put it back together with the
exponent rather than normalizing at every step. In cases where the precision
is not high but the dynamic range is, the floating point can actually save
you hardware over an equivalent fixed point (this happens when there are
things like multiplies or rotations in the data path).
Goran Bilski wrote:
> Hi,
>
> Doing a floating-point operation (add/sub/mult) takes around 5-6 clock
> cycles in a FPGA at 125 MHz clock frequency.
> That will give you something around 15-20 MFLOPS.
> How much does a 50MHz DSP produce?
>
> Göran
>
> William Hall wrote:
>
> > I'm looking at using the Xilinx V2PRO / PowerPC for some floating point
> > work.
> >
> > I gather that this has no floating point hardware. Is it
> > sensible/practical to have an FP Multiplier/Divider on the FPGA?
> >
> > How good is it anyway at FP operations? If one can clock it at 300MHz
> > perhaps it will keep up with a 50MHz DSP (?)
> >
> > William Hall
> > Remove any X in my email address
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46107I'm really interested in this too. The SOF format is straight configuration data. Xilinx has an app note (151) that goes into great detail on how the parts are configured. Does Altera have anything remotely resembling this?? In my opinion the ability to deterministically generate the bitstream is the key to extreme high performance computing. For example the DES encryption done with JBits. You give JBits the key and it generates a bitstream design based on that key. It's the fastest known DES encryption and beats all ASIC implementations. When you create hardware based on the data you want to analyze you can built an optimized programmable machine that runs faster than a full custom, but more general purpose, ASIC. However you can't do this very fast with the current main stream tools. Maybe someone at Altera can come up with a document that describes their bitstream. Actually the Xilinx appnote does not include routing. If you document routing you could be ahead of Xilinx in this area. One last thought. There is a lot of information in different places about the bitstream formats of lots of vendors. It might be nice to get all that information together as an open bitstream website. The Xilinx tools kick out a full description of the bitstream via xdl. By cross referencing app151 it might be possible to write a program that takes that data and puts out a bitstream. Put the VPR place and router from U of Toronto in the loop and you have a replacement for the current tools. Steve PS If there is a document on the Altera bitstream that needs a non-disclosure let me know Thanks! "Bernhard Rieder" <rieder@decomsys.com> wrote in message news:5hk1mukhphdhbtf7ph056rak2fka7kid6e@4ax.com... > > Hi, > > Has anybody Information how to manipulate the contents of ROM cells of > Altera FPGAs after Synthesis. I found a similar Topic in the archive > with one reply stating that Quartus 2.1 might be able to do this. > > However I would like to do this manually by changing the appropriate > bitsd in the SOF file (assuming that the each EAB block has a constant > position in the SOF File and assigning the ROM to specified EABs). > > I've been able to find out the EAB positions in the SOF File, but > unfortunately the SOF File contains some checksums. Is there a > description of the SOF File format (especially the used checksums). > > thanks in advance, > BernhardArticle: 46108
"Ramakrishnan" <rxv20@po.cwru.edu> schrieb im Newsbeitrag news:15cf85fc.0208190913.50dc29b4@posting.google.com... > Hi, > Can someone tell me whether it is possible to dynamically > reconfigure the contents of the memory in FPGA ,without connecting to > a external PROM or a host computer ?. So where will you store the configuration data? You can also use a uC + FLASH. -- MfG FalkArticle: 46109
Ramakrishnan wrote:
>
> Hi,
> Can someone tell me whether it is possible to dynamically
> reconfigure the contents of the memory in FPGA ,without connecting to
> a external PROM or a host computer ?.
>
> Thanks,
>
> Ram.
You will have to be more specific than that. Do you mean the embedded
BlockRAM and Distributed RAM, or the configuration memory. The answer
for both is yes, but they are very different solutions.
Phil
--
--------------------------------------------------------------
__
/ /\/ Dr Phil James-Roxby Direct Dial: 720.652.3767
\ \ Sr. Staff Software Engineer Fax : 720.652.3599
/ / Reconfigurable Logic Group
\_\/\ Xilinx Labs @ Longmont,CO Phil.James-Roxby@xilinx.com
--------------------------------------------------------------
Article: 46110Has anyone had any Stratix experience? Problems? Bugs? Availability? Starting a new project....Stratix looks nice... Thanks, BruceArticle: 46111
This isnt a FPGA issue so much as it is a PCI issue, so I apologize for being slightly off topic. I am using the Insight Electronics Xilinx 2S200 PCI32 development board and I have a design loaded that misbehaves in my older Compaq (circa 1997) PC. In other (newer?) machines the same design in the same card behaves perfectly. In this case the OS is the same among the PCs being tested -- Win2k. My problem is that the host initiator, via an app on the command line, initiates a single DWORD read from SDRAM on the card. The target then issues a retry (STOP# is asserted while IRDY# and DEVSEL# are asserted. TRDY# is not ever asserted). The problem I am having is that the host initiator is not properly recognizing the retry, and reports the bogus data present on the bus to my application. It is also interesting to note that the initiator asserts FRAME# for two clocks before deasserting and then asserting IRDY#. Also, the one similarity the failing PCs have is that they are both SCSI. Have you ever heard of SCSI PCs having particular problems with PCI retries? Does the SCSI chipset somehow interfere with, or have strange requirements for, its interface to the PCI bus? Many other PCI designs work on this card, so I cannot fault the card. The PC, chipset, etc. is of course suspect. Any ideas? Does this sound familiar to anyone? Any help is appreciated. Austin, are you out there? Regards, Tom --- Tom Curran tom_curran@memecdesign_dot_comArticle: 46112
Has anyone come across any 3rd party prototype boards for Actel FPGA's? It seems as if Actel's stuff starts at ~$1k, and I was looking for one closer to the $500 range. Thanks, --JoshArticle: 46113
Hi there, Try use 4x clock, (your input may reduce to 50 mhz) We did that in spatan2 (input = 40 mhz)Article: 46114
Hi all, It's just a classical 1 shot circuit, 2 flipflops can do the job well!Article: 46115
All rising or falling-edge detectors use an AND gate between the incoming signal and a delayed and inverted version of that signal. If you have no clock available, use an analog delay ( not very stable, but can be very fast.) If you have a clock, use it to delay the input, but that creates an output of unpredictable duration ( depending on the phase relationship between the input and the clock). Better to use a 2-stage register and thus implement a true digital differentiator. Substituting the AND with an XOR or XNOR differentiates both edges. Peter Alfke ( remember me? Back from a 4-week European vacation). ======================= Laurent Gauch wrote: > -- You want : > > -- clk -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_ > -- x _______________-----_____------_____ > -- x_reg ________________-----_____------____ > -- x_pulse _______________-_________-__________ > > -- The easy way > > process (rst,clk) -- rst for reset > begin > if rst = '1' then > x_reg <= '0'; > elsif rising_edge(clk) then > x_reg <= x; > end if; > end process; > > -- rising detection > x_pulse <= '1' when (x = '1' and x_reg = '0') else '0' ; > > -- falling detection > --x_pulse <= '1' when (x = '0' and x_reg = '1') else '0' ; > > -- both edge detection > --x_pulse <= '1' when ((x = '1' and x_reg = '0') or > (x = '0' and x_reg = '1')) else '0' ; > > --------------- > Laurent Gauch > Amontec > http://www.amontec.com > _______________________ > Your FPGA Design Partner > > shay wrote: > > > Hellow! > > I want generate pulse when detect rising_edge of specific signal, > > and supply this pulse to enother box and execute command due to this > > pulse & after off some flag & wait to next rising_edge. > > Note: the 2 boxes (detect rising_edge and execute command) are use > > with different sync. > > (in VHDL) > > Thanks in advance!!! > >Article: 46116
What kind of simulation did you run? timing, functional? Have you tried to use the "gate point simulation.." , it may work!!!Article: 46117
SNR improvement by averaging only works as expected when the samples are statistically independant. Even for a random input signal, adjacent samples from the output of a low pass filter at 4X or 8X oversampling rate are not really independant any more - they have been smooshed together (convolved) by the weighted averaging going on inside the filter. If you can convince yourself that you don't need to calculate the redundant output samples, a number of options exist which can be implemented using polyphase techniques: 1) Run (most of) the filter at 1/Nth the clock rate - saves power. Running the downstream signal processing at 1/Nth the rate also saves power. 2) Use 1/Nth the amount of hardware resources to implement the filter (e.g. multiplexing the coefficients) and run it at full clock rate - saves hardware 3) Use the same amount of resources to build a N times better filter (more taps, wider coefficents). regards, tom Noddy wrote: > I'm using FIR filters in Spartan IIs (200) for radio astronomical > applications. Right now I have two 40 tap LP filters per FPGA (cut-off > approximately 0.125) running at 32MHz. The input is a 4 bit quadrature > signal, with post detection integration after the filters of the order of > 2^14 samples. This long integration is neccessary in order to obtain the > signal which is about 6 orders of magnitude less than the noise. > > Now, my question is this: would there be any advantage in switching to a > polyphase filtering technique? I don't know much about it...I see it usually > involves some decimation and interpolation, although I am not keen to start > throwing away samples as every sample helps to increase the SNR by averaging > out the noise. > > Thanks > > Adrian > > >Article: 46118
Peter Alfke wrote > Peter Alfke ( remember me? Back from a 4-week European vacation). Did you find where the rain is hiding :-)Article: 46119
Hi, Tim I spent 2 weeks in Provence ( climate like California...) and one week on the river Yonne, S.E. of Paris ( some rain at night) Then a week in western Germany, no rain at all. The horrible rain and flooding was (or is) much further east; the flood is still on its way down the river Elbe towards Hamburg. Lucky me :-) Peter ================================== Tim wrote: > Peter Alfke wrote > > > Peter Alfke ( remember me? Back from a 4-week European vacation). > > Did you find where the rain is hiding :-)Article: 46120
Hi Tom, I remember...way back in my memory banks...that one Intel chipset had a problem with single word transfers/retries...something like you're describing. My PCI protocol was perfectly correct, but the chipset ignored the STOP/IRDY etc. assertion...and didn't turn the bus around in one cycle after STOP per PCI spec or something like that. AND it worked fine on every other machine/chipset... I did fix it BTW. It was a bit of work though... I take the easy way around problems like this now, I bought a high end PCI protocol analyzer, and if you want me to run it on the system/board combination, I certainly can...please contact me off list for details. I can turn it around in a day. Regards, Austin "tom curran" <tom_curran@memecdesign_dot_com> wrote in message news:vvh2muc1n2u2r3g2fkqpd0ag0e2g8q63uc@4ax.com... > This isnt a FPGA issue so much as it is a PCI issue, so I apologize > for being slightly off topic. > > I am using the Insight Electronics Xilinx 2S200 PCI32 development > board and I have a design loaded that misbehaves in my older Compaq > (circa 1997) PC. In other (newer?) machines the same design in the > same card behaves perfectly. In this case the OS is the same among > the PCs being tested -- Win2k. My problem is that the host initiator, > via an app on the command line, initiates a single DWORD read from > SDRAM on the card. The target then issues a retry (STOP# is asserted > while IRDY# and DEVSEL# are asserted. TRDY# is not ever asserted). > The problem I am having is that the host initiator is not properly > recognizing the retry, and reports the bogus data present on the bus > to my application. It is also interesting to note that the initiator > asserts FRAME# for two clocks before deasserting and then asserting > IRDY#. > > Also, the one similarity the failing PCs have is that they are both > SCSI. Have you ever heard of SCSI PCs having particular problems with > PCI retries? Does the SCSI chipset somehow interfere with, or have > strange requirements for, its interface to the PCI bus? > > Many other PCI designs work on this card, so I cannot fault the card. > The PC, chipset, etc. is of course suspect. > > Any ideas? Does this sound familiar to anyone? Any help is > appreciated. Austin, are you out there? > > Regards, > Tom > > > > --- > Tom Curran > tom_curran@memecdesign_dot_comArticle: 46121
Hi Ray, Hum. I have libraries for everything up to Virtex2...in the [Xilinx installation]\viewlog\data directory. Now, I can't vouch for support from Xilinx or not... That's on a 3. installation... I'll check with my 4. installation upstairs and see if it's installed there.....and...lo and behold...all the way to Virtex 2 PRO!!! So, does that mean it's "supported"? Now, I can't vouch that EVERYTHING is supported, but "some" support seems to be there, at least for the most recent technologies... Are you simply talking about simulation libraries, not just schematic symbol libraries? I haven't tried simulating...but I've simulated Virtex designs so far...never tried V2 or V2P... Regards, Austin "Ray Andraka" <ray@andraka.com> wrote in message news:3D5BB778.FF678341@andraka.com... > Xilinx no longer generates a viewlogic library, no will its > hotline help you out if you have issues with using viewlogic. > You can still generate an edif netlist with viewlogic, but you > will need to do something for the library if you plan to > simulate within viewlogic. Show me where to get a VL library > for the current Xilinx primitives if I am wrong. > > Austin Franklin wrote: > > > > Viewlogic is not really supported by Xilinx anymore... > > > > Hi Ray, > > > > Would you mind clarifying what you mean by "really" please? > > > > Regards, > > > > Austin > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, > 1759 > >Article: 46122
Try setting the TimingChecksOn generic to false. I've had troubles in the
past when that is in the (default) on state interfacing with RTL designs.
Also, you may be bringing the clock high at the same time you are bringing
the WE to inactive at the very beginning of your sim. Try starting with the
clock low.
Patrik Eriksson wrote:
> When I simulates the following code this warning message is displayed at
> time 0ns.
>
> # ** Warning: Invalid ADDRESS: XXXXXXXXXX. Memory contents will be set
> to 'X'.
> # Time: 0 ps Iteration: 3 Instance: /theram
>
> This means that I can't simulate with correct INIT values!!
> All addresses and control signals are constant but the clock inputs are
> toggled.
>
> Have I done anything stupid? Is there an error in the simulation model?
> This code is a debug version of my real design just to track the
> simulation error.
>
> I thought that if WEx is de-asserted nothing should happen to the memory
> contents whatever the other signals looks like.
>
> /Patrik Eriksson
> -----------
>
> library ieee;
> use ieee.std_logic_1164.all;
> use ieee.std_logic_unsigned.all;
>
> -- synthesis translate_off
> library unisim;
> -- synthesis translate_on
>
> entity bram_tb is
>
> end entity bram_tb;
>
> architecture sim of bram_tb is
>
> component BUFG
> port (
> I : in std_logic;
> O : out std_logic);
> end component;
>
> component IBUFGDS_LVPECL_33
> port (
> O : out std_ulogic;
> I : in std_ulogic;
> IB : in std_ulogic);
> end component;
>
> component DCM
> -- synthesis translate_off
> generic (
> DLL_FREQUENCY_MODE : string := "LOW";
> CLKOUT_PHASE_SHIFT : string := "NONE";
> PHASE_SHIFT : integer := 0;
> CLKFX_MULTIPLY : integer := 4;
> CLKDV_DIVIDE : real := 2.0
> );
> -- synthesis translate_on
> port (
> CLKIN : in std_logic;
> CLKFB : in std_logic;
> DSSEN : in std_logic;
> PSINCDEC : in std_logic;
> PSEN : in std_logic;
> PSCLK : in std_logic;
> RST : in std_logic;
> CLK0 : out std_logic;
> CLK90 : out std_logic;
> CLK180 : out std_logic;
> CLK270 : out std_logic;
> CLK2X : out std_logic;
> CLK2X180 : out std_logic;
> CLKDV : out std_logic;
> CLKFX : out std_logic;
> CLKFX180 : out std_logic;
> LOCKED : out std_logic;
> PSDONE : out std_logic;
> STATUS : out std_logic_vector(7 downto 0)
> );
> end component;
>
> component RAMB16_S9_S9
> -- synthesis translate_off
> generic (
> WRITE_MODE_A : string;
> WRITE_MODE_B : string;
> INITP_00, INITP_01, INITP_02, INITP_03,
> INITP_04, INITP_05, INITP_06, INITP_07,
> INIT_00, INIT_01, INIT_02, INIT_03,
> INIT_04, INIT_05, INIT_06, INIT_07,
> INIT_08, INIT_09, INIT_0A, INIT_0B,
> INIT_0C, INIT_0D, INIT_0E, INIT_0F,
> INIT_10, INIT_11, INIT_12, INIT_13,
> INIT_14, INIT_15, INIT_16, INIT_17,
> INIT_18, INIT_19, INIT_1A, INIT_1B,
> INIT_1C, INIT_1D, INIT_1E, INIT_1F,
> INIT_20, INIT_21, INIT_22, INIT_23,
> INIT_24, INIT_25, INIT_26, INIT_27,
> INIT_28, INIT_29, INIT_2A, INIT_2B,
> INIT_2C, INIT_2D, INIT_2E, INIT_2F,
> INIT_30, INIT_31, INIT_32, INIT_33,
> INIT_34, INIT_35, INIT_36, INIT_37,
> INIT_38, INIT_39, INIT_3A, INIT_3B,
> INIT_3C, INIT_3D, INIT_3E, INIT_3F : bit_vector :=
> X"0000000000000000000000000000000000000000000000000000000000000000"
> );
> -- synthesis translate_on
>
> port (
> DIA : in std_logic_vector(7 downto 0);
> DIPA : in std_logic_vector(0 downto 0);
> DIB : in std_logic_vector(7 downto 0);
> DIPB : in std_logic_vector(0 downto 0);
> ENA : in std_ulogic;
> ENB : in std_ulogic;
> WEA : in std_ulogic;
> WEB : in std_ulogic;
> SSRA : in std_ulogic;
> SSRB : in std_ulogic;
> CLKA : in std_ulogic;
> CLKB : in std_ulogic;
> ADDRA : in std_logic_vector(10 downto 0);
> ADDRB : in std_logic_vector(10 downto 0);
> DOA : out std_logic_vector(7 downto 0);
> DOPA : out std_logic_vector(0 downto 0);
> DOB : out std_logic_vector(7 downto 0);
> DOPB : out std_logic_vector(0 downto 0)
> );
>
> end component;
>
> constant INITP : bit_vector :=
> X"1041000100001400010000100040100001400010004100041000100004000104";
> constant INIT : bit_vector :=
> X"1001000100001000010000100000100001000010000100001000100001000100";
>
> signal clk_p, clk_n, clk, rst : std_logic;
> signal clk_ibufg, clk_bufg : std_logic;
>
> begin -- architecture sim
>
> INBUF: IBUFGDS_LVPECL_33
> port map (
> O = clk_ibufg,
> I = clk_p,
> IB = clk_n);
>
> GLOBALBUFFER: BUFG
> port map (
> I = clk_ibufg,
> O = clk_bufg);
>
> clk <= clk_bufg;
>
> THERAM: RAMB16_S9_S9
> generic map (
> WRITE_MODE_A = "WRITE_FIRST",
> WRITE_MODE_B = "READ_FIRST",
> INITP_00 = INITP,
> INITP_01 = INITP,
> INITP_02 = INITP,
> INITP_03 = INITP,
> INITP_04 = INITP,
> INITP_05 = INITP,
> INITP_06 = INITP,
> INITP_07 = INITP,
> INIT_00 = INIT,
> INIT_01 = INIT,
> INIT_02 = INIT,
> INIT_03 = INIT,
> INIT_04 = INIT,
> INIT_05 = INIT,
> INIT_06 = INIT,
> INIT_07 = INIT,
> INIT_08 = INIT,
> INIT_09 = INIT,
> INIT_0A = INIT,
> INIT_0B = INIT,
> INIT_0C = INIT,
> INIT_0D = INIT,
> INIT_0E = INIT,
> INIT_0F = INIT,
> INIT_10 = INIT,
> INIT_11 = INIT,
> INIT_12 = INIT,
> INIT_13 = INIT,
> INIT_14 = INIT,
> INIT_15 = INIT,
> INIT_16 = INIT,
> INIT_17 = INIT,
> INIT_18 = INIT,
> INIT_19 = INIT,
> INIT_1A = INIT,
> INIT_1B = INIT,
> INIT_1C = INIT,
> INIT_1D = INIT,
> INIT_1E = INIT,
> INIT_1F = INIT,
> INIT_20 = INIT,
> INIT_21 = INIT,
> INIT_22 = INIT,
> INIT_23 = INIT,
> INIT_24 = INIT,
> INIT_25 = INIT,
> INIT_26 = INIT,
> INIT_27 = INIT,
> INIT_28 = INIT,
> INIT_29 = INIT,
> INIT_2A = INIT,
> INIT_2B = INIT,
> INIT_2C = INIT,
> INIT_2D = INIT,
> INIT_2E = INIT,
> INIT_2F = INIT,
> INIT_30 = INIT,
> INIT_31 = INIT,
> INIT_32 = INIT,
> INIT_33 = INIT,
> INIT_34 = INIT,
> INIT_35 = INIT,
> INIT_36 = INIT,
> INIT_37 = INIT,
> INIT_38 = INIT,
> INIT_39 = INIT,
> INIT_3A = INIT,
> INIT_3B = INIT,
> INIT_3C = INIT,
> INIT_3D = INIT,
> INIT_3E = INIT,
> INIT_3F = INIT)
> port map (
> DIA = "00000000",
> DIPA = "0",
> DIB = "00000000",
> DIPB = "0",
> ENA = '1',
> ENB = '1',
> WEA = '0',
> WEB = '0',
> SSRA = '0',
> SSRB = '0',
> CLKA = clk_p,
> CLKB = clk,
> ADDRA = "00000000000",
> ADDRB = "00000000000",
> DOA = open,
> DOPA = open,
> DOB = open,
> DOPB = open);
>
> -- CLK process
> process
> begin
> clk_p <= '0';
> clk_n <= '1';
> loop
> wait for (10 ns);
> clk_p <= not clk_p;
> clk_n <= not clk_n;
> end loop;
> end process;
>
> MAIN: process
> begin -- process MAIN
>
> rst <= '1';
> wait for 10 ns;
> rst <= '0';
>
> wait;
>
> end process MAIN;
> end architecture sim;
>
> --
> Patrik Eriksson | patrik.eriksson@netinsight.net
> Net Insight AB | phone: +46 8 685 04 89
> Västberga Allé 9 | fax: +46 8 685 04 20
> SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.net
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46123
It has been a while since I last used viewlogic. I dropped it when I started
using Virtex. At that time, they provided symbols, but there were no simulation
models under the virex specific parts...important things like the carry chain
components, SRL16's and block RAMs. About the same time, Xilinx indicated that
viewlogic was unwilling to do something they needed for the simulation models to
work right, and xilinx didn't see the point in keeping with schematics,
especially a 3rd party vendor. I did see the symbols on the install disk, but
I'd be surprised if there were viewlogic simulation models under all of them. Of
course, you could use the VHDL models, but then you need to edit all the
viewlogic symbols and it also requires you to have their VHDL sim with the
schematic tools. I do know that if you have a viewlogic problem with Xilinx,
you are pretty much on your own.
Austin Franklin wrote:
> Hi Ray,
>
> Hum. I have libraries for everything up to Virtex2...in the [Xilinx
> installation]\viewlog\data directory. Now, I can't vouch for support from
> Xilinx or not... That's on a 3. installation... I'll check with my 4.
> installation upstairs and see if it's installed there.....and...lo and
> behold...all the way to Virtex 2 PRO!!!
>
> So, does that mean it's "supported"? Now, I can't vouch that EVERYTHING is
> supported, but "some" support seems to be there, at least for the most
> recent technologies...
>
> Are you simply talking about simulation libraries, not just schematic symbol
> libraries? I haven't tried simulating...but I've simulated Virtex designs
> so far...never tried V2 or V2P...
>
> Regards,
>
> Austin
>
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3D5BB778.FF678341@andraka.com...
> > Xilinx no longer generates a viewlogic library, no will its
> > hotline help you out if you have issues with using viewlogic.
> > You can still generate an edif netlist with viewlogic, but you
> > will need to do something for the library if you plan to
> > simulate within viewlogic. Show me where to get a VL library
> > for the current Xilinx primitives if I am wrong.
> >
> > Austin Franklin wrote:
> >
> > > > Viewlogic is not really supported by Xilinx anymore...
> > >
> > > Hi Ray,
> > >
> > > Would you mind clarifying what you mean by "really" please?
> > >
> > > Regards,
> > >
> > > Austin
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin,
> > 1759
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46124
Polyphase filtering is basically using parallel filter banks, with only some of
the samples getting processed by each "branch". For example, for a filter with
3 branches, each filter is using every third sample, but the filters are offset
by a sample, essentially using different phases of the signal for each.
Polyphase filtering is used whe you have sample rate changes. an up or down
sample by an integer ratio is the easiest.
In the case of a decimation, you mathematically would do a low pass filter,
followed by discarding the samples between every Nth sample. As it turns out,
there is no need to do the computations for those discarded samples, and that is
what polyphase is all about. If you work the filter backwards eliminating the
dropped samples from the math, you'll see that you wind up with N filter banks,
each of which is fead by a different 'phase' of the input and whose outputs are
summed. Each bank is working at the decimated sample rate instead of the input
sample rate, so while you still have the same number of taps, the computation
rate is lower. Polyphase is not all that useful with high decimation ratios.
Is your average an integrate and dump, or is it a moving average. Both provide
a filter with a frequency response equal to the sunc function (sinx/x), however
the integrate and dump is also decimated at the output by the number of samples
in the average. The moving average is not inherently decimated. Provided this
filter shape is satisfactory, You'd be best off sticking with the average. For
a moving average, or even a decimation by some factor other than N, you can use
a CIC (Hogenaur) filter, which is essentially an integrator, decimation and comb
(difference) filter. It is basically a hardware implementation of a recursive
moving average filter. While the CIC's response is not spectacular, it does
provide an efficient means for filtering with very high decimation ratios, and
unlike the integrate and dump several stages can be cascaded to steepen the
filter response. Normally, this will be used in conjuction with a small FIR
clean-up filter to take out the droop and to put most of the sidelobe energy
into the stopband.
Noddy wrote:
> I'm using FIR filters in Spartan IIs (200) for radio astronomical
> applications. Right now I have two 40 tap LP filters per FPGA (cut-off
> approximately 0.125) running at 32MHz. The input is a 4 bit quadrature
> signal, with post detection integration after the filters of the order of
> 2^14 samples. This long integration is neccessary in order to obtain the
> signal which is about 6 orders of magnitude less than the noise.
>
> Now, my question is this: would there be any advantage in switching to a
> polyphase filtering technique? I don't know much about it...I see it usually
> involves some decimation and interpolation, although I am not keen to start
> throwing away samples as every sample helps to increase the SNR by averaging
> out the noise.
>
> Thanks
>
> Adrian
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
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