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Hi Hristo, Well, It depends on what kind of process. What is it?Article: 46626
Cranking up the clock lets you do the processing in bit or digit serial form, to
process multiple channels with one copy of the hardware, or to reuse parts of the
logic for different pieces of the process algorithm. This can easily get what
would have required an expensive larger device into a low cost (eg. SpartanII)
device, which brings the FPGA based solution into a price range that is palatable
for low cost consumer applications.
hristo wrote:
> in image processing and with color PAL , 33.32 Mhz is enough to do real time,
> with less image size, the sufficient speed is much less
> so why the need for higher speed?
>
> any practical cases
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46627> could someone explain me please what it means from > <<Ports configured as 9, 18, or 36-bits wide have an additional 2048 > bits of parity memory.>> In simple words, it means that instead of having an 8, 16 or 32 bits wide memory, you have an 9, 18, or 36 bits wide memory. For each 8 bits, you get an extra memory bit that you can use as parity or as a data bit. So don't worry about all the fancy words in the description... MartinArticle: 46628
Well, but first of all, what kind of real time process is that?Article: 46629
In article <826a39a7.0209031713.1a5b49e1@posting.google.com>, Andy Glew, Public <andy_glew_public@yahoo.com> wrote: > * Decode CISC instructions and execute directly This would be your classical microcode. > * Decode CISC instructions into simpler instructions > (not necessarily RISC, unless you call an instruction > that is more than 100 bits wide, with more than 2 inputs, > lots of widgets, possibly load-alu, etc., "RISC") Hey, I didn't make up the term "RISC CORE". VLIW and RISC are both approaches to something in between microcode and assembly. One's more horizontal, the other's more vertical, they're both attempts to get to the same place (an ISA that's semantically close to the hardware) from different directions. If it's not user-visible, whether you're using wide or narrow instructions is an implementation detail. > * Decode CISC instructions into simpler instructions > and store them in a decoded instruction cache > ... trace cache > > * Decode CISC instructions into simpler instructions > and perform optimizations on them > ... actually, the "spectrum" forks here, since > you can perform some optimizations on a stream of > instructions without storing them, > although storing the optimized instructions us attractive This is where things like out-of-order execution come in, too, yes no? -- I've seen things you people can't imagine. Chimneysweeps on fire over the roofs of London. I've watched kite-strings glitter in the sun at Hyde Park Gate. All these things will be lost in time, like chalk-paintings in the rain. `-_-' Time for your nap. | Peter da Silva | Har du kramat din varg, idag? 'U`Article: 46630
Xilinx is Carl Carmicheal. We've used the QPRO devices rather extensively.
They have good total dose characteristics, but are still susceptible to SEU, so
you do need to have an SEU mitigation plan in place that includes checking the
configuration. I'm presenting a paper at MAPLD next week regarding a low
complexity way of monitoring the PFGA configuration. You might consider
attending that conference if you can at all swing it, as it is heavy on the SEU
and radiation considerations.
Gaga wrote:
> I am a graduate student at Texas A&M University. We are building a fpga
> based device for space applications. Originally the plan was to use the
> virtex qpro line. But some people we talked to suggested that actel line
> would be better in terms of radiation characteristics and reliability. Does
> any one have any previous experiences with either brands? Or if you are from
> xilinx or actel do you know whom I should contact to acquire further
> information on this matter?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46631
The lines 369 - 370 read
x[6] = r0;
x[7] = r1;
.. but it looks like a simple typo, perhaps they should be
out[6] = r0;
out[7] = r1;
The compiler is complaining that x[6] is of type (unsigned 1) but r0 is of
type (signed 32).
Cheers,
Steffan
> However I now get a new error: 'object cannot be assigned to'. This
> seems to be cropping up everywhere so I guess I'll have to look at the
> code in some depth before I try and find a suitable example. If
> anyone is brave enough to look at the code, I've uploaded it to
>
> http://www.sli-institute.ac.uk/~gk/mdct.hcc
>
> It will also appear at some point on my TWiki page at
>
http://www.sli-institute.ac.uk/project/motorola_projects/twiki/bin/view/H2/W
ebHome
>
> Cheers,
> Gov
Article: 46632
Hi,
Can someone recommend a good xilinx SpartenII based PCI proto board to me?
Ideally it should have DMA engine on board as well.
Thanks,
Hugh
--
Use our news server 'news.foorum.com' from anywhere.
More details at: http://nnrpinfo.go.foorum.com/
Article: 46633Hi, I'm stymied, and I'm hoping some Xilinx guru out there will take pity and show me the way ! Tools: ISE 4.1i, using XST VHDL When I translate my design I get the following message ERROR:NgdBuild:455 - logical net 'N867' has multiple drivers One or more errors were found during NGDBUILD. No NGD file will be written. How do I find N867 ? I can't find a text netlist to view. And without NGD file, I'm unable to get to the FPGA Editor. This is driving me nuts. Thanks for any help !!!!! -rajeev-Article: 46634
Robin KAY <komadori@myrealbox.com> wrote in message news:<3D7609F0.9A7A0E6D@myrealbox.com>... > PALcode (Privileged Architecture Library Code) is library of horizontal microcode routines that abstract the > operating system from specifics of the processor implementation (i.e method for loading TLB entries, etc...). It > has nothing to do with x86 emulation. PALcode isn't microcode. It's ordinary Alpha code, with access to whatever non-architected processor features and state needed to perform the various functions (atomic operations, context management, TLB loads, etc.) needed to run the OS. Other than being non-interruptible, and having access to a privileged set of instructions and facilities (registers, etc.), there's not much special about PALcode.Article: 46635
>There is a parallel 2Kbit memory to the 16Kbit memory that is only >accessible when the port is 8,16 or 36 bits wide (the added memory has >the same number of address bits and an aspect ratio of 1,2 or 4 bits >respectively). This is nominally for parity bits, but is also useful >for working with word widths of slightly greater than the nominal memory >widths. Very handy for things like an End-Of-Packet flag in FIFOs. (Which is just a wider data word if you think of it that way.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 46636
Rajeev, A good place to look is XST log file. XST might have given some warnings on nets with multiple drivers. Also, search on support.xilinx.com for answer records on Ngdbuild multiple driver error messages. ISE 5.1i provides an NGC to EDIF translator to generate a readable netlist file. ISE5.1i also provides a RTL schematic viewer which can be used to track such re-named internal nets. -Vikram Rajeev wrote: > Hi, > > I'm stymied, and I'm hoping some Xilinx guru out there will take > pity and show me the way ! > > Tools: ISE 4.1i, using XST VHDL > When I translate my design I get the following message > > ERROR:NgdBuild:455 - logical net 'N867' has multiple drivers > One or more errors were found during NGDBUILD. No NGD file will be written. > > How do I find N867 ? > > I can't find a text netlist to view. And without NGD file, I'm unable to get > to the FPGA Editor. This is driving me nuts. > > Thanks for any help !!!!! > > -rajeev-Article: 46637
How about Gigabit Ethernet? There's some "need for speed" there. SH7. (There is more to life than video processing, isn't there?) On 4 Sep 2002 10:55:15 -0700, hristostev@yahoo.com (hristo) wrote: >in image processing and with color PAL , 33.32 Mhz is enough to do real time, >with less image size, the sufficient speed is much less >so why the need for higher speed? > >any practical casesArticle: 46638
In article <b0ab35d4.0209040955.7fe9495b@posting.google.com>, hristo <hristostev@yahoo.com> wrote: >in image processing and with color PAL , 33.32 Mhz is enough to do real time, >with less image size, the sufficient speed is much less >so why the need for higher speed? Encryption on the network. There you are talking Gb rates. Encryption on the I/O (disk). Again, Gb+ rates. Gb rate packet processing and analysis. Sequence matching (the faster, the better). -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 46639
Specialized coprocessors for scientific number-crunching. BTW Deep Blue contains a lot of FPGA's. Frank "Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:al62rs$27fg$1@agate.berkeley.edu... > > Sequence matching (the faster, the better).Article: 46640
If I remember correctly the OFFSET parameter (to manage the setup and hold times of input signals) is to be set with respect to an external clock signal comming into the FPGA. Maybe it can be set with respect to a clock signal going out too. I got similar error when I tried to use the parameter with internally generated clock. Brijesh Fabien Arrive wrote: > Xilinx Virtex E - Foundation 4.2 Tools > > I made a block to generate a CLKx2 by using a clk dll. The timing > simulation step is running without any problem. > When I use this block in another design, I got this error message during > the implementation step : > "Signal "CLK" is used as the clock in one or more OFFSET specifications, > but this signal is not connected directly to a pad. An OFFSET > specification must be relative to pad signals." > How to use clk dll to avoid this message ? > > Thank you. > > Fabien > > > >Article: 46641
--------------01B5E42D23BC4DFC2FBFBF63
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
The install replaces a driver with an older version. You need to reinstall the
driver from microsoft after installing the latest webpack. There is an answer
record somewhere on the xilinx website regarding that.
Frank Andreas de Groot wrote:
> (and the latest webpack crashes the Win2000 system boot so I use the
> second-latest),
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46642hristostev@yahoo.com (hristo) wrote in message news:<b0ab35d4.0209040955.7fe9495b@posting.google.com>... > in image processing and with color PAL , 33.32 Mhz is enough to do real time, > with less image size, the sufficient speed is much less > so why the need for higher speed? (Pardon my ignorance, but where does this 33.32 MHz number come from? It doesn't seem to be related to PAL square pixel sample rate, or the 13.5 MHz CCIR 601 sample rate. What is it, and why do you think it is enough?) > > any practical cases Practical cases abound... If processing is going to be involve more than simple color adjustment, or basic (time domain) filtering, typically a DFT is going to be involved. This may arise in image stabilization and pattern recognition, or in removing motion blur. Another application that comes to mind is CT (computed tomography), where a fancy filter (increasing hi-pass), difficult to implement in time domain is used. If you use, say, Xilinx FFT core for this, this means that the 1024 point FFT is used, and because it is a 2-D operation, must be applied twice, both horizontally and vertically. This takes >20us / line-component, using a 100 MHz clock. If all three components are sampled equally (say square pixel sampling rate), it takes slightly more than 60 us to transform them all into the frequency domain, using a single copy of the FFT core. A second core would be needed to get the samples back into spatial form after whatever is done on the frequency side. OK, typically, most algorithms concentrate on luminance component, or only have a luminance component to work with...which case is assumed in rest of discussion... So, with a scan line time of 64 us for PAL video, already 1/3 of that time has been spent getting the image into the frequency domain. Another 1/3 will be spent transforming back, leaving about 20 us per line to do whatever other processing may be going on (actually, no, you still have the whole line time to do additional processing, using other FPGA fabric resource besides the FFT core, the 20us left over is simply idle time for the FFT core, which, to put a good spin on leaving any gate idle, will reduce total power consumption.) At any rate, there is no shortage of clock cycle requirements, even with monochrome video. It isn't even necessary to get into DFT domain... Have a look at what is required for, say, spatially adaptive histogram equalization. Wish I could run these parts near the GHz rates the processor boys get to play with. HTH, hristo JohnArticle: 46643
Quartus II v2.0 AND Quartus II v2.1 were native Linux ports for the RedHat distribution v7.1. Wine is NOT necessary for Quartus II. ModelSim has a native Linux port available, but I don't think the same is true for Leonardo Spectrum. I believe the Xilinx tools are available on Linux at this time only with Wine. -Pete- Prager Roman <rprager@frequentis.com> wrote in message news:al4dt6$ht4$2@frqvie15ux.frequentis.frq... > Xanatos <fpsbb98@yahoo.com> wrote: > > And Works great too.....Good show guys. > I have been using Quartus 2.0 for Linux - but this was only a modified Windows- version using Wine, it > was in no way a native Linux program. Is this the same with Quartus 2.1? > > But I must admitt, I did not test it very long, since I was missing Leonardo and Modelsim under Linux, > and it did not make very much sense to steadily reboot the system just to switch beween the > applications. > > Roman > > -Xanatos > > > > "LET" <vvcd@ath.forthnet.gr> wrote in message > > news:3D51661F.976EDFC6@ath.forthnet.gr... > >> QUARTUS II V2.1 LINUX (C) ALTERA > >> fully functional > >> just arrived > >> > >> > >Article: 46644
Quartus II 2.0 - Linux was released as a full featured, native Linux product. It does not require WINE and runs directly on Red Hat 6.2 or 7.1. Similarly Quartus II 2.1 is also available as a native Linux product (read does not require WINE or any other translation layer) and is fully featured. If a version of Leonardo is not available on Linux, Quartus II 2.1 on all platforms (Windows, Linux, Solaris, HP) has a much improved and very robust HDL (VHDL and Verilog) extractor and synthesizer. ModelTech sells a Modelsim simulator that works on Linux. -ds "Prager Roman" <rprager@frequentis.com> wrote in message news:al4dt6$ht4$2@frqvie15ux.frequentis.frq... > Xanatos <fpsbb98@yahoo.com> wrote: > > And Works great too.....Good show guys. > I have been using Quartus 2.0 for Linux - but this was only a modified Windows- version using Wine, it > was in no way a native Linux program. Is this the same with Quartus 2.1? > > But I must admitt, I did not test it very long, since I was missing Leonardo and Modelsim under Linux, > and it did not make very much sense to steadily reboot the system just to switch beween the > applications. > > Roman > > -Xanatos > > > > "LET" <vvcd@ath.forthnet.gr> wrote in message > > news:3D51661F.976EDFC6@ath.forthnet.gr... > >> QUARTUS II V2.1 LINUX (C) ALTERA > >> fully functional > >> just arrived > >> > >> > >Article: 46645
Pete Ormsby wrote: > > http://www.altera.com/corporate/news_room/releases/corporate/nr-clearlogic.h > tml > > Leon Qin <lyqin@cti.com.cn> wrote in message > news:23c59085.0208210006.3cb6905a@posting.google.com... > > http://www.clear-logic.com/ I guess I never realized that you did not own full rights to the bit stream from your design... amazing. Does Xilinx also have that restriction? If I want to use my bitstream to program an ASIC, am I prohibited? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46646
If you are not looking for a design size reduction or a power reduction, then you don't really have a reason to take the time to implement the polyphase filter. You can keep your current filter and just toss N-1 samples. The purpose of the polyphase filter is to make the computations more efficient at the expense of a more complex design. Also keep in mind that when you low pass filtered the data, you did the same sort of averaging that increases the signal to noise. If you think about how a FIR filter works, you will see that averaging filters are just a "special" case of a FIR filter with the coefficients set to 1.0. When you change the coefficients you don't change the fact that you are averaging samples and gaining SNR. Or you can think of it as removing the higher frequency noise, the effect is the same. Noddy wrote: > > I don't have much time at the moment to start designing, so is there by any > chance a Core generated module from Xilinx which I can drop into my design > which will allow me to provide the multiple sets of filter coefficients? I'm > using Foundation 3.3 > > Thanks > > Adrian > > Ray Andraka <ray@andraka.com> wrote in message > news:3D61AD73.3B9018CE@andraka.com... > > Polyphase filtering is basically using parallel filter banks, with only > some of > > the samples getting processed by each "branch". For example, for a filter > with > > 3 branches, each filter is using every third sample, but the filters are > offset > > by a sample, essentially using different phases of the signal for each. > > Polyphase filtering is used whe you have sample rate changes. an up or > down > > sample by an integer ratio is the easiest. > > > > In the case of a decimation, you mathematically would do a low pass > filter, > > followed by discarding the samples between every Nth sample. As it turns > out, > > there is no need to do the computations for those discarded samples, and > that is > > what polyphase is all about. If you work the filter backwards eliminating > the > > dropped samples from the math, you'll see that you wind up with N filter > banks, > > each of which is fead by a different 'phase' of the input and whose > outputs are > > summed. Each bank is working at the decimated sample rate instead of the > input > > sample rate, so while you still have the same number of taps, the > computation > > rate is lower. Polyphase is not all that useful with high decimation > ratios. > > > > Is your average an integrate and dump, or is it a moving average. Both > provide > > a filter with a frequency response equal to the sunc function (sinx/x), > however > > the integrate and dump is also decimated at the output by the number of > samples > > in the average. The moving average is not inherently decimated. Provided > this > > filter shape is satisfactory, You'd be best off sticking with the > average. For > > a moving average, or even a decimation by some factor other than N, you > can use > > a CIC (Hogenaur) filter, which is essentially an integrator, decimation > and comb > > (difference) filter. It is basically a hardware implementation of a > recursive > > moving average filter. While the CIC's response is not spectacular, it > does > > provide an efficient means for filtering with very high decimation ratios, > and > > unlike the integrate and dump several stages can be cascaded to steepen > the > > filter response. Normally, this will be used in conjuction with a small > FIR > > clean-up filter to take out the droop and to put most of the sidelobe > energy > > into the stopband. > > > > Noddy wrote: > > > > > I'm using FIR filters in Spartan IIs (200) for radio astronomical > > > applications. Right now I have two 40 tap LP filters per FPGA (cut-off > > > approximately 0.125) running at 32MHz. The input is a 4 bit quadrature > > > signal, with post detection integration after the filters of the order > of > > > 2^14 samples. This long integration is neccessary in order to obtain the > > > signal which is about 6 orders of magnitude less than the noise. > > > > > > Now, my question is this: would there be any advantage in switching to a > > > polyphase filtering technique? I don't know much about it...I see it > usually > > > involves some decimation and interpolation, although I am not keen to > start > > > throwing away samples as every sample helps to increase the SNR by > averaging > > > out the noise. > > > > > > Thanks > > > > > > Adrian > > > > -- > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759 > > > > -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46647
Tom Burgess wrote: > > SNR improvement by averaging only works as expected when the samples are > statistically independant. Even for a random input signal, adjacent samples from > the output of a low pass filter at 4X or 8X oversampling rate are not really > independant any more - they have been smooshed together (convolved) by the > weighted averaging going on inside the filter. I hate to nitpic, but allow me to comment on what you said. SNR gain from filtering or averaging comes from the fact that uncorrelated noise increases by less than correlated signal will. With the filter coeficients set to keep the signal gain to 1.0 you will get a reduction in the strength of the noise. This is as true for a low pass filter as it is for an averaging filter. You can't design one that is not also the other. :) > If you can convince yourself that you don't need to calculate the redundant > output samples, a number of options exist which can be implemented using > polyphase techniques: > > 1) Run (most of) the filter at 1/Nth the clock rate - saves power. Running the > downstream signal processing at 1/Nth the rate also saves power. > 2) Use 1/Nth the amount of hardware resources to implement the filter (e.g. > multiplexing the coefficients) and run it at full clock rate - saves hardware > 3) Use the same amount of resources to build a N times better filter (more taps, > wider coefficents). This is all true. I expect that number 3 is what the OP would be looking for, but he was not clear in his problem statement. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46648
rickman wrote:
>
>
> I guess I never realized that you did not own full rights to the bit
> stream from your design... amazing.
>
I see why you are disgusted with the ruling, and while I, too,
don't agree with the ruling, let's say if you were an IP core vendor who
is trying to collect royalty payment for each chip (or board) sold.
If the licensee for some reason stops paying the royalty, wouldn't you
have the right to sue and collect royalty from the licensee because the
licensee's design contains the licenser's IP core?
Also, most IP cores provided by PLD vendors prohibit conversion to an
ASIC, unless the licensee gets a special permission.
> Does Xilinx also have that restriction? If I want to use my bitstream
> to program an ASIC, am I prohibited?
>
> --
>
> Rick "rickman" Collins
>
As far as I know, all PLD vendors have the restriction you are
talking about, and I personally don't know any vendor that directly does
a conversion from Xilinx FPGA bitstream to an ASIC.
However, it should be perfectly legal to create an ASIC from the EDIF
netlists generated by third party synthesis tools. (Synplify,
LeonardoSpectrum, FPGA Compiler II, etc.)
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 46649
Pete Ormsby wrote:
>
> Quartus II v2.0 AND Quartus II v2.1 were native Linux ports for the RedHat
> distribution v7.1. Wine is NOT necessary for Quartus II.
>
> ModelSim has a native Linux port available, but I don't think the same is
> true for Leonardo Spectrum.
>
> I believe the Xilinx tools are available on Linux at this time only with
> Wine.
>
> -Pete-
>
When I see an Altera employee makes a comment about its rival's
product, I just have to ask the intention of doing so, since the
original poster didn't ask anything about Xilinx.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
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