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Look at http://support.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Military+%2 6+Aerospace http://support.xilinx.com/xapp/xapp216.pdf Steve "Masoud Naderi" <naderimisc@yahoo.com> wrote in message news:2ba3bbea.0209080545.464b6185@posting.google.com... > Dear sir, > I study paper abstracts at MAPLD conference, but nothing on > fault-tolerant desing in NORMAL enviroment. can you give me other > online resources? > Best Regards. > Masoud Naderi > > Ray Andraka <ray@andraka.com> wrote in message news:<3D7A8CE7.BAFA7BEB@andraka.com>... > > I highly recommend attending the MAPLD (Military Applications of > > Programmable Logic Devices) conference in Laurel Maryland next week for > > fault tolerance with FPGAs. Probably the first thing you need to do is > > identify what faults are to be detected and what measures are to be > > taken when a fault is detected. There are a number of fault mechanisms > > that need to be considered, and a lot depends on your environment, the > > device and the application. > > > > Masoud Naderi wrote: > > > > > Hi, > > > I am looking for PRACTICAL fault-tolerant fpga design methodes. Can > > > you help me in this regards? > > > I am familiar with traditional fault-tolerant design methodes, but > > > specificly I am looking for fpga fault tolerant design methodes. > > > > > > Best Regards. > > > Masoud Naderi > > > > -- > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759Article: 46776
Hi folks, I am pondering the requirements for a minimalist FPGA-based device: Power supply Clock generator FPGA JTAG header for configuration via Xilinx parellel cable or similar Have I missed anything? Secondly, for the device to do its own FPGA configuration, I would expect to add flash (or serial prom) small CPLD for configuration control Any comments and useful references? Thanks, JohnArticle: 46777
In article <3D7BED91.7FFDD8B8@qut.edu.au>, John Williams <j2.williams@qut.edu.au> wrote: >Hi folks, > >I am pondering the requirements for a minimalist FPGA-based device: > >Power supply Depending on the FPGA and the IO, you may need 2 or even 3 voltages. I remember seeing some cute little switching power supplies which did this. >Clock generator Probably want it socketed, but not necessarily. If soldered on, make it high frequency, its easier to downclock then upclock. >FPGA >JTAG header for configuration via Xilinx parellel cable or similar > >Have I missed anything? Bypass capacitors. Probably a blinkenlight and a reset button, and probably a power button too. You might also want to toss on a small LCD display, they are cheap and only need a few pins, but can convey a lot of information that way. Also, an FPGA which can't talk to anything is pretty useless. I'd say include a high density connector to a daughtercard which you can put whatever sorts of IOs you want. >Secondly, for the device to do its own FPGA configuration, I would >expect to add > >flash (or serial prom) >small CPLD for configuration control Xilinx makes an ASIC to do this (SystemACE), you can hook it up to a compact flash part. IF you use flash, use compact flash, having removability and program-anywhere is nice. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 46778
Triple mode redundancy (TMR), which you are calling majority method, is considered one of the most robust methods. It
is used in FPGAs in critical applications, and in fact Actel sells a device with TMR built in and others have
libraries that automatically insert TMR at each register. As you noted, it is expensive and still does not always
provide 100% coverage. TMR is pretty much considered the gold standard for fault detection. Most of the other
methods are compromises to reduce the cost while hopefully maintaining a reasonable probability of detection and a
reasonable false alarm rate. This is not at all unique to FPGAs, and has been dealt with in the literature
extensively. What is unique to FPGAs is that you also have configuration circuits that may be susceptible in certain
environments. The configuration circuits are generally not protected by fault logic at all, so you will need to
monitor the health of FPGA configuration through some other means. Our paper, which we are presenting on Tuesday,
addresses this in particular.
It all comes down to probabilities of failure and your tolerance to a failure. Given enough time, any system will
fail. Fault tolerance simply seeks to reduce the incidence of failure within a specified period of time to a level
that is acceptable in terms of cost of implementation vs cost of failure. In order to define what is appropriate, you
first have to define your tolerance to failure, identify the failure modes that are likely to exceed your tolerance
level, then address those particular failure modes with appropriate designed in fault tolerance. SOmewhere along the
line you need to evaluate the cost of that fault tolerance to decide whether or not you can afford it.
Masoud Naderi wrote:
> Dear sir,
> Majority method is of use when "majority unit" is HIGH reliable and
> roboust to faults that make other system parts faulty, But this
> assumption is not correct in FPGAs.Suppose majority unit fails, what
> happen? By the way this method has very high overhead that is not so
> good in FPGAs. Do you know other method?
> Best Regards
> Masoud Naderi
>
> "Frank Andreas de Groot" <nospam@nospam.com> wrote in message news:<gtwe9.15246$0p1.256900@news2.ulv.nextra.no>...
> > (As a newbie) I would say, The easiest approach would be 3 or more identical
> > designs in one FPGA,
> > of which the outputs converge, and every output signal should go through a
> > circuit on that same FPGA that outputs the 'majority' output level. This is
> > very easy to accomplish and thus, every circuit can have 1 different
> > subsystem failing without loss of function.
> >
> > Important aironautical systems are similarly designed. They are in triple or
> > more, in separate hardware designed and manufactured by separate companies.
> > The same goes for the software.
> >
> > But there are different approaches to this. When you want to have a
> > gamma-radiation tolerant design for example, you need a different kind of
> > redundancy, I guess, more like a brain, massively redundant. (I am speaking
> > for my own brain ;o)
> >
> > Frank
> >
> >
> > "Ray Andraka" <ray@andraka.com> wrote in message
> > news:3D7A8CE7.BAFA7BEB@andraka.com...
> > > There are a number of fault mechanisms
> > > that need to be considered, and a lot depends on your environment, the
> > > device and the application.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46779
Google returns a plethora of information if you type in "fault tolerant design
techniques". I suggest you start there. As I indicated in my last post, this is not
unique to FPGAs and the techniques used in other logic design apply just as well to
FPGAs. WHat makes FPGAs unique in terms of fault tolerance is that they are a circuit on
top of a circuit, and the underlying circuit is generally not fault tolerant, so you need
to be clever about detecting faults in the underlying logic
MAPLD is arguably the best source for obtaining information about fault tolerant design in
FPGAs. There are no other single sources of information on that subject specific to FPGAs
that even come close in terms of content or quality. Granted, the environment is probably
more severe than what you are likely to encounter at ground level, but the effects and the
mitigation techniques are still the same.
Masoud Naderi wrote:
> Dear sir,
> I study paper abstracts at MAPLD conference, but nothing on
> fault-tolerant desing in NORMAL enviroment. can you give me other
> online resources?
> Best Regards.
> Masoud Naderi
>
> Ray Andraka <ray@andraka.com> wrote in message news:<3D7A8CE7.BAFA7BEB@andraka.com>...
> > I highly recommend attending the MAPLD (Military Applications of
> > Programmable Logic Devices) conference in Laurel Maryland next week for
> > fault tolerance with FPGAs. Probably the first thing you need to do is
> > identify what faults are to be detected and what measures are to be
> > taken when a fault is detected. There are a number of fault mechanisms
> > that need to be considered, and a lot depends on your environment, the
> > device and the application.
> >
> > Masoud Naderi wrote:
> >
> > > Hi,
> > > I am looking for PRACTICAL fault-tolerant fpga design methodes. Can
> > > you help me in this regards?
> > > I am familiar with traditional fault-tolerant design methodes, but
> > > specificly I am looking for fpga fault tolerant design methodes.
> > >
> > > Best Regards.
> > > Masoud Naderi
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46780Quartus II can be used in two ways: For those who are learning how to use FPGA's and would like a quick start, the integrated GUI is the easiest way to learn about the capabilities of the tool. It has wizards to make it easy to create projects, make device, pin and timing constraints, and control the Compiler engine which does extraction, synthesis, place and route, timing analysis, simulation netlist writing, and assembling (generating the bitstream for the programmer). The GUI has an integrated IDE that allows one to locate errors discovered during netlist extraction, synthesis, place and route, back into the design source files by simple clicking on the error messages. The GUI is very useful in analyzing timing analysis results, and locating the results back into a interactive floorplanner for further improvement. If you prefer the command line, and prefer a text file that will contain constraints and commands for your project, the Quartus II executables support procedural scripting using Tcl. The API's supported are documented. If you have a project setup you can use the "Generate Tcl file for Project" command from the UI to create this text file for you. Application note http://www.altera.com/literature/an/an195.pdf describes how the Tcl API's can be used. The design formats supported are standard VHDL and Verilog, EDIF's with standard gates along with a library mapping file, atom netlists written out by synthesis tools from EDA vendors, the builtin Quartus II schematic editor designs files (bdf's) and Altera's own AHDL format. Design constraints are stored in text files. Quartus II has a mode called Smart Compilation which does makefile type operations do decide which parts of the Compiler need to be rerun, when changes are made. - DS "Hal Murray" <hmurray@suespammers.org> wrote in message news:unj75agot63e21@corp.supernews.com... > >In my original post, I said a full working flow for Linux was available from > >Altera using the Quartus II 2.1 Linux Solution, using native synthesis. I > >specifically said Quartus II 2.1 and not Quartus II 2.0, because I > >understand the need for a good HDL (VHDL, Verilog) synthesis and simulation > >solution from Altera or any other EDA vendor is needed to adopt the Linux > >platform for serious day to day work. Altera has made significant > >improvements to their HDL language processing capabilities in Quartus II > >2.1, which makes this flow viable. ... > > I'm not familiar with the Altera tools. > > Is a GUI mentality required, or are they friendly to make files? > > Are the intermediate file formates documented? Is it possible > to write supplimental tools/hacks and merge them into the flow? > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. >Article: 46781
"BasePointer" <mfide@softhome.net> wrote in message news:ee78d89.-1@WebX.sUN8CHnE... > Hi, > I look for Orcad 9.2 Capture(Schematic) Library for XCS10XL-PC84(SpartanXL) and XC18V256PC20 PROM. > > Thanks I've said this before, and it isn't meant insultingly at all...but WHY is it OrCAD users are the ones who are the only ones who ask for symbols? I've never seen a ViewDraw user, or any other schematic capture package user ask in this group for symbols. S'up wit dat? Most everyone, other than apparently OrCAD users, simply make the symbols. AustinArticle: 46782
Peter Alfke wrote:
>
> We finally got around to measuring metastabity.
> We used the CLB flip-flops in our newest Virtex-IIPro device (130 nm
> technolgy, 1.5 Vcc) and clocked them at around 350 MHz with an
> asynchronous input of roughly 50 MHz. This should represent agressive
> modern operating conditions.
> We then measured the number of metastable events per minute as a
> function of the time between clocking the flip-flop under test, and a
> variable clock delay at the observation flip-flop that checks for
> metastable events. This method is described in detail in XAPP094, and I
> first used and documented it in 1988 (!). The concept seems to have
> passed the test of time.
>
> Here are the measured results:
> Metastable events for a clock-to-clock delay of
> 1300 ps: ~ 30,000 errors per minute
> 1400 ps: ~ 2,000 errors per minute
> 1500 ps: ~ 100 errors per minute
> 1600 ps: = 10 errors per minute
Very interesting.
This shows the 'finite lifetime' nature, and agressive settling slope.
> These are short-time measurements of a statistical event, but I am
> willing to estimate that the time between metastable events increases by
> a factor of roughly 200 for every 200 picoseconds of extra delay between
> the two clocks.
But is that safe ?
What about numbers < 1300ps,
( Interesting for completeness, and for curve-fitting )
and > 1600ps
- ie a run for a day should confirm at least the 1800ps lifetime,
(predicted at 20mins/event), and a run for a fortnight should get
info on the 2000ps lifetime.
( instead of furlongs/fortnight, you would specify
MetaEvents/2000ps lifetime/fortnight ;)
How about testing this as well :
Check the lifetime curve for double edged syncroniser:
+---------+----------< CLK
| +---+ | +---+
+-|> | +-o|> |
| | | |
----|D Q|------|D Q|--- Qo
| | | |
+---+ +---+
-jg
Article: 46783Peter Alfke wrote: > <snip> > If you lower the clock frequency to 250 MHz, you gain more than 1 ns > in clock period, which means five multiplications by 200. That makes > the MTBF 320 billion times larger, i.e. roughly 4 billion billion > years ( 4 exp18 ). > That is roughly 200 million times the highest estimate for the life of > the Universe (20 billion years) or about a billion times the age of > our dear old planet (4 billion years). > > Most people would call that a very low probability. Brave souls might > even dare to call it zero. What would happen if you considered the electrons involved as quantized charges - would there not be a limit, beyond which you cannot 'balance' the register any more, and so cannot extend the lifetime any further ? Knowing the nQ/fQ in the gates, should give an electron count ? -jgArticle: 46784
Hi, I have a specific query regarding the fixed point conversion routines in SystemC. I have observed that while using the SC_TRN (trruncation mode) of quantization, there is an anamoly that I am unable to figure out. Say we have a variable "x" quantized with "wl" bits and "iwl" integer bits. In the SC_TRN mode, all values of x in the range [-1/2^(wl-iwl),0] get quantized to 0. However, I expect the quantization to be towards -1/2^(wl-iwl) as SC_TRN represents the round towards minus infinity mode. why is this discrepency occuring? Can anyone please advice. Thanks Vikram Vikram Chandrasekhar Graduate Student Electrical and Computer Engg. Rice University Ph:(713)529 9819 (R) (713)348 2897 (O) www.ece.rice.edu/~cvikram/index.htmlArticle: 46785
John Williams wrote: > Secondly, for the device to do its own FPGA configuration, I would > expect to add > > flash (or serial prom) > small CPLD for configuration control > > You do not need any CPLD. The FPGA is "smart enough" to pull its configuration out of a serial PROM. ( using CCLK ) Peter Alfke, Xilinx ApplicationsArticle: 46786
Jim Granville wrote: > > > What about numbers < 1300ps, > ( Interesting for completeness, and for curve-fitting ) > > and > 1600ps > - ie a run for a day should confirm at least the 1800ps lifetime, > Will do. We have had only 3 days at this. And they seem to have been fruitful. :-) > How about testing this as well : > Check the lifetime curve for double edged syncroniser: > > +---------+----------< CLK > | +---+ | +---+ > +-|> | +-o|> | > | | | | > ----|D Q|------|D Q|--- Qo > | | | | > +---+ +---+ If I can decypher your drawing, thta's exactly what we use for measuring. Look at XAPP094... BTW, the billions of years were somwhat tongue-in-cheek. But that's what you get with exponential functions...If there is no better explanation, I take math anytime. Peter AlfkeArticle: 46788
Hi I am interfacing a xilinx virtex with DSP over a tristatable bus. InPAR simulation the data bus goes to the final value after propagating over few X for small time(10 ns). There is no bus conflict also. The sample code is as follows if enable bus<=mem(conv_int(address_input)); else bus Z what could be the source of problem and will it cause problem in h/w.Article: 46789
Peter Alfke wrote:
>
> Jim Granville wrote:
> > How about testing this as well :
> > Check the lifetime curve for double edged syncroniser:
> >
> > +---------+----------< CLK
> > | +---+ | +---+
> > +-|> | +-o|> |
> > | | | |
> > ----|D Q|------|D Q|--- Qo
> > | | | |
> > +---+ +---+
>
> If I can decypher your drawing, thta's exactly what we use for measuring.
> Look at XAPP094...
I meant this as a alternative for the first, single D register - ie the
clock domain syncroniser - wondering if there was benefit in two
registers,
over one with a longer delay.
I have also seen this topology, would be interesting to
compare this too :
+---------+----------< CLK
| +---+ | +---+
+-|LE | +--|> |
| | | |
----|L Q|------|D Q|--- Qo
| | | |
+---+ +---+
here, the pre-latch trys to avoid D change within Tsu, so avoiding the
metastable-lifetime trigger aperture.( Of course, L-Q can go metastable
)
Since you test using both clock edges, these might be a challenge
to link to your test circuit.
I think your test tabulates lifetime errors, but does not distinguish
between
a (rare) runt pulse, and a (more common) 'delayed decision'
- ie where the OP went one way, then changed its mind, and went the
other.
Does this _ever_ occur ?
Would just need more result capture logic, to count pulses << Lower
Freq PW. :)
That could be important in some systems, as you could get a single
SyncCLK
width pulse launched into a downstream state engine, which it was never
designed/tested for...
-jg
Article: 46790naderimisc@yahoo.com (Masoud Naderi) wrote: > I am familiar with traditional fault-tolerant design methodes, but > specificly I am looking for fpga fault tolerant design methodes. Hi, First you should be more precice acording to: 1. What FPGA? Ram-based fpga face other problems and allow other solutions than fuse based. 2. Tolerant against what failure? If you choose high-rel Actel fpga which are fuse based instead of Ram based you could use all normal methods. Actel provides an app-note for some important points. If you choose Ram based fpgas you should be more clear what failures could happen? I would implement a function for error detection that reloads the fpga in case of error, because you could have big trouble when your cirquit changes its function. But its also possible to implement a self-restoring cirquit on chip. BTW: I good majority funcion for one bit consists of a 4:1 multiplexer. I would expect that to bee a very stable solution. And in fact TMR with a robust design is all you need for space application, which are critical to radiation events. bye ThomasArticle: 46791
Hi, Sorry, been at conference and so haven't been able to respond. > This is all true. I expect that number 3 is what the OP would be > looking for, but he was not clear in his problem statement. Ok, this is my problem. I am building a filterbank receiver (to be precise, its a pulsar timer, but that is irrelevant) for a radio astronomy observatory. Hence, at the moment the design wil just quite a few boards with FPGAs on, each with a complex low pass filter (I am using quadrature signals). All have the same characteristics, and I do some digital complex mixing prior to the filters to shift the signals about DC. What I was thinking of doing was, since the filters have a cutoff of 0.125, I could move all the filtering onto a single FPGA by implementing a polyphase filter with N=8, followed by FFT etc. etc. What do you think? AdrianArticle: 46792
Peter Alfke <palfke@earthlink.net> wrote: >> Secondly, for the device to do its own FPGA configuration, I would >> expect to add >> flash (or serial prom) >> small CPLD for configuration control >You do not need any CPLD. The FPGA is "smart enough" to pull its >configuration out of a serial PROM. ( using CCLK ) >Peter Alfke, Xilinx Applications Given an FPGA with serial PROM connected to the configuration pins do the Xilinx tools and download cables support in circuit programming of the PROM through the FPGA JTAG port?Article: 46793
I've got a counter (down count to zero then stops) which I can implement OK in the lpm_counter megafunction except that I want both a registered and unregistered version of the cout pin. e.g. an 8 bit counter with data input, sload, clk, clk_enable and cnt_enable with q[] unused but cout used to mark the zero count. The counter mode block diagram of the Apex20KE LE appears to allow this. The registered version drives local logic to control whether the counter free-runs or stops when its counted down to zero, the unregistered cout does get registered but only at a pre-existing register as its fed into a ROM implementation in an ESB of my APEX20ke. Because all my other input addresses in the ROM are registered, I can do one of two things: 1) Try and get an unregistered cout which can then be registered at the ESB. 2) Make the ESB unregistered and separately register all other inputs to the ESB. I can't afford an additional register delay on the 'cout' input to my ROM as the ROM is part of a state machine which can't accept the additional latency. I originally tried a hand written counter but couldn't persuade Leonardo to use the carry chain for the calculation of when the count is about to be zero. [ The lpm original for an 8 bit count uses 9 LE's, my Leonardo attempt with same functionality uses 26 LE's) Any help in massaging the tools to do the right thing is appreciated. PS I did look at the Altera alt_synch_counter.tdf file for the optimised code, but it seems to be operating on a level that manipulates the LCELL configuration directly using hex values. Not something I'd like to mess with :) PaulArticle: 46794
"Tony Burch" <tony@burched.com.au> wrote in message news:<3d7c1560$0$28864$afc38c87@news.optusnet.com.au>... > Hi John, > > What you have just described is essentially > the BurchED board... > http://www.burched.com.au/B5Spartan2.html > > Our philosophy has always been to provide > users with the "minimalist" flexible system, which > gives access to ALL of the user I/Os, and > allows it to be used as a base platform for > prototyping a new system, or building into > equipment (one-offs, or OEM). > > The B5-Spartan2e+ has > * Spartan2E 300K gate XC2S300E device > * JTAG and serial mode configuration download pod cable > * Header programmable PLL oscillator (1 - 100MHz) > * All the cables and hardware you need for a basic FPGA system > > Oh, yes, and you also get one test pushbutton > switch (which I almost always use for the > system Rst), and one test LED. > > The B5-Spartan2e+ board is US$179. > > We also supply plug-on modules, for easily > expanding system resources. In eight days time, > we are releasing a flash prom configuration module, > which plugs onto the B5-Spartan2e+. > > Hope that is of interest, > > Best regards > Tony Burch > http://www.BurchED.com > Low cost FPGA boards, for System-On-Chip > prototyping and education > > "John Williams" <j2.williams@qut.edu.au> wrote in message > news:3D7BED91.7FFDD8B8@qut.edu.au... > > Hi folks, > > > > I am pondering the requirements for a minimalist FPGA-based device: > > > > Power supply > > Clock generator > > FPGA > > JTAG header for configuration via Xilinx parellel cable or similar > > > > Have I missed anything? > > > > Secondly, for the device to do its own FPGA configuration, I would > > expect to add > > > > flash (or serial prom) > > small CPLD for configuration control > > > > > > Any comments and useful references? > > > > Thanks, > > > > John The Musketeer (all-for-one) FPGA stamp, is actually both a minimalist and maximalist FPGA development platform, especially for FPGA-embeddable microcontrollers. For about $175 you get everything. JTAG real-time debugger, JTAG boundary scan controller, device programmer. No need for serial FLASH because the Musketeer's on board FPGA is an Actel ProASIC+, re-programmable FPGA with ASIC-like features. There is a product brief and news release you can download at: www.quickcores.com. There are also some ready-made microcontroller designs (STAPL format) that you can download. Regards JerryArticle: 46795
I heard that FPGA cannot implements ADC (PCM)? Is that true?Article: 46796
Dear Gurus, I need to evaluate if a FFT of 16k, 12 bit real points, can be performed on a XC2V1000-4 Xilinx FPGA, just using one board or more connected among them. What are the basic parameters to look for? (I would like to avoid to perform most of the place and route optimisation). Is there exist a ready to use IP from Xilinx to perform this large FFT? I am a bit confused about the benchmark on VirtexII performance on 1024, 16 bit, complex points: less than 1 us!! (on the top FPGA of the Virtex II family). Is there a rule of thumb to scale this benchmark to lower cell count FPGA? I would really appreciate any informations that will show me the light. Thank You very much Yours Sincerely GiovanniArticle: 46797
On 9 Sep 2002 07:41:15 -0700, chankc <chankwanchien@yahoo.com> wrote:
>I heard that FPGA cannot implements ADC (PCM)? Is that true?
Read XAPP155 and decide for yourself.
http://www.xilinx.com/xapp/xapp155.pdf
- Larry
Article: 46798Falk Brunner wrote: > > "rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag > news:3D78D726.A3FA9369@yahoo.com... > > I have received an email reply from Xilinx which says that the XCR3384XL > > device is significantly more expensive to make than the XCR3256XL and so > > there are no plans to significantly reduce the price. > > Hmm, looks like a yield problem. So you will end up by using two 256er > devices, wont you? No, it is more of an issue of which chip will be the standard one vs. the high/low price option. Looks pretty clear that the 256XL will be the standard chip and the 384XL will be the HIGH price option on this board. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46799
We use it this way all of the time. Austin chankc wrote: > I heard that FPGA cannot implements ADC (PCM)? Is that true?
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