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Are all Xilinx CoolRunners XPLA3's, Xilinx CoolRunner-II's, and Atmel ATF15xx's flash-based (ie. do they save their configuration upon power down)? From what I understand, most CPLD's are non-volatile, including the CoolRunners, yet I heard something about the larger CoolRunners being different somehow with respect to this. As far as the Atmel ATF15xx series, I haven't heard anything about this. Thanks in advance for any help!Article: 46826
"Nicholas C. Weaver" wrote: > > Depending on the FPGA and the IO, you may need 2 or even 3 voltages. > I remember seeing some cute little switching power supplies which did > this. Any useful links? I'm targetting very low power consumption (who isn't?!), so the provision of several voltages is potentially problematic. Certainly don't want the heating/resistive losses associated with voltage regulators, so maybe miniature switched mode might be the way to go. > >Clock generator > > Probably want it socketed, but not necessarily. If soldered on, make > it high frequency, its easier to downclock then upclock. I haven't played with Xilinx clock management yet, DCM and all that. But if I have a fixed external clock, say 133MHz, can I expect to achieve reasonable application sdpecific clock frequencies within the device? ie 133MHz coming in, down-clock that to 100, or 66, or 50, or whatever? Obviously integer clock division is trivial, but what about non-integer? Also, can I get the FPGA to down-clock, and also export that reduced clock to external circuitry? > >Have I missed anything? > > Bypass capacitors. Probably a blinkenlight and a reset button, and > probably a power button too. Yep, good call, especially for prototyping. "Is it working? Yes, I've got a 2 HZ blinking light, just like I expected!" > You might also want to toss on a small > LCD display, they are cheap and only need a few pins, but can convey a > lot of information that way. Hmm interesting idea, once again could be very useful for prototyping. > Also, an FPGA which can't talk to anything is pretty useless. I'd say > include a high density connector to a daughtercard which you can put > whatever sorts of IOs you want. Yup. > Xilinx makes an ASIC to do this (SystemACE), you can hook it up to a > compact flash part. IF you use flash, use compact flash, having > removability and program-anywhere is nice. I read the system ACE doco - very interesting stuff. Thanks for your reply. JohnArticle: 46827
Tom Shanley describes it nicely in his PCI System Architecture book. Basically the driver drives to half the voltage level and lets the reflection build the voltage to the spec level. For the clamping diodes, they seem mainly important for conditioning the inputs in the case of voltage overswing or underswing that would damage the buffer due to the unknowns of other PCI bus devices. The clamp to 5V will short to about 5.7V before driving >5.7V into the buffer. Similarly for the ground diode. This gets important if your silicon is 2.5V or lower and you want to be sure your chip works on 5V PCI spec, so your chip spec should indicate what voltage swings are allowed. Hope this helps. -Steen v_ralev@yahoo.com (Vladimir Ralev) wrote in message news:<8a1f1cd8.0209070521.369ba287@posting.google.com>... > Hi all, i have few questions about the pci bus, no good answers in the > specs and i hope you have some extra info.. > > Could any1 explain me how exactly the pci bus handles the relected > signals of the non-terminated lines? > > I can't understand what all that diode clamps stand for. A document > for example says "clamp diodes protect inputs from momentary short > circuit current caused by tri-stating delays". What about that > tri-stating delay, i mean how could a signal delay cause a short > circuit? > > example: i have schematics of a clamped input, a clamp to the 5V rail > (from input to the rail diode orientation) and a clamp to ground (from > GND to input diode orientation), bth diodes meet at a certain "vertex" > and appear to be in paralell with respect to the power rails. How des > this prevent a short? Are the clamp diodes some kind of special > diodes? Can u tell me a brand name & model for diodes that would work > as clamps(in 5V signalling environment)? > > Thanks for your time!Article: 46828
In article <3D7D2D90.E14FFF66@qut.edu.au>, John Williams <j2.williams@qut.edu.au> wrote: >> Depending on the FPGA and the IO, you may need 2 or even 3 voltages. >> I remember seeing some cute little switching power supplies which did >> this. > >Any useful links? I'm targetting very low power consumption (who >isn't?!), so the provision of several voltages is potentially >problematic. Certainly don't want the heating/resistive losses >associated with voltage regulators, so maybe miniature switched mode >might be the way to go. I remember seeing ones from Lucent a couple years ago, but can't find a reference. Some companies make small ones that BGA mount for cellphone applications (4-6V input, 1.5V output or similar), but the current was only 1/2 an amp (so under a watt, you probably want to be ABLE to draw a few watts), that google was able to find. http://www.vishay.com/document/10106/10106.pdf has ones that are 1.5W max power, 85-90% efficient, 3.6 to 6V input, 1.5 to 3.6V output (settable by a resister). I don't know if these in particular can be run in parallel, but the lucent ones could. >I haven't played with Xilinx clock management yet, DCM and all that. >But if I have a fixed external clock, say 133MHz, can I expect to >achieve reasonable application sdpecific clock frequencies within the >device? ie 133MHz coming in, down-clock that to 100, or 66, or 50, or >whatever? Obviously integer clock division is trivial, but what about >non-integer? Integer power of two is easy. Integer any power is easy if you don't mind a 50/50 duty cycle. You could feed it back through the DLL to give you back a 50/50 duty cycle IIRC. >Also, can I get the FPGA to down-clock, and also export that reduced >clock to external circuitry? No problem. And you can PLL it so it is the same phase as the internal one, at least on the virtex families, IIRC. >> Bypass capacitors. Probably a blinkenlight and a reset button, and >> probably a power button too. > >Yep, good call, especially for prototyping. "Is it working? Yes, I've >got a 2 HZ blinking light, just like I expected!" You probably want a hard reset, a "soft" reset (a signal pin), and 2 blinkenlights. You can just use surface mount LEDs and switches. >> You might also want to toss on a small >> LCD display, they are cheap and only need a few pins, but can convey a >> lot of information that way. > >Hmm interesting idea, once again could be very useful for prototyping. Probably overall, they ARE cheap. And it is amazing teh amount of information you can convey for debugging purposes. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 46829
Hi John, All CoolRunner XPLA3 and CoolRunner-II devices are non-volatile. They are EE based, not flash based.. There was a CoolRunner family (XPLA2) that was SRAM based (volatile). That family went up to 960 macrocells and was originally sold by Philips. The XPLA2 family is no longer being sold by Xilinx. This is most likely the larger CoolRunner that you are referring to. Hope that helps, Mark John wrote: > Are all Xilinx CoolRunners XPLA3's, Xilinx CoolRunner-II's, and Atmel > ATF15xx's flash-based (ie. do they save their configuration upon power > down)? > From what I understand, most CPLD's are non-volatile, including the > CoolRunners, yet I heard something about the larger CoolRunners being > different somehow with respect to this. As far as the Atmel ATF15xx > series, I haven't heard anything about this. Thanks in advance for any > help!Article: 46830
John wrote: > > Are all Xilinx CoolRunners XPLA3's, Xilinx CoolRunner-II's, and Atmel > ATF15xx's flash-based (ie. do they save their configuration upon power > down)? > From what I understand, most CPLD's are non-volatile, including the > CoolRunners, yet I heard something about the larger CoolRunners being > different somehow with respect to this. As far as the Atmel ATF15xx > series, I haven't heard anything about this. Thanks in advance for any > help! Philips did have a SRAM Coolrunner, now defunct. Atmel PLDs are all FLASH/EE based. Cypress have some large SRAM/Loader based CPLDs Xilinx say this about XC2 : > To those ends, the general behavior is summarized as follows: > 1. I/O pins are disabled until the end of power-up. > 2. As supply rises, configuration bits transfer from > nonvolatile memory to SRAM cells. > 3. As power up completes, the outputs become as > configured (input, output, or I/O). > 4. The process takes less than 25 ms and draws less than > 5 mA of current. but an Icc/Vcc(rise) and Icc/Vcc(fall) curve set is missing. -jgArticle: 46831
Hi, I am looking for an FPGA chip which has a built-in DAC. My intend it to build a portable with three chips only, A compact-flash, an FPGA containing the MP3 decoder and Compact flash and USB interface, a power amplifier. Is it possible? What's the SIMPLEST approach possible to make a portable MP3 player in today's technology? Kelvin.Article: 46832
Uwe Bonnes wrote: > > rickman <spamgoeshere4@yahoo.com> wrote: > ... > : Can you help me out a little? I don't see a clear selection guide and I > : am working over a very low speed data link today. Can you find the > : parts that meet my criteria? I had pretty well settled on the > : XCR3256XL, but if you have something cheaper, I would love to hear about > : it. > > : Requirements: > > : small package such as 256 fine pitch BGA (17 mm sq) > :>=256 macrocells > :>160 IOs > : very low idle current > : low operating current > : 3.3 volt Vcc > : JTAG boundary scan > : JTAG programming > : onchip memory for FIFOs would be useful, but not required > : memory will allow fewer macrocells >140 > > Coolrunner II may be an alternative, also it seems no general available > yet... > > Bye > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Thanks for the reply, but Coolrunner II is not a 3.3 volt device. I believe it is either 2.5 or 1.8 volt core. This chip must run from only 3.3 volts and be 5 volt compatible, so using a small LDO is not of use here. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46833
Jim Granville wrote: > > rickman wrote: > > > > I am not clear on what you are saying. Based on the number of cells in > > these chips, the area should be 50% larger. So you will get about 1/3 > > less die and you will have 50% more area to see defects in. The price > > of the 384XL is 3:1 over the 256XL price. Because of the lower number > > of 384XL die on the wafer, multiply the price of the 256XL by 3/2, now > > the ratio is 2:1. > > > > I think if you do the math, you will see that a 50% increase in chip > > area does not make a 50% reduction in yield unless your yield is already > > pretty low. > > For reference points, here is info from Lattice Web : > > # Pricing for the ispXPLD5512MC in volumes of >1000 pieces > # starts at $17.75 > > # For high-volume applications, the ispMACH 4512C will be > # priced below $15.00. > > # Projected pricing for the ispMACH5768VG is as low as > # $33.00 in high-volume for the second half of 2002 > > Seems they also have a steepening of the price curve, but at 512->768, > not 256->384. I see what you are saying, but 2:1 is not abnormal, 4:1 is. Peter is good at waving his hands, but to justify a 4:1 price increase by anything other than marketing pressures, he would have to show some unusual data on the chip size change due to extra routing. His other items don't hold water (at least not a lot). Not trying to be argumentative, just stating the facts as I see them. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46834
Peter Alfke <peter@xilinx.com> wrote: > > >nospam wrote: > >> >> I think I would keep the clock generators physically separate with the >> device under test in the middle that way the device gets to see both clocks >> before the generators get to see each other. > >Sure, done that. >Remember, I have been at this, on and off, for 14 years... So I didn't do so bad for 10 minutes of thought then :)Article: 46835
rickman wrote: > > Uwe Bonnes wrote: > > > > rickman <spamgoeshere4@yahoo.com> wrote: > > ... > > : Can you help me out a little? I don't see a clear selection guide and I > > : am working over a very low speed data link today. Can you find the > > : parts that meet my criteria? I had pretty well settled on the > > : XCR3256XL, but if you have something cheaper, I would love to hear about > > : it. > > > > : Requirements: > > > > : small package such as 256 fine pitch BGA (17 mm sq) > > :>=256 macrocells > > :>160 IOs > > : very low idle current > > : low operating current > > : 3.3 volt Vcc > > : JTAG boundary scan > > : JTAG programming > > : onchip memory for FIFOs would be useful, but not required > > : memory will allow fewer macrocells >140 > > > > Coolrunner II may be an alternative, also it seems no general available > > yet... > > > > Bye > > -- > > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Thanks for the reply, but Coolrunner II is not a 3.3 volt device. I > believe it is either 2.5 or 1.8 volt core. This chip must run from only > 3.3 volts and be 5 volt compatible, so using a small LDO is not of use > here. XC2 is 3.3V capable, with a 1.8V core -> but you have added 5V compatible. These days, that's quite an issue: The newer, larger, CPLDs are all shrink devices that CANNOT tolerate 5V, so you are hooking to a trailing technology device. I'd choose carefully, and get a lifetime assurance ( FWIW ) Can this app use a small FPGA ? -jgArticle: 46836
Since you recognize the need for a power amplifier, look into Class-D amplifiers. While the one device I glanced at from TI has an analog input and an internal ramp generator, the push-pull FETs give you high efficiency compared to the linear equivalents. If you can find/substitute your own digital to analog equivalent, you can have good THD and great efficiency at some very respectable power levels. There are other D/A techniques that can give you the similar characteristics, but if you're going for minimal, the class-D emulation might get you close to your analog goals. Search this groups.google.com and you might find a few postings about mp3 implementations here and in other newsgroups. "Cool Morning ..." wrote: > Hi, > > I am looking for an FPGA chip which has a built-in DAC. My intend > it to build a portable with three chips only, A compact-flash, an FPGA > containing the MP3 decoder and Compact flash and USB interface, a > power amplifier. Is it possible? > > What's the SIMPLEST approach possible to make a portable MP3 player > in today's technology? > > Kelvin.Article: 46837
> >> You might also want to toss on a small > >> LCD display, they are cheap and only need a few pins, but can convey a > >> lot of information that way. > Probably overall, they ARE cheap. And it is amazing teh amount of > information you can convey for debugging purposes. For prototyping, I have an on-chip text display generator core that uses a handful of LUTs and two 512 B BRAMs to drive a VGA monitor at (5+1)*32 pixels by (8+2)*3*16 lines, ~60 Hz. The second BRAM is used as a 96x5x8 character generator ROM for display of ASCII characters 0x20-0x7F. Externally, IIRC, it requires 3 pins, a couple of resistors, and a VGA connector. (I'll grant you that if all you've got on hand is a 21" monitor, it looks a little funny.) Jan Gray, Gray Research LLCArticle: 46838
Jim Granville wrote: > XC2 is 3.3V capable, with a 1.8V core -> but you have added 5V > compatible. > > These days, that's quite an issue: > > The newer, larger, CPLDs are all shrink devices that CANNOT > tolerate 5V, so you are hooking to a trailing technology device. > > I'd choose carefully, and get a lifetime assurance ( FWIW ) > > Can this app use a small FPGA ? I am only too aware of the issues of using 5 volt TTL logic. But unfortunately, there is a lot of history out there and it doesn't just go away because the low voltage, shrink transistors, thin fast oxides are the new wave. Try building a PC/104 card that won't tolerate 5 volts on its PC/104 interface... :) There is already an FPGA on the board, but try finding an FPGA that will meet the other requirements!!! I think low power and FPGA are a contradiction of terms. :( Have I missed learning about a new FPGA family that has uA standby current??? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46839
rickman wrote: > Peter is > good at waving his hands, but to justify a 4:1 price increase by > anything other than marketing pressures, he would have to show some > unusual data on the chip size change due to extra routing. His other > items don't hold water (at least not a lot). I am really trying to hold my water as best I can! ...Gotta go! > Not trying to be argumentative, C'mon, be your usual self! Peter AlfkeArticle: 46840
Jan Gray wrote: > > > >> You might also want to toss on a small > > >> LCD display, they are cheap and only need a few pins, but can convey a > > >> lot of information that way. > > > Probably overall, they ARE cheap. And it is amazing teh amount of > > information you can convey for debugging purposes. > > For prototyping, I have an on-chip text display generator core that uses a > handful of LUTs and two 512 B BRAMs to drive a VGA monitor at (5+1)*32 > pixels by (8+2)*3*16 lines, ~60 Hz. Anyone for Pong?! :) > (I'll grant you that if all you've got on hand is a 21" monitor, > it looks a little funny.) A bit like plugging an Atari 2600 into a video projector! Still, it's an interesting and cheap solution to get info out of the FPGA during prototyping. A couple of resistors and a VGA socket are much cheaper than the serial-driven LCD displays I've seen around the place. JohnArticle: 46841
Peter Alfke wrote: > > rickman wrote: > > > Peter is > > good at waving his hands, but to justify a 4:1 price increase by > > anything other than marketing pressures, he would have to show some > > unusual data on the chip size change due to extra routing. His other > > items don't hold water (at least not a lot). > > I am really trying to hold my water as best I can! ...Gotta go! > > > Not trying to be argumentative, > > C'mon, be your usual self! > > Peter Alfke Well, I can't argue with the facts!!! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46842
rickman wrote: > > Jim Granville wrote: > > XC2 is 3.3V capable, with a 1.8V core -> but you have added 5V > > compatible. > > > > These days, that's quite an issue: > > > > The newer, larger, CPLDs are all shrink devices that CANNOT > > tolerate 5V, so you are hooking to a trailing technology device. > > > > I'd choose carefully, and get a lifetime assurance ( FWIW ) > > > > Can this app use a small FPGA ? > > I am only too aware of the issues of using 5 volt TTL logic. But > unfortunately, there is a lot of history out there and it doesn't just > go away because the low voltage, shrink transistors, thin fast oxides > are the new wave. Try building a PC/104 card that won't tolerate 5 > volts on its PC/104 interface... :) > > There is already an FPGA on the board, but try finding an FPGA that will > meet the other requirements!!! I think low power and FPGA are a > contradiction of terms. :( > > Have I missed learning about a new FPGA family that has uA standby > current??? Not to mention the inrush current :) I was thinking of the Atmel AT40K family - never used them, so you should check preferred / life indicators, but they do have 5V capability, and are now in the CPLD arena ( logic/price ?) Just looking at the May 2002 info, of AT40K05AL, I see - 7V ABS MAX pin rating - 0.6mA unpgmd Icc - POR peak < 50mA looks PC/104 friendly ? ... they are not 'new', but for 5V you need 'old' :) -jgArticle: 46843
Does any one know of a 555 schematic or vhdl for xilinx or other clock circuit ? Trying to minimise external components.There is very little space left on the board I'm using. Only got enough space for 2 8pin dil dipswitches ,4 leds, 7 transistors, 7 resistors and 1 seven segment display. Need a clock Max clock needed is 1MHz I am a beginner, still using schematics. All help greatly appreciated. AlexArticle: 46844
"Peter Alfke" <palfke@earthlink.net> wrote in message news:3D7C176F.D6CA850F@earthlink.net... > (snip) > BTW, the billions of years were somwhat tongue-in-cheek. But that's what you > get with exponential functions...If there is no better explanation, I take > math anytime. Do you consider the case where an alpha particle comes through at just the wrong time? When your MTBF gets that long, it might matter. I have noticed MTBF for hard disk drives in the hundreds of years range, yet I don't think anyone would still want to use one then. I do remember when I used to use mainframe machines, and they would report the current value of the MTBF on the wall for all to see. -- glenArticle: 46845
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:aliref$1pp18i$1@ID-84877.news.dfncis.de... > "Peter Alfke" <palfke@earthlink.net> schrieb im Newsbeitrag > news:3D7C176F.D6CA850F@earthlink.net... > > > If I can decypher your drawing, thta's exactly what we use for measuring. > > Look at XAPP094... > > Hmmm. > If I got it right, you have a free running clock with 50 MHz and another > free running 350 Mhz clock for sampling. > Both clock are NOT related to each other by deriving them from the same > clock source or by use of a PLL. > In this case, the phase drift between the two clocks is undefined, random. > What does it mean? I remember from the TTL days someone explaining that, I believe it is the 74S124, dual oscillator, you could only use one because they would phase lock even if you didn't want them to. Keeping two oscillators from locking is not always easy. -- glenArticle: 46846
> Yep, good call, especially for prototyping. "Is it working? Yes, I've > got a 2 HZ blinking light, just like I expected!" I'd go slightly farther and suggest several debugging connections - places where you can conveniently connect a scope and/or an external input. Might as well put LEDs on them unless you are really tight on board space. But I like LEDs. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 46847
Jim Granville wrote: > Not to mention the inrush current :) No, I am very familiar with the power on current. I finally got Xilinx to properly state their requirements for the power supply so that I could design one to startup a Spartan IIE. It took some dozen or so emails and contact with the right internal person. > I was thinking of the Atmel AT40K family - never used them, so > you should check preferred / life indicators, but they > do have 5V capability, and are now in the CPLD arena ( logic/price ?) > > Just looking at the May 2002 info, of AT40K05AL, I see > - 7V ABS MAX pin rating > - 0.6mA unpgmd Icc > - POR peak < 50mA > > looks PC/104 friendly ? ... they are not 'new', but for 5V you need > 'old' :) There is old and there is OLD! I would not touch that part with a ten foot pole. It is way too old. It also needs support to power on configure and although I did not state it (if you want the full spec, I can send you a detailed document of about 35 pages) it really needs to be flash based so that it can be ready on power up. I run the bus reset through this part. Yes, the PC/104 spec has a bus reset signal. I appreciate the help, but why are you trying so hard to find an alternative? I am quite happy with the XCR3256XL other than needing a few more pins. This all started when I found out that the next size part, XCR3384XL is over 4x the price. I assumed that was because it was a new part. The Xilinx people want you to thing it has to do with the economics of Si manufacturing. Obviously it is due to the lack of price pressure at this node. BTW, there is a BIG difference between "unpgmd Icc" and 0 Hz Icc. Assuming that I could use the AT40 FPGA with a small PROM, it would have to have the low current after programming. And this part is not boundary scan compatible I bet... But thanks anyway. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 46848
> Just looking at the May 2002 info, of AT40K05AL, I see > - 7V ABS MAX pin rating ... > looks PC/104 friendly ? ... they are not 'new', but for 5V you need > 'old' :) I'm not familiar with the fine print of PC/104. I seem to remember that the hard problem for PCI is an 11 V spike. That happens when a driver goes from low to high and the bus is unloaded and the reflection bounces off the other end and comes back so you get back the classic twice as much as you sent. If you FCC is 5.5, then you get back 11. (Even if your driver doesn't jump up to 5.5V output in order to provoke a horrible reflection, the one on the chip next to you might do it.) Do PC/104 systems have the same problem? If not, how do they avoid it? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 46849
>How about testing this as well : >Check the lifetime curve for double edged syncroniser: > > +---------+----------< CLK > | +---+ | +---+ > +-|> | +-o|> | > | | | | >----|D Q|------|D Q|--- Qo > | | | | > +---+ +---+ [note bubble on second clock input] What are you trying to do? I don't see any point in testing this circuit. That is I think we understand things well enough to predict the answer. I'd much rather have Peter collecting data at low voltage and high temperatures or working on other types of chips. Sure, if he runs out of other things to try, checking this would be good. This is potentially interesting if CLK is running slowly. Peter's numbers show that you need ~2000 pS, and that assumes tight routing. If your clock is twice that and you know it's a 50-50 duty cycle, then the above circuit is safe and it saves a half cycle. I would normally put the bubble on the first FF. This way you only get a 1/2 cycle for Qo to get to the rest of the logic and that might be a long path. (But the tools should be able to check that.) In general, being tricky around metastability is asking for troubles. It's much safer to have a clean circuit that is easy to check by eye. If you try to be tricky, you might forget things like the 50-50 clock requirement, or somebody who takes over your design might miss it... Yes, I've done things like the above to save a half cycle. But I'm real careful because the first time we did that we got burned. That was back in the old TTL days and the chip we picked to get the falling edge clock was no good for metastability. (And we thought we understood metastability.) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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