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Dear all, I have an question about Virtex II's DCM. For example, I have a 400Mhz clock signal. Then how can I get a 90-degree phase shifted clock signal from it? I have checked the VirtexII's datasheet. Since 400MHz clock is regarded as a high frequency, clk90 is not supported for 400MHz clock signal in DCM. So can I use the phase shift parameter in DCM to achieve the 90-degree phase shift? Or is there any other method to achive it? Please advise, thanks. Regards, KennethArticle: 46076
Greetings all I guess I'm not the first person to be having this problem. "ISE/Foundation 4.2i programming interface not supported in XP." Is there a common soulution? Some third party tool or push button switches on the JTAG interface and enter it manually? :-) (jk) TIA, Greg the Grog.Article: 46077
Mike, As Ray suggested, Xilinx Coregen provides a pipelined integer divider. I have not seen any non-pipelined divider yet, even if there was, it would be rather slow that it would not make sense in your design. I would suggest you try to replace dividers with shift operators. To do this, try to define the divisors as 2's powers. Jianyong Niu "mikest" <mikest@ccs.nrl.navy.mil> wrote in message news:3D595D48.6000403@ccs.nrl.navy.mil... > Hello, > > I was wondering if anyone has tried the Xilinx System generator blockset > and can provide assistance in building a divider block. It doesn't have > one and I could use it. I know that a divider is basically a shift and a > subtraction and I am trying to put one together. Let me know if there is > one already. > > Thank You > Mike >Article: 46078
Kenneth, Correct, you use the fixed phase shift to shift it precisely 90 degrees, +/- one tap (+/- 60 ps). Or, you use whatever phase shift you like to center the clock where you need it. Austin Kenneth wrote: > Dear all, > > I have an question about Virtex II's DCM. > > For example, I have a 400Mhz clock signal. Then how can I get a > 90-degree phase shifted clock signal from it? > > I have checked the VirtexII's datasheet. Since 400MHz clock is > regarded as a high frequency, clk90 is not supported for 400MHz > clock signal in DCM. So can I use the phase shift parameter > in DCM to achieve the 90-degree phase shift? Or is there any other > method to achive it? > > Please advise, thanks. > > Regards, > KennethArticle: 46079
Wait for new version - due in a few weeks. William Hall Remove any X in my email addressArticle: 46080
Hi Holger, I will not comment on the usage on MicroBlaze since I developed it. But I can comment on the migration from MicroBlaze to V2PRO. We have been working hard to get this as easy as possible. The biggest obstacle when moving an embedded processor design from one processor to another processor is not as people believe the instruction set, but it's the device drivers= and they also depend on the available peripherals. Since MicroBlaze and V2PRO share exactly the same peripherals and the sam= e device drivers, we removed the biggest problem. Our goal is that you can move from MicroBlaze to V2PRO with a push button= =2E Since there is some hardware difference between MicroBlaze and PowerPC, t= here will however sometimes be some manual work involved. But the SW will be e= asy to move. It's actually also easy to from V2PRO to MicroBlaze ;-) Hope that this helps G=F6ran Holger Venus wrote: > Hi all, > does any body has experience with embedded processor IP cores in FPGA? > I am especial interested on the behaviour of the Xilinx MicroBlaze usag= e. > What are the main functions the processor is used for? > What about the code size? > What about the processing power, the FPGA system clock? > How where the own modules connected to the processor core, via the IBM > core connect bus (OPB)? > Where the gnu software tools suitable for development and test / debug?= > Would you do it the same way or why not? > Could this way open a path to a V2PRO migration of a family of designs > (start with MicroBlaze and expand to V2PRO if available as needed? > > Thanks for any (related) comment, > > Holger VenusArticle: 46081
In article <ajigb9$1b4d74$1@ID-22088.news.dfncis.de>, Manfred Kraus <newsreply@cesys.com> wrote: >Bill, >If everyone here would promote his products, this NG >would be completly useless. Please think about that >before advertising again. Actually, promotion in the newsgroup, if done right, can be a good thing. But you have to be up front about it, etc etc etc. EG, this is a really NIFTY idea, pitty the FPGA is a bit of a dog: it wolud be so much more useful with a Spartan IIE. It would also be better if it used a SystemACE part and booted out of a compact flash slot which the FPGA could access: so no funky parallel port configuration required. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 46082
Unlike multiplication, the arithmetic for each partial result depends on the
previous partial result. Because of this, division does not respond well to
the techniques used to speed up multipliers. If it is division by a fixed
divisor or a limited set of divisors, you can use a multiplier and a table of
1/x constants to reduce the problem to a fast multiplier. For general purpose
division however, you are stuck with having to handle the sub-operations
sequentially. This is why we generally try to find alternative algorithms to
reduce the need for a divide in hardware.
JianyongNiu wrote:
> Mike,
> As Ray suggested, Xilinx Coregen provides a pipelined integer divider. I
> have not seen any non-pipelined divider yet, even if there was, it would be
> rather slow that it would not make sense in your design.
>
> I would suggest you try to replace dividers with shift operators. To do
> this, try to define the divisors as 2's powers.
>
> Jianyong Niu
>
> "mikest" <mikest@ccs.nrl.navy.mil> wrote in message
> news:3D595D48.6000403@ccs.nrl.navy.mil...
> > Hello,
> >
> > I was wondering if anyone has tried the Xilinx System generator blockset
> > and can provide assistance in building a divider block. It doesn't have
> > one and I could use it. I know that a divider is basically a shift and a
> > subtraction and I am trying to put one together. Let me know if there is
> > one already.
> >
> > Thank You
> > Mike
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46083You can try the Hotman product. Worst case you'd have to find a xp parallel port driver on the web and hack the jtag example. The free trial for Hotman is a month. In that time Xilinx should have a solution.. Steve www.vcc.com "Grog" <shem_an_na@SPAM_ME_NOThotmail.com> wrote in message news:1g579.9432$xL5.31977@news-server.bigpond.net.au... > Greetings all > > I guess I'm not the first person to be having this problem. > "ISE/Foundation 4.2i programming interface not supported in XP." > Is there a common soulution? > Some third party tool or push button switches on the JTAG interface and > enter it manually? :-) (jk) > > TIA, > Greg the Grog. > >Article: 46084
nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote in message news:<ajhs8d$2n5k$1@agate.berkeley.edu>... > In article <7299ab58.0208151908.61aa191b@posting.google.com>, > Ryan <ryan_rs@c4.com> wrote: > >> I'd say use MIPS or a small-register-windowed SPARC as your ISA, > >> simply so you don't have compiler issues. SPARC I know you can > >> release, MIPS I think so. Arm is also nice from an ISA viewpoint, but > >> they have patent lawyers and ISA related patents and ENFORCE them > >> against ISA clones. > > > >ISA design is one of the funnest parts! And porting the gcc chain is > >also part of the project. > > Use LCC, its much easier to retarget. > > Also, how much do you REALLY gain vs having more established tools? I'm pretty sure I don't REALLY gain much at all from this whole project. I suppose it has to do with one's definition of a real gain. Certainly from the financial, employment, and social standpoints this project is a loss, not a gain. * It will cost some money. * It will take some time away from my job (not a hardware field). * It will cause me to live in my bedroom during the weekends. BUT: It will be the largest and most involved hardware project I have undertaken. Also, I have some fond memories of living in the university lab working on projects. Thanks for the LCC suggestion. I had not heard of it. I will take a look. -RyanArticle: 46085
In article <7299ab58.0208161105.37c04cd7@posting.google.com>, Ryan <ryan_rs@c4.com> wrote: >> Also, how much do you REALLY gain vs having more established tools? > >I'm pretty sure I don't REALLY gain much at all from this whole >project. I suppose it has to do with one's definition of a real gain. I mean in terms of gain from the intellectual exercise: You gain very little from designing your own ISA. Retargeting tools is a pain in the ass, porting to a new system is hard enough without having to retarget the compiler. Doing a new ISA adds a lot of shitwork without adding intellectual content. Not to mention it makes your design less usable by anyone lese. You gain very little in saving hardware area, MIPS is already a good, simple ISA, and there is only really one stupidity (the branch delay slot) to deal with. >Thanks for the LCC suggestion. I had not heard of it. I will take a >look. It's a nice compiler. The results aren't great, but it is easy to retarget. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 46086
Hello,
Currently I am trying to use a spartan2e as a timer counter to measure a
clock pulse. The input to the dll is 102.4MHz and I am using all 4
quadrature outputs (clk0, clk90, clk180, and clk270) to drive 4 counters and
then summing the output of the counters
(count<=count0+count90+count180+count270). The problem is that the clocks
are not perfect by the time they get to the counters due to distribution
delays, etc. Also the buffers are not close enough to use the 4 buffers
properly on 4 dll outputs. So...
Here is my idea...
Provide a 204.8MHz clock input to the DLL then use the clk0 and clk180
outputs from the DLL in high frequency mode to drive 2 counters and then sum
them. By the way, the counters use an enable input to key them on and off.
Related idea...
Can I (or should I) use a second dll to generate the 204.8 MHz from a 102.4
MHz source or should I just start with a 204.8 MHz oscillator to begin
with.?
Another question...
I am currently distributing the 102.4MHz as a LVTTL signal. Bad news!!!
Clock noise is unexpectedly high in the adjacent analog sections. Previous
design used a spartanXL with a LVPECL to TTL converter (at 204.8 MHz).
Should I try to use the LVPECL clock input on the Spartan2E or is it a real
pain? Note: I can't afford the time or money for another respin of the
circuit board.
Thanks,
Theron Hicks
Article: 46087The DLLs provide 50% duty cycle correction so I'd just use the 0 and 90 degree phases and have two counters clocked off positive edges, two clocked off negative edges. Additionally, you can clock double in the DLL and use the positive and negative transitions of the lone clock, again accuracy is provided by the 50% duty cycle correction. Don't the Spartan-IIEs have real differential inputs? If you used true differential clock inputs, the common mode clock noise problems would be reduced. Any jitter problems on your original signal (phase modulation) will still be with you independent of what signaling standard you use; it's only the common mode or power supply feedthrough that gets you. Theron Hicks wrote: > Hello, > Currently I am trying to use a spartan2e as a timer counter to measure a > clock pulse. The input to the dll is 102.4MHz and I am using all 4 > quadrature outputs (clk0, clk90, clk180, and clk270) to drive 4 counters and > then summing the output of the counters > (count<=count0+count90+count180+count270). The problem is that the clocks > are not perfect by the time they get to the counters due to distribution > delays, etc. Also the buffers are not close enough to use the 4 buffers > properly on 4 dll outputs. So... > > Here is my idea... > Provide a 204.8MHz clock input to the DLL then use the clk0 and clk180 > outputs from the DLL in high frequency mode to drive 2 counters and then sum > them. By the way, the counters use an enable input to key them on and off. > > Related idea... > > Can I (or should I) use a second dll to generate the 204.8 MHz from a 102.4 > MHz source or should I just start with a 204.8 MHz oscillator to begin > with.? > > Another question... > > I am currently distributing the 102.4MHz as a LVTTL signal. Bad news!!! > Clock noise is unexpectedly high in the adjacent analog sections. Previous > design used a spartanXL with a LVPECL to TTL converter (at 204.8 MHz). > Should I try to use the LVPECL clock input on the Spartan2E or is it a real > pain? Note: I can't afford the time or money for another respin of the > circuit board. > > Thanks, > Theron HicksArticle: 46088
I'm looking at using the Xilinx V2PRO / PowerPC for some floating point work. I gather that this has no floating point hardware. Is it sensible/practical to have an FP Multiplier/Divider on the FPGA? How good is it anyway at FP operations? If one can clock it at 300MHz perhaps it will keep up with a 50MHz DSP (?) William Hall Remove any X in my email addressArticle: 46089
"Grog" <shem_an_na@SPAM_ME_NOThotmail.com> wrote in message news:1g579.9432$xL5.31977@news-server.bigpond.net.au... > Greetings all > > I guess I'm not the first person to be having this problem. > "ISE/Foundation 4.2i programming interface not supported in XP." > Is there a common soulution? > Some third party tool or push button switches on the JTAG interface and > enter it manually? :-) (jk) > > TIA, > Greg the Grog. > > works here fine. xp pro on a athlon and celeron 400. Also for windows 2000. First install a port driver that allows access to the ports for the software under xp. Allows programs to think they can access the hardware directly. like DLPortIO for serial or parallel. Or xilinx multilink for usb. http://www.google.com/search?sourceid=navclient&q=DLPortIO Must say ISE/Foundation 4.2i is rather crappy. Let me qualify that. The version that came with the book Logic and Computer Design Fundamental 2nd edition by Mano and Kime. No simulator. Doesn't install properly. Have to reinstall it three times to get it working properly. Install disk is labeled documents. Document disc is labeled install. Have to manually set the environment / path variables. 2.2 is a lot more useful. Whatever moron packaged 4.2i Foundation Edition together at prentice hall should be shot. Lecturers have told everyone to install 2.2 and forget 4.2. Or install both but use the simulator from 2.2 and 4.2i for everything else. Hey Greg , are you doing IDS(Introductory Digital Systems) at UTS ? alxxArticle: 46090
Floating point is doable in FPGA,s although full ieee floating point can be
cumbersome. The performance is going to depend on how deep you pipeline
it, which in the case of an accumulator means doing something to absorb the
pipeline delays in the loop defined by the feedback path.
For arithmetic, unless the carry chains in V2-pro are significantly better
than those in V2, you aren't going to get anywhere near a 300 MHz clock
rate for the arithmetic. The carry chains in the V2 are slower than those
in virtexE by a significant amount, and the problem isn't in the added
bits, it is in the time to get on and off the chain. For the V2-4, the top
end for arithmetic is right about 200MHz, and you might have to do some
hand-routing to get that in a congested design (the router doesn't do as
good a job as previous versions of the software did when given a particular
placement).
William Hall wrote:
> I'm looking at using the Xilinx V2PRO / PowerPC for some floating point
> work.
>
> I gather that this has no floating point hardware. Is it
> sensible/practical to have an FP Multiplier/Divider on the FPGA?
>
> How good is it anyway at FP operations? If one can clock it at 300MHz
> perhaps it will keep up with a 50MHz DSP (?)
>
> William Hall
> Remove any X in my email address
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46091hi, Can someone tell me how would i be able to download a text file or a Binary executable code to FPGA memory so that my controller would be able to read from it . Thanks, Ram. "reply in the newsgroup" <deepfry.a.spammer.today@abuse.org> wrote in message news:<ajcddp$gak$1@slb7.atl.mindspring.net>... > If there's enough space left in the FPGA, you can put in two > applications by using one bit to control a set of MUXes to > select which one is active. Or, have more selection bits and > put in more applications. > > "Ramakrishnan" <rxv20@po.cwru.edu> wrote in message > news:15cf85fc.0208130701.67480ed3@posting.google.com... > > Hi, > > So basically u r saying is that , it is not possible to implement > > two applications without downloading them seperately one after the > > other, that basically means , it is kind of impossible to reconfigure > > dynamically to switch to other application at run time. > > > > Thanks, > > > > Ram. > > > > "reply in the newsgroup" <deepfry.a.spammer.today@abuse.org> wrote in > message news:<aj9mtc$beh$1@slb6.atl.mindspring.net>... > > > Then you'll need a separate simulation for each configuation. > > > I was assuming that you were using only one configuration, > > > but not initializing all the sections in tests that weren't using > > > them. > > > > > > "Ramakrishnan" <rxv20@po.cwru.edu> wrote in message > > > news:15cf85fc.0208121403.b469915@posting.google.com... > > > > Hi, > > > > I really didn't understand what you meant in your post. Actually > > > > the number of memories for each and every application varies in my > > > > architecture, for example bandpass filter implementation required 12 > > > > memories of 4 elememts whereas cosine filter needed only 10 memories. > > > > > > > > So every time a new application is to be implemented, the whole > > > > architecture would have to some how be reset to reflect the exact > > > > number of memories. > > > > > > > > Thanks, > > > > > > > > Ram. > > > > > > > > "reply in the newsgroup" <deepfry.a.spammer.today@abuse.org> wrote in > message news:<aj8mlp$i87$1@slb7.atl.mindspring.net>... > > > > > "Ramakrishnan" <rxv20@po.cwru.edu> wrote in message > > > > > news:15cf85fc.0208120735.1884e326@posting.google.com... > > > > > > Hi, > > > > > > I have a few questions with regard to Xilinx 4000 series FPGA. > > > > > > > [deleted] > > > > > > The problem i think would like in the fact that some of the > > > > > > applications that i choose to implement would use fewer memories > in my > > > > > > VHDL architecture than others. So how would i be able to overcome > this > > > > > > problem. > > > > > > > > > > > Then why not create a file for each memory not used in all the > tests, > that > > > > > loads this memory with random data, and use the resulting files to > load > any > > > > > memory not used in the current test so that all the memories end up > > > > > loaded?Article: 46092
"Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:ajjjr1$1l1$1@agate.berkeley.edu... > In article <7299ab58.0208161105.37c04cd7@posting.google.com>, > Ryan <ryan_rs@c4.com> wrote: > >> Also, how much do you REALLY gain vs having more established tools? > > > >I'm pretty sure I don't REALLY gain much at all from this whole > >project. I suppose it has to do with one's definition of a real gain. > > I mean in terms of gain from the intellectual exercise: You gain very > little from designing your own ISA. To the contrary. A new instruction set architecture that coevolves with the FPGA processor datapath implementation can achieve significant performance, size, cost, power, etc. improvements over a full reimplementation of a legacy ISA. There are plenty of slow 1000-3000 LUT FPGA implementations of legacy RISC ISAs, whereas an implementation of an FPGA-optimized integer RISC ISA can be <180 LUTs (16-bit) and <300 LUTs (32-bit) and relatively fast. > Retargeting tools is a pain in the ass, porting to a new system is > hard enough without having to retarget the compiler. ... Not to > mention it makes your design less usable by anyone lese. Not to mention, having to maintain the port as the underlying code base evolves. A simpler approach is static or dynamic binary translation from a legacy ISA to a streamlined, FPGA-optimized ISA. Debugging remains a challenge, though. It is also worth considering implementing a simplified/subsetted implementation of a legacy ISA, binary translating from full ISA to subset ISA. (The resulting code still runs fine on full ISA processors, of course, and potentially simplifies the debugger issues.) > >Thanks for the LCC suggestion. I had not heard of it. I will take a > >look. See also www.fpgacpu.org/papers/xsoc-series-drafts.pdf, which includes a brief discussion of retargeting LCC to a new FPGA CPU ISA. Jan Gray, Gray Research LLCArticle: 46093
I'm using FIR filters in Spartan IIs (200) for radio astronomical applications. Right now I have two 40 tap LP filters per FPGA (cut-off approximately 0.125) running at 32MHz. The input is a 4 bit quadrature signal, with post detection integration after the filters of the order of 2^14 samples. This long integration is neccessary in order to obtain the signal which is about 6 orders of magnitude less than the noise. Now, my question is this: would there be any advantage in switching to a polyphase filtering technique? I don't know much about it...I see it usually involves some decimation and interpolation, although I am not keen to start throwing away samples as every sample helps to increase the SNR by averaging out the noise. Thanks AdrianArticle: 46094
Hi Austin, Thanks for your help. But I feel strange that if i can make a 90-degree phase shifted clock by setting the phase shift parameter, why the CLK90 is not supported in the high frequency mode in DCM? Regards, Kenneth Austin Lesea wrote: > > Kenneth, > > Correct, you use the fixed phase shift to shift it precisely 90 degrees, > +/- one tap (+/- 60 ps). > > Or, you use whatever phase shift you like to center the clock where you > need it. > > Austin > > Kenneth wrote: > > > Dear all, > > > > I have an question about Virtex II's DCM. > > > > For example, I have a 400Mhz clock signal. Then how can I get a > > 90-degree phase shifted clock signal from it? > > > > I have checked the VirtexII's datasheet. Since 400MHz clock is > > regarded as a high frequency, clk90 is not supported for 400MHz > > clock signal in DCM. So can I use the phase shift parameter > > in DCM to achieve the 90-degree phase shift? Or is there any other > > method to achive it? > > > > Please advise, thanks. > > > > Regards, > > KennethArticle: 46095
Hi, Has anybody Information how to manipulate the contents of ROM cells of Altera FPGAs after Synthesis. I found a similar Topic in the archive with one reply stating that Quartus 2.1 might be able to do this. However I would like to do this manually by changing the appropriate bitsd in the SOF file (assuming that the each EAB block has a constant position in the SOF File and assigning the ROM to specified EABs). I've been able to find out the EAB positions in the SOF File, but unfortunately the SOF File contains some checksums. Is there a description of the SOF File format (especially the used checksums). thanks in advance, BernhardArticle: 46096
please go thro this circuit and tell me is there any why to reduce the design the various variables are pixclk_reg[], lc_msb_inv[] & lc_byt_cnt[]. depending on the values of these variables the design changes. i have given u only two different conditions like pixclk_reg[] == 6 & lc_byt_cnt[] == 0 and pixclk_reg[] == 6 & lc_byt_cnt[] == 1. but still there are more conditions like pixclk_reg[] == 6 & lc_byt_cnt[] == 2 pixclk_reg[] == 6 & lc_byt_cnt[] == 3 pixclk_reg[] == 5 & lc_byt_cnt[] == 0 pixclk_reg[] == 5 & lc_byt_cnt[] == 1 pixclk_reg[] == 5 & lc_byt_cnt[] == 2 ---- --- --- --- pixclk_reg[] == 3 & lc_byt_cnt[] == 3 end_of_line is just A CONDITION CAN U PLEASE HELP ME OUT MAIMUNA the design is as below if pixclk_reg[] == 6 & lc_byt_cnt[] == 0 then if lc_msb_inv[] == 0 then if end_of_line == TRUE then line_cntr_one[6..0] = line_cntr_one[6..0] +1; if line_cntr_one[6..0] == TRUE then line_cntr_one[6..0] =1; else line_cntr_one[6..0] = line_cntr_one[6..0]; end if; else line_cntr_one[] = line_cntr_one[]; end if; elsif lc_msb_inv[] == 1 then if end_of_line == TRUE then line_cntr_one[5..0] = line_cntr_one[5..0] +1; if line_cntr_one[5..0] == TRUE then line_cntr_one[5..0] =1; else line_cntr_one[5..0] = line_cntr_one[5..0]; end if; else line_cntr_one[] = line_cntr_one[]; end if; elsif lc_msb_inv[] == 2 then if end_of_line == TRUE then line_cntr_one[4..0] = line_cntr_one[4..0] +1; if line_cntr_one[4..0] == TRUE then line_cntr_one[4..0] =1; else line_cntr_one[4..0] = line_cntr_one[4..0]; end if; else line_cntr_one[] = line_cntr_one[]; end if; elsif lc_msb_inv[] == 3 then if end_of_line == TRUE then line_cntr_one[3..0] = line_cntr_one[3..0] +1; if line_cntr_one[3..0] == TRUE then line_cntr_one[3..0] =1; else line_cntr_one[3..0] = line_cntr_one[3..0]; end if; else line_cntr_one[] = line_cntr_one[]; end if; elsif lc_msb_inv[] == 4 then if end_of_line == TRUE then line_cntr_one[2..0] = line_cntr_one[2..0] +1; if line_cntr_one[2..0] == TRUE then line_cntr_one[2..0] =1; else line_cntr_one[2..0] = line_cntr_one[2..0]; end if; else line_cntr_one[] = line_cntr_one[]; end if; elsif lc_msb_inv[] == 5 then if end_of_line == TRUE then line_cntr_one[1..0] = line_cntr_one[1..0] +1; if line_cntr_one[1..0] == TRUE then line_cntr_one[1..0] = 1; else line_cntr_one[1..0] = line_cntr_one[1..0]; end if; else line_cntr_one[] = line_cntr_one[]; end if; end if; elsif pixclk_reg[] == 6 & lc_byt_cnt[] == 1 then if end_of_line == TRUE then line_cntr_one[6..0] = line_cntr_one[6..0]+1; if line_cntr_one[6..0] == TRUE then line_cntr_one[6..0] = 0; else line_cntr_one[6..0] = line_cntr_one[6..0]; end if; else line_cntr_one[6..0] = line_cntr_one[6..0]; end if; if end_of_line == TRUE & line_cntr_one[] == TRUE then if lc_msb_inv[] == 0 then if end_of_line == TRUE then line_cntr_two[6..0] = line_cntr_two[6..0] +1; if line_cntr_two[6..0] == TRUE then line_cntr_two[6..0] = 0; else line_cntr_two[6..0] = line_cntr_two[6..0]; end if; else line_cntr_two[] = line_cntr_two[]; end if; elsif lc_msb_inv[] == 1 then if end_of_line == TRUE then line_cntr_two[5..0] = line_cntr_two[5..0] +1; if line_cntr_two[5..0] == TRUE then line_cntr_two[5..0] = 0; else line_cntr_two[5..0] = line_cntr_two[5..0]; end if; else line_cntr_two[] = line_cntr_two[]; end if; elsif lc_msb_inv[] == 2 then if end_of_line == TRUE then line_cntr_two[4..0] = line_cntr_two[4..0] +1; if line_cntr_two[4..0] == TRUE then line_cntr_two[4..0] = 0; else line_cntr_two[4..0] = line_cntr_two[4..0]; end if; else line_cntr_two[] = line_cntr_two[]; end if; elsif lc_msb_inv[] == 3 then if end_of_line == TRUE then line_cntr_two[3..0] = line_cntr_two[3..0] +1; if line_cntr_two[3..0] == TRUE then line_cntr_two[3..0] = 0; else line_cntr_two[3..0] = line_cntr_two[3..0]; end if; else line_cntr_two[] = line_cntr_two[]; end if; elsif lc_msb_inv[] == 4 then if end_of_line == TRUE then line_cntr_two[2..0] = line_cntr_two[2..0] +1; if line_cntr_two[2..0] == TRUE then line_cntr_two[2..0] = 0; else line_cntr_two[2..0] = line_cntr_two[2..0]; end if; else line_cntr_two[] = line_cntr_two[]; end if; elsif lc_msb_inv[] == 5 then if end_of_line == TRUE then line_cntr_two[1..0] = line_cntr_two[1..0] +1; if line_cntr_two[1..0] == TRUE then line_cntr_two[1..0] = 0; else line_cntr_two[1..0] = line_cntr_two[1..0]; end if; else line_cntr_two[] = line_cntr_two[]; end if; end if; else line_cntr_two[] = line_cntr_two[]; end if; if line_cntr_one[6..0] == TRUE then line_cntr_one[6..0] =1; else line_cntr_one[6..0] = line_cntr_one[6..0]; end if; --- --- --- ---- END;Article: 46097
Isn't there a case for a CASE statement here? If not to reduce the design, at least to make it a bit more readable! Adrian maimuna <maimuna_a@nrsa.gov.in> wrote in message news:13bf39b3.0208190350.447bd4bf@posting.google.com... > please go thro this circuit and tell me is there any why to reduce the > design > > the various variables are pixclk_reg[], lc_msb_inv[] & lc_byt_cnt[]. > depending on the values of these variables the design changes. > i have given u only two different conditions like pixclk_reg[] == 6 & > lc_byt_cnt[] == 0 and pixclk_reg[] == 6 & lc_byt_cnt[] == 1. but still > there are more conditions like > pixclk_reg[] == 6 & lc_byt_cnt[] == 2 > pixclk_reg[] == 6 & lc_byt_cnt[] == 3 > pixclk_reg[] == 5 & lc_byt_cnt[] == 0 > pixclk_reg[] == 5 & lc_byt_cnt[] == 1 > pixclk_reg[] == 5 & lc_byt_cnt[] == 2 > ---- > --- > --- > --- > pixclk_reg[] == 3 & lc_byt_cnt[] == 3 > end_of_line is just A CONDITION > CAN U PLEASE HELP ME OUT > MAIMUNA > > the design is as below > > > if pixclk_reg[] == 6 & lc_byt_cnt[] == 0 then > if lc_msb_inv[] == 0 then > if end_of_line == TRUE then > line_cntr_one[6..0] = line_cntr_one[6..0] +1; > if line_cntr_one[6..0] == TRUE then > line_cntr_one[6..0] =1; > else line_cntr_one[6..0] = line_cntr_one[6..0]; > end if; > else line_cntr_one[] = line_cntr_one[]; > end if; > elsif lc_msb_inv[] == 1 then > if end_of_line == TRUE then > line_cntr_one[5..0] = line_cntr_one[5..0] +1; > if line_cntr_one[5..0] == TRUE then > line_cntr_one[5..0] =1; > else line_cntr_one[5..0] = line_cntr_one[5..0]; > end if; > else line_cntr_one[] = line_cntr_one[]; > end if; > elsif lc_msb_inv[] == 2 then > if end_of_line == TRUE then > line_cntr_one[4..0] = line_cntr_one[4..0] +1; > if line_cntr_one[4..0] == TRUE then > line_cntr_one[4..0] =1; > else line_cntr_one[4..0] = line_cntr_one[4..0]; > end if; > else line_cntr_one[] = line_cntr_one[]; > end if; > elsif lc_msb_inv[] == 3 then > if end_of_line == TRUE then > line_cntr_one[3..0] = line_cntr_one[3..0] +1; > if line_cntr_one[3..0] == TRUE then > line_cntr_one[3..0] =1; > else line_cntr_one[3..0] = line_cntr_one[3..0]; > end if; > else line_cntr_one[] = line_cntr_one[]; > end if; > elsif lc_msb_inv[] == 4 then > if end_of_line == TRUE then > line_cntr_one[2..0] = line_cntr_one[2..0] +1; > if line_cntr_one[2..0] == TRUE then > line_cntr_one[2..0] =1; > else line_cntr_one[2..0] = line_cntr_one[2..0]; > end if; > else line_cntr_one[] = line_cntr_one[]; > end if; > elsif lc_msb_inv[] == 5 then > if end_of_line == TRUE then > line_cntr_one[1..0] = line_cntr_one[1..0] +1; > if line_cntr_one[1..0] == TRUE then > line_cntr_one[1..0] = 1; > else line_cntr_one[1..0] = line_cntr_one[1..0]; > end if; > else line_cntr_one[] = line_cntr_one[]; > end if; > end if; > elsif pixclk_reg[] == 6 & lc_byt_cnt[] == 1 then > if end_of_line == TRUE then > line_cntr_one[6..0] = line_cntr_one[6..0]+1; > if line_cntr_one[6..0] == TRUE then > line_cntr_one[6..0] = 0; > else line_cntr_one[6..0] = line_cntr_one[6..0]; > end if; > else line_cntr_one[6..0] = line_cntr_one[6..0]; > end if; > if end_of_line == TRUE & line_cntr_one[] == TRUE then > if lc_msb_inv[] == 0 then > if end_of_line == TRUE then > line_cntr_two[6..0] = line_cntr_two[6..0] +1; > if line_cntr_two[6..0] == TRUE then > line_cntr_two[6..0] = 0; > else line_cntr_two[6..0] = line_cntr_two[6..0]; > end if; > else line_cntr_two[] = line_cntr_two[]; > end if; > elsif lc_msb_inv[] == 1 then > if end_of_line == TRUE then > line_cntr_two[5..0] = line_cntr_two[5..0] +1; > if line_cntr_two[5..0] == TRUE then > line_cntr_two[5..0] = 0; > else line_cntr_two[5..0] = line_cntr_two[5..0]; > end if; > else line_cntr_two[] = line_cntr_two[]; > end if; > elsif lc_msb_inv[] == 2 then > if end_of_line == TRUE then > line_cntr_two[4..0] = line_cntr_two[4..0] +1; > if line_cntr_two[4..0] == TRUE then > line_cntr_two[4..0] = 0; > else line_cntr_two[4..0] = line_cntr_two[4..0]; > end if; > else line_cntr_two[] = line_cntr_two[]; > end if; > elsif lc_msb_inv[] == 3 then > if end_of_line == TRUE then > line_cntr_two[3..0] = line_cntr_two[3..0] +1; > if line_cntr_two[3..0] == TRUE then > line_cntr_two[3..0] = 0; > else line_cntr_two[3..0] = line_cntr_two[3..0]; > end if; > else line_cntr_two[] = line_cntr_two[]; > end if; > elsif lc_msb_inv[] == 4 then > if end_of_line == TRUE then > line_cntr_two[2..0] = line_cntr_two[2..0] +1; > if line_cntr_two[2..0] == TRUE then > line_cntr_two[2..0] = 0; > else line_cntr_two[2..0] = line_cntr_two[2..0]; > end if; > else line_cntr_two[] = line_cntr_two[]; > end if; > elsif lc_msb_inv[] == 5 then > if end_of_line == TRUE then > line_cntr_two[1..0] = line_cntr_two[1..0] +1; > if line_cntr_two[1..0] == TRUE then > line_cntr_two[1..0] = 0; > else line_cntr_two[1..0] = line_cntr_two[1..0]; > end if; > else line_cntr_two[] = line_cntr_two[]; > end if; > end if; > else line_cntr_two[] = line_cntr_two[]; > end if; > if line_cntr_one[6..0] == TRUE then > line_cntr_one[6..0] =1; > else line_cntr_one[6..0] = line_cntr_one[6..0]; > end if; > --- > --- > --- > > ---- > END;Article: 46098
Hi Shay I use the following code to generate the leading edge. Regards Paul --1 GENERATING_LEADING_EDGES : PROCESS (SYSCLK, RESET) BEGIN IF RESET = '1' THEN signal_in_1del <= '0'; signal_in_2del <= '0'; ELSIF RISING_EDGE(SYSCLK) THEN signal_in_1del <= SIGNAL_IN; signal_in_2del <= signal_in_1del; END IF; END PROCESS GENERATING_LEADING_EDGES; --2 --Concurrent signal_in_le <= (signal_in_1del) AND NOT(signal_in_2del);Article: 46099
Kenneth, The DCM is all digital. In the high frequency mode, the delay lines are re-arranged to provide just a single tap for the phase outputs (clk180). Fewer delay lines = better performance at high frequencies. And, a 90 degree phase shift is covered by the fixed (or variable) phase shift anyway. Austin Kenneth wrote: > Hi Austin, > > Thanks for your help. > But I feel strange that if i can make a 90-degree phase shifted > clock by setting the phase shift parameter, why the CLK90 is not > supported in the high frequency mode in DCM? > > Regards, > Kenneth > > Austin Lesea wrote: > > > > Kenneth, > > > > Correct, you use the fixed phase shift to shift it precisely 90 degrees, > > +/- one tap (+/- 60 ps). > > > > Or, you use whatever phase shift you like to center the clock where you > > need it. > > > > Austin > > > > Kenneth wrote: > > > > > Dear all, > > > > > > I have an question about Virtex II's DCM. > > > > > > For example, I have a 400Mhz clock signal. Then how can I get a > > > 90-degree phase shifted clock signal from it? > > > > > > I have checked the VirtexII's datasheet. Since 400MHz clock is > > > regarded as a high frequency, clk90 is not supported for 400MHz > > > clock signal in DCM. So can I use the phase shift parameter > > > in DCM to achieve the 90-degree phase shift? Or is there any other > > > method to achive it? > > > > > > Please advise, thanks. > > > > > > Regards, > > > Kenneth
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