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My design is: --xc18v04(2nd)--c18v04(1st)--fpga- And the daisy chain is Jtag & Master Serial.Jtag mode can work well. But some wrong with Master Serial Mode: 1,promgen generates two split file demo000.mcs&demo001.mcs. and which file match the 1st Prom. 2,whichever method(jtag|Master) I use for config.but fpga can't work well. 3,Please Email me for your convenience!Thanks muck!Article: 46026
Use a board with a smaller part which is supported by Xilinx Webpack. Those virtex 2 parts are MONSTERS, if you mostly want to experiment, a smaller part is fine. A Spartan II is jsut about big enough to fit a synthesized SPARC core, and could easily fit a hand designed, 40+ MHz MIPS. This also cuts your cost to $0 in software. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 46027
And the Spartan II boards can be had for as little as about $120...
Viewlogic is not really supported by Xilinx anymore, and the new Xilinx tools
pretty much focus on HDLs. To use an HDL well, you should start with a mental
picture of your logic in mind. Then describe that circuit with VHDL. A
common trap for software types is to treat VHDL as a programming language
rather than as a hardware description language. The difference is with the
former, the hardware is forced to fit a software construct and in the latter
the hardware is expressed with the software.
"Nicholas C. Weaver" wrote:
> Use a board with a smaller part which is supported by Xilinx Webpack.
> Those virtex 2 parts are MONSTERS, if you mostly want to experiment, a
> smaller part is fine.
>
> A Spartan II is jsut about big enough to fit a synthesized SPARC core,
> and could easily fit a hand designed, 40+ MHz MIPS.
>
> This also cuts your cost to $0 in software.
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46028
Hi Whoami,
Thank you for your reply. ^_^
Reala
"whoami" <whoami@nowhere.net> wrote in message
news:3D59CFC4.3FCA161B@nowhere.net...
> > However, if I want to design the chip directly. I guess that it is
> > something difficult.
>
> Compared to FPGA, ASIC development is much more expensive. The tools
> are more expensive, the NRE (non-recurring expense) are *FAR HIGHER*,
> and the design-cycle (length of time from start to finish) is much
> longer.
>
> If you are *serious* about ASIC-development, your best bet is to
> contact a design services company (esilicon.com, qthink.com,
> flextronics.com, etc. there are many others) which specializes in
> ASIC-development. These companies can give you an overview.
>
> > (eg. what systhesis tools i can you? As the target is not a FPGA, what
> > library used for systhesis?)
>
> Synopsys's Design Compiler is the most popular ASIC synthesis tool.
> Ironically, Synopsys's FPGA compiler (which Xilinx used to OEM in older
> Foundation software) is falling behind Synplicity, Leonardo, etc.
>
> As for the synthesis target ('technology library'), some foundries
> give you a basic library at no cost. (I think TSMC licenses/pays
> Artisan Components for its standard-cell portfolio.) "Advanced"
> macroblocks (PLLs, high-speed I/O drivers, embedded memory arrays)
> generally cost the customer extra $$$.
>
> By the way, the 'synthesis' step is the least difficult part of
> the ASIC development flow. The steps that come afterward get
> more and more hairy!
Article: 46029Take a good look at the XESS XSA-50 ($149) or the BurchEd B5 with an XC2S300E ($190 not including add-on boards). Both can be targeted with free WebPack tools. Both are quite adequate for a thoughtfully designed 32-bit CPU, caches, and TLBs -- maybe 4-8 or so in the 2S300E. There are links to other boards at fpgacpu.org/links.html and at www.optimagic.com/boards.html. You may also wish to join us on the fpga-cpu mailing list, yahoogroups.com/group/fpga-cpu. Jan Gray, Gray Research LLC FPGA CPU News: www.fpgacpu.orgArticle: 46030
Hello, I am working with a XC4010XL FPGA, and I am having the following problem (issue?): - Almost immediately after configuring the FPGA (using asynchronous peripheral mode), it seems to loss its configuration. The strange part is that the DONE pin stays high. I drive a 7segment, 1 digit display, showing a sequence of numbers. The FPGA gets configured long enough to show the first number, then the display fades and the system no longer works. If I download the bitstream using JTAG, the problem doesn't appear. I measured the current in the circuit, in fear of a power supply malfunction, but the circuit consumption is low, so there is no voltage fall (is that the right term?) What can be the cause of such strange behavior? Thank you very much. Mauricio Lange nospam_mlange@hotmail.com (remove nospam_ to email me)Article: 46031
>> Would you tell me the subtle defference between "flip flop" and "register"? fred <not@for.mail> writes: > Flip-flop is the generic term which describes all storage elements whose > output changes for a specific change at its inputs. I would qualify that to "bistable storage elements". An astable multivibrator, such as a one-shot, can be viewed as a short-term storage element, but isn't considered to be a flip-flop. > I've still to decide whether an unclocked storage element (a transparent or > set-reset latch) is a member of the flip-flop type :-) I've never heard the term "set-reset latch" used. There are plenty of references to set-reset flip-flop, though. Anyhow, regarding the original question, flip-flops are commonly divided into two classes, registers and latches. I'm not sure about formal definitions, but in common usage a register is edge-triggered, and the input only matters within a short interval before and after the clock edge (setup time and hold time). A latch is level-sensitive, and while the clock is in the active state, the outputs follow the inputs in real time (with some propogation delay). Once the clock goes inactive, though, the output retains its last state.Article: 46032
samg@codenet.net writes: > I agree that systematic RS system will have the data portion unchanged > but the parity section will screw up the Syndrome generators that are > trying to determine if there is an error. > The reason being that the GF math logic will be slightly different for > 285 vs 301, right? The logic to transform the codes would be as complex as the logic to simply decode and reencode.Article: 46033
>>>>> "John" == John Williams <j2.williams@qut.edu.au> writes:
John> [...]
John> In a testbench I'm trying to define the following procedure:
John>
John> procedure ReadBand(file datafile : TEXT;
John> signal band_sig : out std_logic_vector) is
John> [...]
John> # ERROR: C:/projects/IEICE/tb_acca_pass1.vhd(18): near "file":
John> expecting: IDENTIFIER
Change your procedure declaration to:
procedure ReadBand(datafile: IN TEXT;
signal band_sig : OUT std_logic_vector) is
Procedure can have IN, OUT and INOUT parameters, which can be SIGNAL,
VARIABLE or CONSTANT. The deafault for IN is CONSTANT, and for the
rest VARIABLE.
Regards,
Michal
Article: 46034
Ryan wrote:
>
> Back in university days, about three years ago, I had some fun
> designing a little 8 bit CPU. I used some version of Xilinx
> foundation and a X??4010XL board. Lately, I've wanted to design a
> larger CPU. 32 bit, caches, VM, etc.
>
> As of now, I have nothing. No board, no computer, no tools. Well, I
> have a Mac, but nobody writes CAD stuff for those. Also a 'scope.
>
> I found a nice board, Virtex 2 XC2V1000 and 32 megs of DDR SDRAM.
> About $1000.
>
If you are going to use the free Xilinx ISE WebPACK for a
Virtex-II design, it only supports up to XC2V250.
The largest device supported by ISE WebPACK are Virtex-E XCV300E and
Spartan-IIE XC2S300E.
> I'll get a 2.X GHz PC w/ 1G ram, $1500-2500.
>
Computers are so much cheaper than EDA software or an
oscilloscope . . .
I guess it is a matter of scale of economics . . .
> And some software...
>
> On my first CPU I used the schematic editor in Foundation. It worked
> well. I used a nice hierarchical design and I found it quite easy to
> keep an overall view of the project in my head.
>
> It seems to me that text is a good way to view software because
> software executes in a linear, one-at-a-time fashion. Hardware, on
> the other hand, executes everywhere at once. Though I admit I don't
> know verilog or vhdl, neither seems particulary intuitive or natural.
>
I believe Xilinx's ISE WebPACK comes with a schematic tool
called ECS.
However, I have been a Verilog HDL user from day one, so I don't know
what it is like.
I doubt that you can target Xilinx parts, but Actel's Libero Silver
(Libero Silver is free.) tool does come with an OEM version of Viewdraw.
I recommend that you learn some kind of non-proprietary HDL like
Verilog HDL or VHDL, and not bother with a schematic tool because, in
general, you can design complex digital circuits a lot faster in HDL
than in schematic.
If you are going to learn HDL, I recommend that you learn Verilog-HDL
instead of VHDL because Verilog's syntax is a lot more simple than VHDL,
and VHDL is needlessly verbose than Verilog. (I am sure some people
won't agree with that.)
Since you said you are going to design a microprocessor, you will likely
spend substantial amount of time writing HDL code to verify the
functionality of the microprocessor.
However, most HDL books published don't devote many pages to writing
testbench code to test a design.
The only book I found so far that was "partially" helpful when writing
testbench code was a book called Writing Testbenches - Functional
Verification of HDL Models by Janick Bergeron (Kluwer Academic
Publishers, ISBN 0-7923-7766-4) which costs about $100.
The problem of Writing Testbenches - Functional Verification of HDL
Models I think is that it gives only small code examples throughout the
book, and doesn't contain large enough testbench code that test a bus
interface or a microprocessor.
Although I don't recommend it as a general Verilog-HDL textbook (Try
looking for a different Verilog-HDL textbook.), but a book called
Verilog Digital System Design by Zainalabedin Navabi (McGraw-Hill, ISBN
0-07-047164-9) does contain an 8-bit microprocessor design which might
be helpful when designing your own microprocessor.
The book itself is horrible, but if you are buying one, I will say that
you shouldn't bother reading Chapter 1 through 8 because the author gets
into soooooo many unimportant details.
Most Borders bookstore should have a copy of it.
Computer Organization & Design 2nd Edition by Patterson and Hennessy
(Morgan Kaufmann, ISBN 1-55860-428-6) is another helpful book when
designing a pipelined microprocessor, but doesn't discuss anything about
HDL or how to write testbench code to test a microprocessor.
> It appears I need to purchase one of:
> - Xilinx Foundation $2500
> - Xilinx Alliance $1500 + Third party schematic capture $??
>
> I assume the Alliance package will do simulation and timing? Those
> seem to be post- place-n-route things. Correct?
>
For simulation, you will realistically use an HDL simulator.
Fortunately, ISE WebPACK comes with a free and crippled version of
ModelSim called ModelSim XE-Starter.
It's crippled because if you try to simulate a design larger than 500
HDL statements, the simulation speed will slow down substantially, but
at least it will still let you simulate the design.
> The old Xilinx tool I used in the university lab several years ago
> would be quite sufficient for this project. I understand that Xilinx
> may have replaced it with a not-so-good version recently? Also, I
> have heard a several people say that viewlogic is much better than the
> Xilinx Foundation schematic tool. How much $$ is it?
>
> It seems this project will end up costing $5-6k. Ugh. I write
> software for a living but it still hurts to pay >$2500 for a one-off
> project. I'd use the webpack it doesn't support large chips. Does
> anyone (Peter?) think Xilinx would give me a break for hobbyist
> project like this? Worth a try?
>
> -Ryan
I personally will doubt that Xilinx will ever give away their
paid version software for free unless it is for a non-profit university
research project.
You said you are doing this microprocessor project as a hobby,
and if so, I recommend that you don't spend any money on EDA tools.
In my case, I have developed an initiator/target PCI IP core, and in
that process, the only EDA tools I used were ISE WebPACK and ModelSim
XE-Starter.
I didn't resort to buying Synplify (A synthesis tool that costs $9,000 .
. .) or ModelSim PE (A far less restricted version that costs $4,500 . .
.) because I just couldn't afford them.
In retrospect, neither tools would have helped at all.
All I spent for the project was about $350 on hardware (A
Spartan-II-based PCI prototype card, two option cards, and a parallel
port JTAG programming cable.) and about $500 on books about HDL and PCI.
I didn't use an oscilloscope or a logic analyzer because I just cannot
afford neither one, and that did cost me 2 weeks to figure out a strange
synthesis problem, but eventually I did figure out what was wrong by
doing a post P&R simulation.
After I made sure that my design worked fine during a post P&R
simulation, the PCI card worked perfectly in two computers I tested it.
(Before I did a post P&R simulation, the PCI card will freeze the
computer as soon as I access it . . .)
Probably in your project, you will need at least a logic analyzer at
some point to debug the microprocessor, but you should be able to do
most of the testing on ModelSim.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 46035> Viewlogic is not really supported by Xilinx anymore, and the new Xilinx tools > pretty much focus on HDLs. To use an HDL well, you should start with a mental > picture of your logic in mind. Then describe that circuit with VHDL. A > common trap for software types is to treat VHDL as a programming language > rather than as a hardware description language. The difference is with the > former, the hardware is forced to fit a software construct and in the latter > the hardware is expressed with the software. The easiest way to learn a new "programming language" is to look at example code. Now for my question: I am strictly a schematic user for now, for no other reason than when I started my current project, I knew nothing about FPGAs. Schematic capture seemed a quicker and easier way to begin playing with FPGAs, and I haven't finished the project yet, so no time to start learning VHDL, although I have read a couple books on it. OK, no for my question: using Xilinx Foundation, is it possible to translate my entire schematic design into one large VHDL file? thanks adrianArticle: 46036
> -----Original Message-----
> From: John Williams [mailto:j2.williams@qut.edu.au]
> Posted At: 15 August 2002 01:01
> Posted To: fpga
> Conversation: Modelsim VHDL problem
> Subject: Modelsim VHDL problem
>
>
> Hi folks,
>
> Sorry this is not strictly FPGA related, but I've already tried in
> comp.lang.vhdl and had no luck. I've also emailed xilinx
> support but am
> waiting for a reply.
>
> In a testbench I'm trying to define the following procedure:
>
> procedure ReadBand(file datafile : TEXT;
> signal band_sig : out std_logic_vector) is
> variable l_in : line;
> variable temp : std_logic_vector(31 downto 0);
> begin
> -- read the input file and assign to the signal
> readline (datafile,l_in);
> hread(l_in,temp);
> band_sig <=3D temp(band_sig'high downto band_sig'low);
> end procedure;
>
> The basic idea being to read a value from a file and put it
> on a signal.
>
> I looked at Modelsim's version of textio.vhd to get hints on
> the syntax
> of the declaration, but it doesn't like it:
>
The following file works for me!
Note: you MUST use VHDL 93 for FILE parameters to work!
I didn't use hread as I couldn't remember the text format,
but I've compiled the following and it works fine.
e.g.
vcom -93 fileparam.vhd
vsim e
run -all
--------------------------------------------------------------
library ieee;
use std.textio.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_1164.all;
entity e is
end;
architecture a of e is
procedure ReadBand(file datafile : TEXT;
signal band_sig : out std_logic_vector) is
variable l_in : line;
variable temp : std_logic_vector(31 downto 0);
begin
-- read the input file and assign to the signal
readline (datafile,l_in);
read(l_in,temp);
band_sig <=3D temp(band_sig'high downto band_sig'low);
end procedure;
signal s : std_logic_vector(31 downto 0);
begin
process
file F :TEXT open READ_MODE is "test.txt";
variable L : LINE;
begin
while not ENDFILE(F) loop
ReadBand(F, s);
wait for 0 ns; -- delta for s to get assigned
write(L,s);
writeline(OUTPUT,L);
end loop;
wait;
end process;
end architecture;
> # ERROR: C:/projects/IEICE/tb_acca_pass1.vhd(18): near "file":
> expecting: IDENTIFIER
>
> I am using all the right packages, (std.textio.all and
> ieee.std_logic_textio.all), and I regularly use files in testbenches
> without any problems. It's just the act of passing a file as a
> parameter to a procuedre that is not working.
>
> What am I doing wrong?
>
> Thanks in advance,
>
> John
>
Article: 46037
I think vhdl 87 supports FILE type, too.
In vhdl 87, you can declare like
file datafile : text is in "path/your_file_name";
--in means read while using out means write
while in vhdl 93, it is
file datafile : text open read_mode "path/your_file_name";
--write_mode and append_mode also
just like what Mr. Alan Fitch told.
Best regards,
phile
"Alan Fitch" <alan.fitch@doulos.com> wrote in message
news:drNwpTDRCHA.3628@lucy.doulos.com...
> -----Original Message-----
> From: John Williams [mailto:j2.williams@qut.edu.au]
> Posted At: 15 August 2002 01:01
> Posted To: fpga
> Conversation: Modelsim VHDL problem
> Subject: Modelsim VHDL problem
>
>
> Hi folks,
>
> Sorry this is not strictly FPGA related, but I've already tried in
> comp.lang.vhdl and had no luck. I've also emailed xilinx
> support but am
> waiting for a reply.
>
> In a testbench I'm trying to define the following procedure:
>
> procedure ReadBand(file datafile : TEXT;
> signal band_sig : out std_logic_vector) is
> variable l_in : line;
> variable temp : std_logic_vector(31 downto 0);
> begin
> -- read the input file and assign to the signal
> readline (datafile,l_in);
> hread(l_in,temp);
> band_sig <= temp(band_sig'high downto band_sig'low);
> end procedure;
>
> The basic idea being to read a value from a file and put it
> on a signal.
>
> I looked at Modelsim's version of textio.vhd to get hints on
> the syntax
> of the declaration, but it doesn't like it:
>
The following file works for me!
Note: you MUST use VHDL 93 for FILE parameters to work!
I didn't use hread as I couldn't remember the text format,
but I've compiled the following and it works fine.
e.g.
vcom -93 fileparam.vhd
vsim e
run -all
--------------------------------------------------------------
library ieee;
use std.textio.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_1164.all;
entity e is
end;
architecture a of e is
procedure ReadBand(file datafile : TEXT;
signal band_sig : out std_logic_vector) is
variable l_in : line;
variable temp : std_logic_vector(31 downto 0);
begin
-- read the input file and assign to the signal
readline (datafile,l_in);
read(l_in,temp);
band_sig <= temp(band_sig'high downto band_sig'low);
end procedure;
signal s : std_logic_vector(31 downto 0);
begin
process
file F :TEXT open READ_MODE is "test.txt";
variable L : LINE;
begin
while not ENDFILE(F) loop
ReadBand(F, s);
wait for 0 ns; -- delta for s to get assigned
write(L,s);
writeline(OUTPUT,L);
end loop;
wait;
end process;
end architecture;
> # ERROR: C:/projects/IEICE/tb_acca_pass1.vhd(18): near "file":
> expecting: IDENTIFIER
>
> I am using all the right packages, (std.textio.all and
> ieee.std_logic_textio.all), and I regularly use files in testbenches
> without any problems. It's just the act of passing a file as a
> parameter to a procuedre that is not working.
>
> What am I doing wrong?
>
> Thanks in advance,
>
> John
>
Article: 46038"Noddy" <g9731642@campus.ru.ac.za> wrote in message news:1029399196.246254@turtle.ru.ac.za... > > The easiest way to learn a new "programming language" is to look at example > code. Now for my question: I am strictly a schematic user for now, for no > other reason than when I started my current project, I knew nothing about > FPGAs. Schematic capture seemed a quicker and easier way to begin playing > with FPGAs, and I haven't finished the project yet, so no time to start > learning VHDL, although I have read a couple books on it. OK, no for my > question: using Xilinx Foundation, is it possible to translate my entire > schematic design into one large VHDL file? You could take one of your schematic subsystems and translate it into VHDL. Check that it works, create a symbol from it, add it to the schematic, and go on to the next. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 46039
> -----Original Message----- > From: phile [mailto:philewar@icc.sh.cn] > Posted At: 15 August 2002 10:10 > Posted To: fpga > Conversation: Modelsim VHDL problem > Subject: Re: Modelsim VHDL problem > > > I think vhdl 87 supports FILE type, too. > > In vhdl 87, you can declare like > file datafile : text is in "path/your_file_name"; > --in means read while using out means write > while in vhdl 93, it is > file datafile : text open read_mode "path/your_file_name"; > --write_mode and append_mode also > just like what Mr. Alan Fitch told. > Just to clarify what I was saying - yes files do indeed work in both VHDL 87 and VHDL93, with different syntax. The point I was making is that in VHDL87 parameters to procedures could be of three classes variable constant signal In VHDL93 there are four classes file variable constant signal In VHDL 93 if you want to pass a file to a procedure, you declare the procedure parameter to be of class file. In VHDL 87, if you want to pass a file to a procedure, you declare the procedure parameter to be of class variable. kind regards Alan <snip> >Article: 46040
Hi, I'm programming a XC2S150 Spartan FPGA with Xilinx ISE - Software in VHDL without using an external Reset-Pin. My question is: How do I describe in VHDL the starting values of a component after configuration, without using an external Reset-Pin. I only know that after configuration all Flip-Flops will be set to logic '0'. But, how can I tell the Synthesis-Tool - to Set or Reset a Flip-Flop after configuration? - in which state a statemachine starts after configuration, when I'm using one-hot-coding? Or does someone know an interesting Webpage on the internet, where this problem is described? Thank in advance Heiko TimmerArticle: 46041
maimuna wrote:
>
> the width of the array which i have used in my program changes with some inputs.
> is there any way to set the width of the array according to the inputs.
> if so please tell me
I don't believe there is directly. Remember that your array is
implemented as hardware; once your chip is programmed, it can't change
itself on the fly based on inputs.
There are ways you can get around the problem though. What you can try
is to make the array the maximum size, and then use a case statement to
determine which bits of the array are valid based on the value of your
inputs. For example, say your array was a shift register and you wanted
to do a parity calculation:
reg [7:0] array;
reg [1:0] array_size;
reg parity;
case (array_size)
2'b00: parity <= ^array[1:0]; // 2-bit array size
2'b01: parity <= ^array[3:0]; // 4-bit array size
2'b10: parity <= ^array[5:0]; // 6-bit array size
2'b11: parity <= ^array[7:0]; // 8-bit array size
endcase
Or alternatively:
reg [7:0] array2;
case (array_size)
2'b00: array2 <= {6'h0,array[1:0]}; // 2-bit array size
2'b01: array2 <= {4'h0,array[3:0]}; // 4-bit array size
2'b10: array2 <= {2'h0,array[5:0]}; // 6-bit array size
2'b11: array2 <= array[7:0]; // 8-bit array size
endcase
parity <= ^array2;
Hope this helps,
Pete
--
Peter Young
Hardware Designer
AMIRIX Systems - Halifax, N.S.
http://www.amirix.com
(remove spam block in reply address to send me e-mail)
Article: 46042Hellow! I want generate pulse when detect rising_edge of specific signal, and supply this pulse to enother box and execute command due to this pulse & after off some flag & wait to next rising_edge. Note: the 2 boxes (detect rising_edge and execute command) are use with different sync. (in VHDL) Thanks in advance!!!Article: 46043
Hi, there, As you know, Phillips hold the patent of I2C bus. But I also found somewhere said many of these patents had expired. However I still wondered if I design an I2C interface on my FPGA/CPLD chip and use this chip only in my system, do I have to buy their license? The designed FPGA/CPLD chip itself will not be a commercial product but this system will be. Thanks a lot. DavidArticle: 46044
> Viewlogic is not really supported by Xilinx anymore... Hi Ray, Would you mind clarifying what you mean by "really" please? Regards, AustinArticle: 46045
Xilinx no longer generates a viewlogic library, no will its
hotline help you out if you have issues with using viewlogic.
You can still generate an edif netlist with viewlogic, but you
will need to do something for the library if you plan to
simulate within viewlogic. Show me where to get a VL library
for the current Xilinx primitives if I am wrong.
Austin Franklin wrote:
> > Viewlogic is not really supported by Xilinx anymore...
>
> Hi Ray,
>
> Would you mind clarifying what you mean by "really" please?
>
> Regards,
>
> Austin
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin,
1759
Article: 46047Please realize that not "all Flip-Flops will be set to logic '0' " but all FD, FDR, FDRS primitives and the enabled cousins will be set to logic '0' unless specifically initialized otherwise. FDS and FDSE primitives will be set to logic '1' and cause you problems where you expect a zero power-up. The Xilinx devices have an internal reset signal that can be used in place of an external reset allowing all the flops to be explicitly initialized in your code. Without these explicit initializations, the normal initialization state can be overridden with the Xilinx INIT=S or INIT=R constraint. How to work those into your VHDL is, I believe, very dependent on your synthesizer. Take a look in the Xilinx libraries guide in the online sw documentation for the ROC primitive. This might be the right element for getting a signal that's "reset on configuration" but if I'm wrong (I haven't used it yet) there should be pointers to the other initialization related primitives there. Heiko Timmer wrote: > Hi, > > I'm programming a XC2S150 Spartan FPGA with Xilinx ISE - Software in VHDL > without using an external Reset-Pin. > > My question is: How do I describe in VHDL the starting values of a component > after configuration, without using an external Reset-Pin. I only know that > after configuration all Flip-Flops will be set to logic '0'. But, how can I > tell the Synthesis-Tool > > - to Set or Reset a Flip-Flop after configuration? > - in which state a statemachine starts after configuration, when I'm using > one-hot-coding? > > Or does someone know an interesting Webpage on the internet, where this > problem is described? > > Thank in advance > Heiko TimmerArticle: 46048
Hi all, I have a problem generating a programming file for my latest Verilog code. The mapper says that I have an illegal LOC. The pin N2 is connected to a 50-pin header on my SpartanIIe test board. Do you see anything wrong in this? The error message: Release 4.2WP0.x - Map E.35 Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved. Using target part "2s300efg456-6". ERROR:MapLib:93 - Illegal LOC on symbol "clk_sd" (pad signal=clk_sd) or BUFGP symbol "clk_sd_BUFGP" (output signal=clk_sd_BUFGP), IPAD-IBUFG should only be LOCed to GCLKIOB site. >From the ucf file: # # NET "clk_sd" LOC = "N2"; NET "clk_100" LOC = "AB12"; NET "din_sd" LOC = "M2"; NET "reset_local" LOC = "D8"; NET "transmitting" LOC = "F1"; >From the v file: module bit_transfer (clk_100, reset_local, din_sd, clk_sd, parallel_out, par_msb, transmitting); input clk_100; // 100MHz clock input reset_local; // a local reset button input din_sd; // bitstream data input input clk_sd; // bitstream clock. output [7:0] parallel_out; // output to send to parallel port output par_msb; // are we currently sending a most significant byte? output transmitting; // positive flank for valid outdata reg [7:0] parallel_out; reg par_msb; reg transmitting; ... always @(negedge clk_sd or negedge reset_local) // sigma-delta data is valid at negative clock edge begin ... end Thanks, BørgeArticle: 46049
What I did when I started working on FPGAs (which is not such a long time ago, as you can see from my newbie postings) was to get a SpartanIIe-300 board from Insight Memec. I also started learning Verilog. The board works like a charm (make sure you get version 1.3 of the documentation!). It has some leds and dips and stuff. Starting on Verilog was just like learning any new programming language, but the WebPack came with a learning curve of its own. I've done analog stuff with schematic entry before, but I think Verilog makes more sense for digital electronics. Here is the tiny little link to the Memec Xilinx boards page. Have a look at the Spartan series kits. http://www.insight.na.memec.com/cgi-bin/bvutf8/memec/scripts/local/mc_loc_a6 .jsp?catPath=/INSIGHT/AMERICAS/UNITED_STATES/MANUFACTURERS/XILINX/EVALUATION _KITS&Manu=XILINX&Div=INSIGHT&Reg=AMERICAS&Country=UNITED_STATES&Lang=EN Regards, Børge
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