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The problem is synplicity has a bad habit of putting combinatorial logic in
the clock enable path, which then has to be placed in a lut other than the
one associated with the flip-flop. The Xilinx auto place and route does an
exceptionally poor job at placing LUTs that are not associated with the D
input to a flip-flop (often times placing it a dozen ormore rows/cols away
even though all the input and output to the LUT is local to the flip-flop.
Floorplanning is difficult in that case too because the name of the LUT
changes from synthesis run to run. In many cases, one can get an equivalent
function that behaves much nicer if the enable is not used. Synchronous
set-reset flip=flops are an example where this happens frequently.
As indicated yesterday, synplify 7.0 and later has the useenables attribute
that can control the inference of the clock enables. Earlier versions could
be forced by using a syn_keep on the LUT output that goes to the FF_D input,
although that is a bit more of a pain to code.
Mike Treseler wrote:
> Nicholas C. Weaver wrote:
>
> > Thanks. Although this is what we are already doing, the CEs are being
> > added/inferred by symplify's mapping process.
>
> That may be because the primitive logic elements have clock enables.
> Consider letting the synth handle the unused inputs rather
> than forcing attributes or editing the netlist.
>
> -- Mike Treseler
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46001hmurray@suespammers.org (Hal Murray) writes: > I wouldn't call the BIT file > "compressed", just a better encoding. Yes. Binary instead of ASCII. > You can do better > still if you do real compression. Yes. Massively (for XCV300): neil@chonsp 0:53:44 ~> ls -al pdp10.bit -rw-r--r-- 1 neil franklin 219047 Jul 10 15:20 pdp10.bit neil@chonsp 0:53:51 ~> gzip pdp10.bit neil@chonsp 0:53:55 ~> ls -al pdp10.bit.gz -rw-r--r-- 1 neil franklin 21243 Jul 10 15:20 pdp10.bit.gz neil@chonsp 0:53:57 ~> It is seldom to see files compress by factor 10. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - Make your code truely free: put it into the public domainArticle: 46002
There is a pipelined divider core in the coregen. I don't know if it has a
matching s file that would make it usable in the coregen or not.
mikest wrote:
> Hello,
>
> I was wondering if anyone has tried the Xilinx System generator blockset
> and can provide assistance in building a divider block. It doesn't have
> one and I could use it. I know that a divider is basically a shift and a
> subtraction and I am trying to put one together. Let me know if there is
> one already.
>
> Thank You
> Mike
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46003
He was asking about inferred RAM, not instantiated RAM. I am not aware of any
synthesis that will allow the RAM contents of inferred RAM to be specified out
on the market yet, but things are changing fairly fast, so there may be
something now. Personally, I prefer to instantiate the RAMs because then I can
init them as well as place them in my code.
"M. Randelzhofer" wrote:
> I think the syntax is the same for fpga express and xilinx XST
>
> here is an example of a spartan2 fpga express bram (as rom) initialisation:
>
> -- braminst example start
> architecture braminst_arch of braminst is
>
> -- dualported ram component declaration, each port has 4bit width
> component RAMB4_S4_S4 port (
> WEA,WEB,ENA,ENB,RSTA,RSTB,CLKA,CLKB: in std_logic ;
> DIA: in std_logic_vector(3 downto 0) ;
> ADDRA: in std_logic_vector(9 downto 0) ;
> DOA: out std_logic_vector(3 downto 0) ;
> DIB: in std_logic_vector(3 downto 0) ;
> ADDRB: in std_logic_vector(9 downto 0) ;
> DOB: out std_logic_vector(3 downto 0)
> ) ;
> end component;
>
> attribute INIT: string ;
> attribute INIT_00: string;
> attribute INIT_01: string;
> attribute INIT_02: string;
> attribute INIT_03: string;
> attribute INIT_04: string;
> attribute INIT_05: string;
> attribute INIT_06: string;
> attribute INIT_07: string;
> attribute INIT_08: string;
> attribute INIT_09: string;
> attribute INIT_0a: string;
> attribute INIT_0b: string;
> attribute INIT_0c: string;
> attribute INIT_0d: string;
> attribute INIT_0e: string;
> attribute INIT_0f: string;
>
> -- first bram
> attribute INIT_00 of DP_VRM0: label is
> "d56c13e08101012c1180688012282170ee1ff30f811760000000000000000000";
> attribute INIT_01 of DP_VRM0: label is
> "3d25291f27101f1d7861d06261105ea2d3aa2d3daa2d3d050959232b81351200";
> attribute INIT_02 of DP_VRM0: label is
> "0fd00cacaa41c5d43caaa53dc5aaa9281d0c5dcaa41dcaad1e2aaa1d0c5d0d1d";
> attribute INIT_03 of DP_VRM0: label is
> "daa105940b2c113424140402313261599f0a31213211710d23435883d4af2219";
> attribute INIT_04 of DP_VRM0: label is
> "302313261599f0f31213211710d23435883d4af22190c222113a43da83d54883";
> attribute INIT_05 of DP_VRM0: label is
> "fe8a016015442435392fedc1ba98074831211109910446c1131215211910d234";
> attribute INIT_06 of DP_VRM0: label is
> "a4dd1140db03b8543732f0438c96fedc9d801b42e64138072627604f8b62904f";
> attribute INIT_07 of DP_VRM0: label is
> "08515a1a2c3e38d89cd912d8ba508cdb03c183150dc7d1d06cdd0140cc1c13cd";
> attribute INIT_08 of DP_VRM0: label is
> "41605f6c5d6654893448230d0d8092c007170f43fd402c12841d27404d818888";
> attribute INIT_09 of DP_VRM0: label is
> "3f410608354610235121d1f02150410b14220d41bc66ffdb211f00504455656d";
> attribute INIT_0a of DP_VRM0: label is
> "222d44f125140122c435175afd973636f594271e430631111188b303d6533709";
> attribute INIT_0b of DP_VRM0: label is
> "0201020101f60da6010342d2df66d21b6b111007221c24606065b61537c87535";
> attribute INIT_0c of DP_VRM0: label is
> "a98ae10fd300100052547704fbb010fd5d05010c010c0101f62ea70103511101";
> attribute INIT_0d of DP_VRM0: label is
> "0000000000000000000000000000000000000000000000000000000000000000";
> attribute INIT_0e of DP_VRM0: label is
> "0000000000000000000000000000000000000000000000000000000000000000";
> attribute INIT_0f of DP_VRM0: label is
> "0000000000000000000000000000000000000000000000000000000000000000";
>
> -- second bram
> attribute INIT_00 of DP_VRM1: label is
> "1f14f5f4ff5f7fff01aa4d0cf5047f0411d110c1014ffafdddddddddddddddd0";
> attribute INIT_01 of DP_VRM1: label is
> "a5a0c0c0c2c1051a414d6d5c7c0195e0949e08499e0249018bbc4504ff7fffdd";
> attribute INIT_02 of DP_VRM1: label is
> "a32c0b7b470cb070cb44704eb05671c0c4ab07b4704eb755a2c640c4ab04a6a7";
> attribute INIT_03 of DP_VRM1: label is
> "bba00bc4d40801b3b3b3b3aaaa0c0c1aa49ea1a11ca11ca90cdf1aa4a00fa04f";
> attribute INIT_04 of DP_VRM1: label is
> "faaaa0c0c1aa493a1a11ca11ca90cdf1aa4a22fa04fa60c2c44944994491abb4";
> attribute INIT_05 of DP_VRM1: label is
> "fff4d939f3f304304f3000030000330101010108e4898a801b1b10cb10cb90cd";
> attribute INIT_06 of DP_VRM1: label is
> "05b148430b30412465504111f71d11111004d04d04d14d2f9504764f24f9fe45";
> attribute INIT_07 of DP_VRM1: label is
> "1c1111b115714104047e51011115047043c1114ea01c11140470b01f11114147";
> attribute INIT_08 of DP_VRM1: label is
> "0c0414a710abbb0404a6a046aff1f14d011101114a4104111e78070b18b8bb91";
> attribute INIT_09 of DP_VRM1: label is
> "4da101150cd04150cd1621411baba911c0c6100c0c24045245524504babab1a0";
> attribute INIT_0a of DP_VRM1: label is
> "4162d1411abab9dbd041d0004524045a2404504d11d8df7f5f040cd18a0c1151";
> attribute INIT_0b of DP_VRM1: label is
> "702120313c48a40411114121142ad04def01112da0404aa0a019811d04dc04d0";
> attribute INIT_0c of DP_VRM1: label is
> "fff754248209190fc0beecf1fab2144ee0d171712121313c48a4041111411171";
> attribute INIT_0d of DP_VRM1: label is
> "0000000000000000000000000000000000000000000000000000000000000777";
> attribute INIT_0e of DP_VRM1: label is
> "0000000000000000000000000000000000000000000000000000000000000000";
> attribute INIT_0f of DP_VRM1: label is
> "0000000000000000000000000000000000000000000000000000000000000000";
>
> etc....
>
> begin
>
> -- bram instatiation example
> DP_VRM0:RAMB4_S4_S4 port map (
> WEA => LS, WEB => LS, ENA => HS, ENB => HS, RSTA => LS, RSTB => LS, CLKA =>
> m49, CLKB => m49,
> DIA => up_di0(3 downto 0), ADDRA => up_ada, DOA => up_do0(3 downto 0),
> DIB => vr_di0(3 downto 0), ADDRB => pcjmp(9 downto 0), DOB => vr_do0(3
> downto 0) ) ;
>
> DP_VRM1:RAMB4_S4_S4 port map (
> WEA => LS, WEB => LS, ENA => HS, ENB => HS, RSTA => LS, RSTB => LS, CLKA =>
> m49, CLKB => m49,
> DIA => up_di0(7 downto 4), ADDRA => up_ada, DOA => up_do0(7 downto 4),
> DIB => vr_di0(7 downto 4), ADDRB => pcjmp(9 downto 0), DOB => vr_do0(7
> downto 4) ) ;
>
> etc....
>
> end braminst_arch;
>
> MIKE
>
> "Kolja Sulimma" <kolja@bnl.gov> schrieb im Newsbeitrag
> news:25c81abf.0208130156.679ce799@posting.google.com...
> > Hi!
> >
> > For a SOC I use both ROMs made of Block-RAMs and dual-ported
> > Block-RAMs that are preloaded at reset.
> > Currently I use CoreGen to generate these building blocks.
> >
> > I use Xilinx Foundation 4.1i XST and would much prefer to use inferred
> > Block-RAMs. I know the Language Assistant VHDL examples for inferring
> > Block-RAM, but they do not show how to preinitialize the RAMs.
> >
> > Any ideas?
> >
> > Kolja Sulimma
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46004
For devices without a GBit serdes, you'll need to bring the clock in at half
rate and treat the data as DDS data. You can't get the raw clock in reliably at
full rate. The newer chips with the DDS IOBs make this easier too, since they
have two registers right at the IOB. We were working with a VirtexE-7, and
found that 1) none of the I/O standards on the FPGA matched the I/O of the ADC,
2) getting the data in as DDR data was tricky because one of the flip-flops had
to be inside the FPGA. WHen you add up the clock jitter, the DLL jitter, and
variances in the data paths, it becomes very hard to get 500 Mhz inputs. 500
MHz is reachable with extreme care in a part without DDR iobs, but is by no
means trivial. YOu might refer to some of the LVDS appnotes on both the xilinx
and altera websites. The big problem is simply one of reliable clocking and
limited bandwidth of the IOBs. Once inside it is often fairly trivial to break
it down into parallel words to get to whatever data rate is comfortable.
Pete Ormsby wrote:
> I'm not quite understanding the difficulty of using an FPGA for unloading
> this ADC. The ADC's two 8-bit buses with a forwarded clock at 500 MHz
> aren't too much different from the physical layer specs of some of the new
> I/O standards like RapidIO or HyperTransport. There are several of these
> cores implemented in FPGAs from more than one FPGA vendor, so it's got to be
> at least do-able.
>
> I can't speak to the ease/difficulty of implementing this in a Xilinx
> device, but it's pretty straight-forward in any Altera device since the Apex
> 20KE. Each data line comes into the FPGA at, say, 500 MHz and goes into
> it's own SerDes. The SerDes output is 8-bits wide at 62.5 MHz, essentially
> making a 64-bit word when you line then all up. Since the data sample
> values are now spread out across the eight 8-bit words, you'll need to
> shuffle the bits around to put bits 0,8,16,24,32,40,48,56 together for one
> sample, 1,9,17,25,33,41,49,57 for the next, etc. However, since you're
> working at 62.5 MHz at this point, the shuffling isn't rocket-science.
>
> -Pete-
>
> Ray Andraka <ray@andraka.com> wrote in message
> news:3D557628.59972223@andraka.com...
> > The LVDS specs on some of the faster chips will handle that, but the
> > internal design just to get the data reliably onto the chip is not
> > trivial, and involves treating the data as DDR data. VirtexII would make
> > this easier for you, but still a major PITA to pull it off. We did a
> > similar design earlier this year with an Atmel 8 bit 1GS/sec converter
> > plus a sister chip (also Atmel) that packed 4 samples into one 32 bit
> > word and transferred that at a much more manageble 240 MHz into a virtexE
> > over LVDS lines. That was a lot easier than trying to run at the hairy
> > edge using interface specs that were not directly compatible.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46005Hello all I am a greenhorn in this area and i was wondering if anyone could help me on the issue of testing the X2S USB board. what would be the quickest way of verifying pin functions? please i'd be very grateful for any help on this. Thanks Sani AbachaArticle: 46006
Dear Sam, Thank you for your reply. ^_^ Reala <samg@codenet.net> wrote in message news:3d591934.1310965@news.newsguy.com... > The previous poster was dead on about the costs of an ASIC and I wish > to add one more thing that is an issue. > > Much of the FPGA IP people buy from Xilinx is already compiled and in > bitstream form and relatively cheap! The thing is, Xilinx did not > intend you to take this stuff to ASIC behind their backs. If you > check your license agreements, I believe that it mentions something > about that. So be carefull if you are using an Asian conversion > company to reverse engineer that Xilinx IP to standard cell logic > gates in order to save a buck. Digital signatures can still be > implanted into the IP and if your ASIC is very profitable, someone > might do some reverse engineering on your product and then want > royalties on it which might not make it so profitable anymore. > > I am not trying to scare anyone and I am not employed or connected > with Xilinx in any way, just read your license agreement and keep > everthing legal. The FPGA industry does a LOT of subsidizing to get > you your cheap tools and stuff, but when you go to make an ASIC, all > bets are off and the price can skyrocket. > And you don't want to do anything illegal in chip design realm because > it always seems like the legal "Hammer of God" can come out of nowhere > when you least expect it. > (Just look at the money spent in lawsuits between the EDA companies > and even the FPGA companies over disputes!) > > The good news is that many of the FPGA companies can help out in some > areas of turning big projects into an ASIC through partners such as > Xilinx/IBM for the Power PC embeded stuff. > > Sam > > On Tue, 13 Aug 2002 06:36:47 GMT, spam_hater_7@email.com (Spam Hater) > wrote: > > >Reala, > > > >For the library, you have to contact the fabrication house and find > >out which ones they have certified. > > > >For example, with TSMC or UMC, you can use Artisan or Virtual Silicon. > >There are dozens of FAB houses, and dozens of library makers. > > > >For synthesis, you can use Synplicity, Synopsys, or Ambit. There's > >probably more; those are the ones I have used. Just make sure the > >library has support. > > > >It's a 3-piece puzzle, that involves substantial time to solve. This > >is a non-trivial task. It takes work. No sane person is going to do > >this much work for free; serious money is usually involved. > > > >And you're probably unaware of the costs involved. I can put together > >a decent FPGA development station for $1,300.00 - that includes the > >prototype board and all the software. (Actually, you can build a > >Cypress development station, including HDL, for under $500.) > > > >The last ASIC I did, we used $2,000,000.00 worth of layout software, > >simulators, and synthesizers. And the 1st chip run cost $250,000.00 > > > >The FPGA maker makes their money on the chips; they practically give > >the software away. > > > >Yes, there are cheaper ways to do it. Take a class in ASIC design at > >a local university, and see how they do student runs. > > > >SH7 > > > >On Tue, 13 Aug 2002 14:11:55 +0800, "Reala" > ><manfield.chow@scoreconcept.com> wrote: > > > >>Hi SH7, > >> > >>Thank you for your reply. > >>Yes, the questions are similar. > >>I ask this question again because I find that the free systhesis tools > >>always target to FPGA. > >>If I design the chip by FPGA, then I change it to ASIC. I can find some > >>vender to help me for conversion. > >>However, if I want to design the chip directly. I guess that it is something > >>difficult. > >>(eg. what systhesis tools i can you? As the target is not a FPGA, what > >>library used for systhesis?) > >> > >>Reala > >> > >> > >>"Spam Hater" <spam_hater_7@email.com> wrote in message > >>news:3d57e652.6164760@64.164.98.7... > >>> > >>> Hi, > >>> > >>> You asked this same question on 07/22/2002 > >>> > >>> What's wrong with the answers you got then? > >>> > >>> SH7 > >>> > >>> > >>> > >>> On Mon, 12 Aug 2002 11:32:31 +0800, "Reala" > >>> <manfield.chow@scoreconcept.com> wrote: > >>> > >>> >Hi, > >>> > > >>> >I wrote a verilog code. Then, I ran Modelsim to verify the design. > >>> >If I implement the design by Altera, I can use LeonardaSpectrum for > >>> >synthesis. > >>> >However, i want to implement the design by ASIC. What > >>> >information/software/library needed for this approach? Thank you. > >>> > > >>> >Reala > >>> > > >>> > > >>> > > >>> > > >>> > > >>> > >> > >> > >> > >> > > >Article: 46007
If there's enough space left in the FPGA, you can put in two applications by using one bit to control a set of MUXes to select which one is active. Or, have more selection bits and put in more applications. "Ramakrishnan" <rxv20@po.cwru.edu> wrote in message news:15cf85fc.0208130701.67480ed3@posting.google.com... > Hi, > So basically u r saying is that , it is not possible to implement > two applications without downloading them seperately one after the > other, that basically means , it is kind of impossible to reconfigure > dynamically to switch to other application at run time. > > Thanks, > > Ram. > > "reply in the newsgroup" <deepfry.a.spammer.today@abuse.org> wrote in message news:<aj9mtc$beh$1@slb6.atl.mindspring.net>... > > Then you'll need a separate simulation for each configuation. > > I was assuming that you were using only one configuration, > > but not initializing all the sections in tests that weren't using > > them. > > > > "Ramakrishnan" <rxv20@po.cwru.edu> wrote in message > > news:15cf85fc.0208121403.b469915@posting.google.com... > > > Hi, > > > I really didn't understand what you meant in your post. Actually > > > the number of memories for each and every application varies in my > > > architecture, for example bandpass filter implementation required 12 > > > memories of 4 elememts whereas cosine filter needed only 10 memories. > > > > > > So every time a new application is to be implemented, the whole > > > architecture would have to some how be reset to reflect the exact > > > number of memories. > > > > > > Thanks, > > > > > > Ram. > > > > > > "reply in the newsgroup" <deepfry.a.spammer.today@abuse.org> wrote in > > message news:<aj8mlp$i87$1@slb7.atl.mindspring.net>... > > > > "Ramakrishnan" <rxv20@po.cwru.edu> wrote in message > > > > news:15cf85fc.0208120735.1884e326@posting.google.com... > > > > > Hi, > > > > > I have a few questions with regard to Xilinx 4000 series FPGA. > > > > > > > [deleted] > > > > > The problem i think would like in the fact that some of the > > > > > applications that i choose to implement would use fewer memories in my > > > > > VHDL architecture than others. So how would i be able to overcome this > > > > > problem. > > > > > > > > > Then why not create a file for each memory not used in all the tests, > > that > > > > loads this memory with random data, and use the resulting files to load > > any > > > > memory not used in the current test so that all the memories end up > > > > loaded?Article: 46008
Nicholas C. Weaver wrote: >>2) With the security bit set there is aboslutely no visibility into >>an anti-fuse part (this is permanent) > > A good probe technique should be able to create a break on the > security bits, probably more reliabily than a glitch attack on the > SRAM based security bits. > > That would be how I'd attack an antifuse setup: Reverse engineer > the part until I can determine the location of the readback lock > bits, then changed them by very fine drilling, probing, and > filling. Basically drill down to where I need to break [1], > backfill with insulator and conductor to restore any layers/vias > broken on the way in, and then use the readback mechanisms. I don't believe the Actel antifuse parts have a readback mechanism to simply read out the design. I don't recall what Quicklogic has. -- rk, Just an OldEngineer The ability to improve a design occurs primarily at the interfaces. This is also the prime location for screwing it up. -- from Akin's Laws of Spacecraft DesignArticle: 46009
> However, if I want to design the chip directly. I guess that it is
> something difficult.
Compared to FPGA, ASIC development is much more expensive. The tools
are more expensive, the NRE (non-recurring expense) are *FAR HIGHER*,
and the design-cycle (length of time from start to finish) is much
longer.
If you are *serious* about ASIC-development, your best bet is to
contact a design services company (esilicon.com, qthink.com,
flextronics.com, etc. there are many others) which specializes in
ASIC-development. These companies can give you an overview.
> (eg. what systhesis tools i can you? As the target is not a FPGA, what
> library used for systhesis?)
Synopsys's Design Compiler is the most popular ASIC synthesis tool.
Ironically, Synopsys's FPGA compiler (which Xilinx used to OEM in older
Foundation software) is falling behind Synplicity, Leonardo, etc.
As for the synthesis target ('technology library'), some foundries
give you a basic library at no cost. (I think TSMC licenses/pays
Artisan Components for its standard-cell portfolio.) "Advanced"
macroblocks (PLLs, high-speed I/O drivers, embedded memory arrays)
generally cost the customer extra $$$.
By the way, the 'synthesis' step is the least difficult part of
the ASIC development flow. The steps that come afterward get
more and more hairy!
Article: 46010
Hi, I have a design with to LVDS clocks and one LVTTL clock. (See below)
cta_ext>---DCM---BUFG--->MUX IN 0
MUX OUT ---->BUFG--tdm_clk_ext--FLIP FLOPS 1
ctb_ext>---DCM---BUFG--->MUX IN 1
cta_int>---DCM---BUFG--->MUX IN 0
MUX OUT --->BUFG--tdm_clk_int--FLIP FLOPS 2
ctb_int>---DCM---BUFG--->MUX IN 1
clk_ref>---BUFG---->FLIP FLOPS 3
How should I interpret the report below? (This is not the whole report)
Clock to Setup on destination clock ctb_int_n_lvds
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_ref | 15.472| | | |
cta_int_n_lvds | 9.256| | | |
cta_int_p_lvds | 9.256| | | |
ctb_int_n_lvds | 9.342| | | |
ctb_int_p_lvds | 9.256| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock ctb_int_p_lvds
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_ref | 15.686| | | |
cta_int_n_lvds | 9.785| | | |
cta_int_p_lvds | 9.256| | | |
ctb_int_n_lvds | 10.027| | | |
ctb_int_p_lvds | 9.342| | | |
---------------+---------+---------+---------+---------+
Regards
Hakon Lislebo
Article: 46011Hello, Im using The Altera Excalibur kit with APEX 20k and have the following problem regarding clocks. My Design uses two clocks, one for the NiOS module (33MHz) and one for my own module (VHDL, speed varies). It's really just a test on how to transfer data between asynchronous clock domains. The problem is that whenever I use the my module with a clock slower that 11MHz, the block won't work. Nothing seems to happen (I've checked a few signals with logic analyzer). Are there things to consider during synthesis when using clocks that are considerably slow? Im using Quartus II. Between 11MHz and 100MHz the design works fine... regards, -- JuzaArticle: 46012
Is the transputer still constructed and used today? Please send us the name of constructor and latest type of transputer. Thank you in advance!Article: 46013
ted wrote: > > I have a circuit with an Altera Max7128 CPLD. On the same board there > is a programming circuit using a 74HC244 (exactly as per ALTERA > byteblaster > specs). The whole thing connects to a parallel port on the PC, which > is > running the latest MAX IDE. Last i looked, the 'exact' specs omit the bypass capacitor across the 74HC244. Have you got one?Article: 46014
Erm, so they are working to specification (or even better depending on what you are doing) then! Take a look at the apex20k datasheet and look at the minimum and maximum allowed input clock speeds. Sorry to be the bearer of bad news. Paul "Lähteenmäki Jussi" <jusa@students.cc.tut.fi> wrote in message news:ajd879$6uk$1@news.cc.tut.fi... > Hello, > > Im using The Altera Excalibur kit with APEX 20k and have the following > problem regarding clocks. My Design uses two clocks, one for the NiOS > module (33MHz) and one for my own module (VHDL, speed varies). It's > really just a test on how to transfer data between asynchronous clock > domains. The problem is that whenever I use the my module with a clock > slower that 11MHz, the block won't work. Nothing seems to happen (I've > checked a few signals with logic analyzer). Are there things to consider > during synthesis when using clocks that are considerably slow? Im using > Quartus II. Between 11MHz and 100MHz the design works fine... > > regards, > -- > JuzaArticle: 46015
Is that internally generated or external clock? Matjaz "Lähteenmäki Jussi" <jusa@students.cc.tut.fi> wrote in message news:ajd879$6uk$1@news.cc.tut.fi... > Hello, > > Im using The Altera Excalibur kit with APEX 20k and have the following > problem regarding clocks. My Design uses two clocks, one for the NiOS > module (33MHz) and one for my own module (VHDL, speed varies). It's > really just a test on how to transfer data between asynchronous clock > domains. The problem is that whenever I use the my module with a clock > slower that 11MHz, the block won't work. Nothing seems to happen (I've > checked a few signals with logic analyzer). Are there things to consider > during synthesis when using clocks that are considerably slow? Im using > Quartus II. Between 11MHz and 100MHz the design works fine... > > regards, > -- > JuzaArticle: 46016
hello, I do remember Peter said one day in this group, that we have not to bother too much about line overloading. I mean when a path has a high fan out, as it happens when implementing the inverse structure of an FIR. This is due to the high routing buffering. i want to know from when can we assume that a long path has influence on the final processing speed. basically when implementing the inverted or the direct form of an FIR,what is (roughly) the filter length at which i should go for a specific structure. I am seeking basically speed design optimisation thanksArticle: 46017
<hypi@gmx.net> wrote in message news:3215928b.0208140333.3cc4957c@posting.google.com... > Is the transputer still constructed and used today? Please send us the > name of constructor and latest type of transputer. > > Thank you in advance! I think the last transputer was made about five years ago. I've got an unused development system a friend gave me. A couple of universities are making transputer-like systems with other CPUs. They are implementing the link engines in an FPGA. Leon -- Leon Heller, G1HSM leon_heller@hotmail.com http://www.geocities.com/leon_hellerArticle: 46018
thank you very much! "Joe Maloney" <joebird@xilinx.com> wrote in message news:3D583E91.29648D0@xilinx.com... > > > http://www.xilinx.com/esp/technologies/wireless_networks/bluetooth.htm > > Sleep Mode wrote: > > > > Hi there! > > > > I am involved with a project regarding bluetooth protocol stack and I want > > to move protocols of this stack to hardware (FPGA or even mController) -till > > now I only have some very very complicated implementations in C++. > > I am looking for references for such a task since I have little experience > > on the subject yet (how to transfer a protocol layer effectively in vhdl for > > instance). I also don't seem to find very explanatory details of the > > interface provided by the bluetooth stack so as to interconnect it correctly > > with hardware. > > If you have any knowledge of such hardware, sample codes or references > > please please tell me! > > > > HW rulez! :-)Article: 46019
Depends on which device family. VIrtex and VirtexE seem to be quite
sensitive to internal fanout. Virtex2 so far appears to be much better,
but what you gain there you give up in the carry chains, which are
considerably slower than the virtexE carry chains.
hristo wrote:
> hello,
>
> I do remember Peter said one day in this group, that we have not to
> bother too much about line overloading. I mean when a path has a high
> fan out, as it happens when implementing the inverse structure of an
> FIR. This is due to the high routing buffering.
>
> i want to know from when can we assume that a long path has influence
> on the final processing speed. basically when implementing the
> inverted or the direct form of an FIR,what is (roughly) the filter
> length at which i should go for a specific structure. I am seeking
> basically speed design optimisation
>
> thanks
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 46020Please see John Jakson's recent posting on T2 at http://groups.google.com/groups?selm=38111bbc.0208080412.4d310323%40posting. google.com, and also http://fpgacpu.org/log/dec01.html#011210. Jan Gray, Gray Research LLC FPGA CPU News: www.fpgacpu.orgArticle: 46021
thanks! i didn't have a clue about this site . . . "Joe Maloney" <joebird@xilinx.com> wrote in message news:3D583E91.29648D0@xilinx.com... > > > http://www.xilinx.com/esp/technologies/wireless_networks/bluetooth.htm > > Sleep Mode wrote: > > > > Hi there! > > > > I am involved with a project regarding bluetooth protocol stack and I want > > to move protocols of this stack to hardware (FPGA or even mController) -till > > now I only have some very very complicated implementations in C++. > > I am looking for references for such a task since I have little experience > > on the subject yet (how to transfer a protocol layer effectively in vhdl for > > instance). I also don't seem to find very explanatory details of the > > interface provided by the bluetooth stack so as to interconnect it correctly > > with hardware. > > If you have any knowledge of such hardware, sample codes or references > > please please tell me! > > > > HW rulez! :-)Article: 46022
Hi folks,
Sorry this is not strictly FPGA related, but I've already tried in
comp.lang.vhdl and had no luck. I've also emailed xilinx support but am
waiting for a reply.
In a testbench I'm trying to define the following procedure:
procedure ReadBand(file datafile : TEXT;
signal band_sig : out std_logic_vector) is
variable l_in : line;
variable temp : std_logic_vector(31 downto 0);
begin
-- read the input file and assign to the signal
readline (datafile,l_in);
hread(l_in,temp);
band_sig <= temp(band_sig'high downto band_sig'low);
end procedure;
The basic idea being to read a value from a file and put it on a signal.
I looked at Modelsim's version of textio.vhd to get hints on the syntax
of the declaration, but it doesn't like it:
# ERROR: C:/projects/IEICE/tb_acca_pass1.vhd(18): near "file":
expecting: IDENTIFIER
I am using all the right packages, (std.textio.all and
ieee.std_logic_textio.all), and I regularly use files in testbenches
without any problems. It's just the act of passing a file as a
parameter to a procuedre that is not working.
What am I doing wrong?
Thanks in advance,
John
Article: 46023I agree that systematic RS system will have the data portion unchanged but the parity section will screw up the Syndrome generators that are trying to determine if there is an error. The reason being that the GF math logic will be slightly different for 285 vs 301, right? Sam On Fri, 09 Aug 2002 23:05:01 -0500, Mike Rosing <rosing@neurophys.wisc.edu> wrote: >Igor wrote: >> I have Reed-Solomon decoder with polynom 391 (Intelsat standard), >> whether probably to transform a signal encoded with polynom 285 (DVB >> standard), and decode it by this decoder ? >> > >If there's no errors you can convert code words directly. If there's >errors to deal with, the math would get pretty hairy. So I'd guess >yes "in principle" it should be possible. > >Patience, persistence, truth, >Dr. mike > >-- >Mike Rosing >www.beastrider.com BeastRider, LLC >SHARC debug tools >Article: 46024
Back in university days, about three years ago, I had some fun designing a little 8 bit CPU. I used some version of Xilinx foundation and a X??4010XL board. Lately, I've wanted to design a larger CPU. 32 bit, caches, VM, etc. As of now, I have nothing. No board, no computer, no tools. Well, I have a Mac, but nobody writes CAD stuff for those. Also a 'scope. I found a nice board, Virtex 2 XC2V1000 and 32 megs of DDR SDRAM. About $1000. I'll get a 2.X GHz PC w/ 1G ram, $1500-2500. And some software... On my first CPU I used the schematic editor in Foundation. It worked well. I used a nice hierarchical design and I found it quite easy to keep an overall view of the project in my head. It seems to me that text is a good way to view software because software executes in a linear, one-at-a-time fashion. Hardware, on the other hand, executes everywhere at once. Though I admit I don't know verilog or vhdl, neither seems particulary intuitive or natural. It appears I need to purchase one of: - Xilinx Foundation $2500 - Xilinx Alliance $1500 + Third party schematic capture $?? I assume the Alliance package will do simulation and timing? Those seem to be post- place-n-route things. Correct? The old Xilinx tool I used in the university lab several years ago would be quite sufficient for this project. I understand that Xilinx may have replaced it with a not-so-good version recently? Also, I have heard a several people say that viewlogic is much better than the Xilinx Foundation schematic tool. How much $$ is it? It seems this project will end up costing $5-6k. Ugh. I write software for a living but it still hurts to pay >$2500 for a one-off project. I'd use the webpack it doesn't support large chips. Does anyone (Peter?) think Xilinx would give me a break for hobbyist project like this? Worth a try? -Ryan
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