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>Finally, even if you CAN use a tri-state bus with your current library >from vendor A, you might not use it in vendor B's design flow. Why >box yourself in??? But correspondingly, if you are not planning to switch to another vendor (or to an ASIC), then why not take advantage of all the tools that are available? It might save you switching to a faster or larger chip. I like tri-state busses. Maybe that's because I'm an old-fart and they were common in old (70s-80s) microcoded machines when I learned about hardware. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 43476
I was pretty excited when Xilinx announced the crossprobing feature, which allows you to click on a net/register in the Timing Analyzer and have it highlighted in Floorplanner, but I have to say I've been a little disappointed with the feature. Has anybody else noticed that it just doesn't work that well? On a large portion of the links it just doesn't work at all. You click on the net, and nothing is highlighted. Sometimes you click on a net and only the source is highlighted. If you click on the whole data path, usually only half of it gets highlighted. And sometimes the whole crossprobing feature just doesn't work unless I shut down the applications and restart. What's up? I've got 4.2.02i. -KevinArticle: 43477
Austin, > I have also stated that over time, we get better in our test coverage as we > hear from everyone who finds an occasional test escape, and fix the program. > How we actually accomplish what you state is impossible, is proprietary and > confidential (or already covered by patents, or in patents pending), Touchy on Monday morning, eh? I said "A complete test isn't practical." If Xilinx was doing a complete test, there would be no occasional test escapes, correct? We agree that there are test escapes. So Xilinx isn't doing a complete test. QED. As a mostly happy Xilinx customer, for my current application I'd rather reduce my odds of finding an occasional test escape. I know that this isn't free, and I know that my current application isn't anything close to the average. -- Phil HaysArticle: 43478
I need to develop a High-Speed buffer (1Gbps line speed) system using a Xilinx FPGA - currently I am looking at the Virtex-II family. The Max CLKIN/CLKOUT for a -5 grade chip is 420MHz. Q1. Is it possible to achieve 1Gbps on a serial input for this device? I have a feeling I cant - is this good hunch? Q2. What would be the max IO datarate achievable? 840Mbps using DDR? Q3. Is there a Xilinx FPGA capable of such serial datarates? Sorry for the scattered question, but I'm fed up with trolling through datasheets Thanks in advance for any help, Mitchell Crago mmccrraaggoo@@ffllooww.ccoomm.aauu __________________________________________________________________Article: 43479
In comp.lang.vhdl Austin Franklin <austin@dark98room.com> wrote: Yes, they are very efficient in FPGA designs, when the routing capacity is somewhat restricted. I was mainly talking about SOC designs, where you, nowadays, have all the routing you ever wanted. But when the bandwidth is an issue, you may want to use separate lines. Yet, one thing people seem to forget a lot in their wisdow is the fact that the designs should also work after they have been "produced". I guarantee, that using on-chip tri-stated buses will never give you 100% boundary-scan. This is not a problem with FPGAs, but it sure is with ASICs. On the other hand, it is a world of extreme experiences nowadays, so why not live on the edge :) regards, juza : So what if they are primarily used to interface to the outside world? That : is what a large number of designs do! : The internal tri-state busses in the Xilinx had some major advantages to : other methods. They did not take up logic resources...and weren't counted : in the "gate count". They were (far) faster than using a mux, if you had, : say, more than 4 connections. They also reduced the routing resources : substantially. All those could make or break a design!Article: 43480
I am using a XC2V250 for a project, and I'm trying to work out the expected configuration times. The only reference I have found to allow around 1mS per bit of the configuration stream. If this is true, it will take me around 28 minutes to configure the device. Is this true? If not, how long would one expect to load a design? Cheers Mitchell mmccrraaggoo@@ffllooww.ccoomm.aauu __________________________________________________________________Article: 43481
Ooops, must be time for a break - config is at 1uS per bit -> 1.7secs, damn I'm a goose sometimes. "Mitchell Crago" <mcrago@flow.com.au> wrote in message news:acfmta$kgu$1@lust.ihug.co.nz... > I am using a XC2V250 for a project, and I'm trying to work out the expected > configuration times. The only reference I have found to allow around 1mS per > bit of the configuration stream. If this is true, it will take me around 28 > minutes to configure the device. Is this true? If not, how long would one > expect to load a design? > > Cheers > > Mitchell > mmccrraaggoo@@ffllooww.ccoomm.aauu > __________________________________________________________________ > >Article: 43482
OK. An example. Suppose that I have a simulation with agents in it (agent-based simulation). The agents have relatively simple logic. Agent's algorithm complexity is not a problem here, but the problem here is the huge number of interactions between those agents. I suppose that you know what a multi-agent simulation is so I do not feel the need to write more about it. The number of agents is several thousands or more. The problem nowadays is that such simulations take a really long time to simulate. But the problem is inherently parallel - the algorithms of agents are executing in parallel from the point of view of an individual agent (you can think of such an agent as a human for example, the population of agents are people). The common solution nowadays is that we simulate that paralelism on sequential processors (like x86 or G4) and the result of course is that we have only several thousands of cycles per agent per second. This makes the simulation so slow. We cannot raise the number of agents to say 100000 because the simulation will simply "stop". A logical solution of the problem of parallel simulation would be to make the agents execute in parallel. We can use some programmable logic (PL) for this purpose - the agents could be simply "burned into" some hardware that executes the simulation. But such a PL should have enough memory and enough logic. John_H <johnhandwork@mail.com> wrote in message news:<3CEADC92.ADADB2D@mail.com>... > Addressing the front part of your recent post inline below: > > Help me understand, please... Is a "branch" not a selection between two > pieces of an algorithm? In my interpretation of a sequential code > algorithm, I would design my hardware not to send data to a different > piece of the silicon, but instead change how the data is modified through > a common path based on the branch condition; sometimes this > simplification won't hold and some silicon must sit idle while an > alternative path is used but it's often much less efficient. The > "operation units" sound like adders, shift right operators, logical ANDs > and other ALU style items. We deal with logical operations which are a > very different flavor in the operand and result widths as well as > implementation efficiencies. What operations should be designed in the > reconfigurable architecture to be most effective for universal algorithm > appeal? The "memory" is varied in the ability to manipulate it in > convenient and efficient forms now more than ever. We have logic tightly > coupled to registers - memory elements - and we have larger memory arrays > that can deal with kbits of storage. > I must appology for my english and the terms I use. The "branch" is of course a selection between two paths in algorithm execution, a physical implementation of if-then-else. The "operation units" are simply units that can perform some computation (they can be adders, shifters, ...). But I think that thinking in more abstract terms is essential, so I have done so. And please do not think of memory as registers, think of memory in general. > We have what we need. > Please tell me what we don't yet know we need. Sorry, but I must disagree with you - we dont have what we need. Let me explain it more precissely: an essential property of any innovation is that we are unable to imagine a use for it. A use for any innovation cannot be precissely determined in advance, it cannot be predicted (in case somebody thinks it is so he is a communist or fascist (I apologize if I have hurt someone's emotions)). The use for an innovation is in vast number of cases found AFTER its invention. Even the inventors are unable of imagine what will be their innovation used for. Von Neumann was not conscoius of the fact that we will use computers to play 3D games. The future is simply not predictable. The people that "encounter" an innovation will use the innovation for their own unique selfish purposes. Each of these people has his own unique memory and mind, so it is not a miracle that they will use the same thing for different purposes. If someone says that this kind of discussion is not a common one, I must admit that it is true. It is about what I need, and not about what exists. When I think of the start of the discussion, I must admit that I should rather start with the example of multi-agent simulation and not with abstract questions. I think that this discussion is interesting. If somebody thinks that this discussion cannot improve his overall knowledge, let me know please.Article: 43483
Russell wrote: > James Zaiter wrote: > > > > hi my name is james and my email is jzaiter@magnasys.com.au > > I am new to fgpa programming and need some direction in learning to programm > > these devices. > > I need help with software and development board preferably xilinx > > xc2000,xc3000 and xc4000 chips. > > is there any free software available to use for learning purposes only as i > > have a very small budget. > > any help would be much appreciated. > > james > > You can download xilinx webpack and make a jtag cable programmer. > If you can make good circuit boards, you can make and program > your own kit. You'll need to learn vhdl, verilog, or schematic > entry. It would also be best if you go straight to the modern - Virtex class - generation of FPGAs which are both bigger and cheaper than the one you mention. The largest SpartanIIE is only about US $60 in small quantities and WebPack has all you need to build logic for them. There's even a free edition of the powerful ModelSim logic simulator. Its hobbled in that it slows down for designs > 80K lines of code but that should be enough for your purposes. The other thing to consider is getting an FPGA eval board. Although they seem to be out of stock right now one of the cheapest ones with a good reputation can be found down under at: http://www.burched.com.au also try http://www.xess.com More serious & heavyweight are the Nallatech boards http://www.nallatech.com Finally, although I have absolutely no doubt I'll re-start one of the most common threads on the NG, go for one of the HDLs to start with, not schematics. Schems do have their place but IMO the amount of effort they require to handle large & complex designs gets in the the way of understanding the logic design. Schem design also means you don't have access to a simulator at source code level. HDLs require more initial investment of brain cycles but the rewards are great ... go HDL - you won't regret it. Which HDL you start with is a matter of choice and, once again, there is much vocal opinion [both heat and light] on this NG and comp.lang.verilog, comp.lang.vhdl about their respective merits and pitfalls. Verilog, for example, is much the easier of the 2 major ones to learn but has the dismerit of allowing you to make some very subtle and sophisticated mistakes very early on ... but then you are going to make 100s of such errors in your FPGA career anyway so you might as well get used to tearing your hair out while staring at simulator traces telling you that, yes you've screwed up again :-)). [Sees first flame on horizon and ducks back into trench].Article: 43484
Jan Ziak wrote: > > OK. An example. Suppose that I have a simulation with agents in it > (agent-based simulation). The agents have relatively simple logic. > Agent's algorithm complexity is not a problem here, but the problem > here is the huge number of interactions between those agents. I > suppose that you know what a multi-agent simulation is so I do not > feel the need to write more about it. > > The number of agents is several thousands or more. The problem > nowadays is that such simulations take a really long time to simulate. > But the problem is inherently parallel - the algorithms of agents are > executing in parallel from the point of view of an individual agent > (you can think of such an agent as a human for example, the population > of agents are people). The common solution nowadays is that we > simulate that paralelism on sequential processors (like x86 or G4) and > the result of course is that we have only several thousands of cycles > per agent per second. This makes the simulation so slow. We cannot > raise the number of agents to say 100000 because the simulation will > simply "stop". > > A logical solution of the problem of parallel simulation would be to > make the agents execute in parallel. We can use some programmable > logic (PL) for this purpose - the agents could be simply "burned into" > some hardware that executes the simulation. But such a PL should have > enough memory and enough logic. See the other thread on "Architecture for high-level reconfigurable computing", and also on Soft cores in general The FPGA fabric is flexible enough, that you in theory can build almost any mix of distributed, parallel processing you could desire. The challenge is in the SW to manage this, and I like the look of inherently parallel languages like ASML. http://www.research.microsoft.com/fse/asml/ >From earlier: > ASML is inherently parallel, until 'step' in invoked, and thus > the SAME source could potentially target an OpCode or FPGA at runtime. > > This from their overview: > > It is only after a step has been made that the new values > > become visible. > > In general, a computation in AsmL is not sequential unless > > explicitly marked as being so. Solve the software problems well enough, and you will start to 'steer' the Silicon developments :-) -jgArticle: 43485
Hi, I used a really cool and free (LGPL) soft cpu (LEON) on a Xilinx Virtex FPGA. Check out: http://www.gaisler.com/ LEON is a synthesisable VHDL model of a 32-bit SPARC compatible processor. A nice cross compilation system is also available with: # GNU C/C++ compiler (gcc-2.95.2) # Linker, assembler, archiver etc. (binutils-2.11) # Standalone C-library (newlib-1.8.2 from Cygnus) # RTEMS real-time kernel (rtems-4.5.0+) # Boot-prom utility (mkprom-1.3.3) # GNU debugger with Tk front-end (gdb-5.0 + insight-5.0) # DDD graphical user interace for gdb (ddd-3.1.3) # Remote target monitor (rdbmon-1.3) Cheers Matthias DyerArticle: 43486
Hi Newsgroup, I have a question which is very basic. Is it possible to overheat a Spartan2 FPGA just with tasks in the downloaded program? Regards, SteffenArticle: 43487
See the RocketIO on the VirtexII-Pro serie ! Laurent www.amontec.com Mitchell Crago wrote: > I need to develop a High-Speed buffer (1Gbps line speed) system using a > Xilinx FPGA - currently I am looking at the Virtex-II family. > > The Max CLKIN/CLKOUT for a -5 grade chip is 420MHz. > > Q1. Is it possible to achieve 1Gbps on a serial input for this device? > I have a feeling I cant - is this good hunch? > > Q2. What would be the max IO datarate achievable? 840Mbps using DDR? > > Q3. Is there a Xilinx FPGA capable of such serial datarates? > > Sorry for the scattered question, but I'm fed up with trolling through > datasheets > > Thanks in advance for any help, > > Mitchell Crago > mmccrraaggoo@@ffllooww.ccoomm.aauu > __________________________________________________________________ > > >Article: 43488
To learn about HDL and FPGA, it is better to start with small chip like CPLD and try to design simple counters or parallel-serial designs. The free webpack of Xilinx can be used for all Xilinx CPLD, and SpartanII FPGAs. It is free and works very well. Our Chameleon POD is a small and very low cost board to do your first steps in the HDL world. It is based on Coolrunner CPLDs. It can be connected directly to your computer parallel port for downloading the CPLD and for working with it. The Chameleon POD comes with free configuration, like pseudo xilinxcableIII jtag cable to download all you next Xilinx FPGA, pseudo wiggler jtag cable to control all arm processors and many other pseudo jtag POD or DDS core and PSK core. With Chameleon POD, you will have a good prototyping board for small designs and many free configurations. Laurent Gauch www.amontec.com James Zaiter wrote: > hi my name is james and my email is jzaiter@magnasys.com.au > I am new to fgpa programming and need some direction in learning to programm > these devices. > I need help with software and development board preferably xilinx > xc2000,xc3000 and xc4000 chips. > is there any free software available to use for learning purposes only as i > have a very small budget. > any help would be much appreciated. > james > > >Article: 43489
Hi all, I have been thinking about using a simulated sea-of-gates FPGA architecture for some design experiments. I want to keep the architecture as simple as possible. I was thinking about using a sea of 4 input LUTs, each of the four inputs being driven by the output from one of the 4 surrounding LUTs, as I can easily map this to a real FPGA. However as there is only 1 layer of logic no signal can cross another, which really limits what combinational logic you can make. I understand the Xilinx 6200 had a similar architecture. I suppose the longer lines could be used to cross signals, but it doesn't seem reasonable to have such a serious limitation for an FPGA. Is there anyone out there who did designs with the 6200 that can tell me what I'm missing? Cheers, AngusArticle: 43490
Hi although I hope you'll get the definitive answer over on the active HDL group, I wouldn't hold your breath :) Best place I've found to answer this sort of thing is with your local distributor who can then pass on the request. I've had a similar problem using Leonardo for synthesis with Altera, and it basically stems from the use of libraries. Bringing up the library manager you'll probably see an fpga express library and xilinx's own. In my Altera situation, for post-synthesis simulation AHDL complains about missing or incorrect apex20ke LCELLs etc which stems from a slight naming difference between Leonardo and Altera (I think) Somewhere in the bowels of the product I read that you need to detach the altera library and then rename the altera exemplar library to altera. Fortunately AHDL do provide a script to do this for you. Take a look around and see if you come up with similar scripts etc. for your product combination. FWIW AHDL-hosted synthesis/PAR often does not allow you to specify optimised settings for the design, so it would be worthwhile you comparing the synthesis/timing report generated by the tools within AHDL and separately as a properly configured standalone synthesis/PAR process. I found Leonardo was set to some relatively quick but poor options and that Quartus 2 P&R was using some generic default files rather than optimised constraints. (Q2 has been alleviated in SP3 of AHDL because you can specify external constraint files) Check with FPGA express to see if you have similar issues. Also, why are you simulating post-synthesis? Usually this has a poor guess at routing speeds so any 'timing' issues won't get seen. IMHO you may be better to PAR and then use the timing simulation for better results. Start with a functional sanity check, then straight to timing. Overall AHDL is a fine product, but make sure you get the best out of the design flow by optimising synthesis/PAR outside AHDL first and then compare to the AHDL-driven approach. Youcan still easily use AHDL with the vho/sdf files for simulation etc. Good luck Paul Baxter >Article: 43491
Anybody know where I can get orcad symbol for virtex II XC2V-6000 FF1152 ?
greg
Article: 43492Check out our tutorials at http://www.al-williams.com/pictutor. The Xilinx tutorial uses the free Web Pack and although it is meant to work with our low-cost development board (http://www.al-williams.com/awce/pbx84.htm), you can also just work through it with simulation. The tutorial uses a different Xilinx part, but it will let you see how everything works including simulation, Verilog, etc. Al Williams AWC > I am new to fgpa programming and need some direction in learning to programm > these devices. > I need help with software and development board preferably xilinx > xc2000,xc3000 and xc4000 chips.Article: 43493
Hi, Our team of volunteers need people with good knowledge on FPGA development and time to develop an FPGA that will be used into a computer board. To learn more about this FPGA, see at this url : www.arnold6.com If you're interrested to join our team, please subscribe to our mailing list for developpers : www.egroups.com/group/ngcpc Or contact us as soon as possible : christopheguelff@aol.com & Hans.Summers@tudor.com If you want to have fun and work on a great and ambitious project, it's the time to join us ! Thanks, ChrisArticle: 43494
I'm looking for a dual processor system for a new employee.
The systems we have in house right now are Dual P3's
(800-1200 MHz) with 1-2GB memory and ultraSCSI RAID. Looking
for similar horsepower but with more recent technology.
What are people buyng today as far as serious workstations
for synthesis, simulation and PAR?
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin
Franklin, 1759
Article: 43495
It is, but at 50MHz you'd have to work really really hard at it. That assumes
you are not shorting any of the I/O, of course. I think a Xc2S50 with all the
cells connected as SRL16s plus registers and toggled on average at 50% is going
to be well under 2W. Most designs are not going to come near that level of
activity.
Steffen Thieringer wrote:
> Hi Newsgroup,
> I have a question which is very basic.
>
> Is it possible to overheat a Spartan2 FPGA just with tasks in the downloaded
> program?
>
> Regards, Steffen
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43496Hi, For incorporating a very old design as part for a new design, I need to reverse engineer the bitstream of a XC3020A fpga. Can any one point me to a method to generate a kind of edif or xnf or other netlist from the bitstream?? I know it is maybe a stupid question, but I need to try it because it is important here. Thanks a lot. StefaanArticle: 43497
Hello to everybody, I'm working on a design containing a xilinx 4000 series FPGA (Very old, I know).However recently we had some problems, especially on reset. It sometimes get's into an unwanted state after a reset or power on. Put the same code in a spartan and the problem dissapears. The FPGA is used as a VME controller (slave device on bus)and it takes directly the signals from the bus (like SYSRES, DTACK, data strobes, ...), without registering or making them synchronous. Would that be a part of my problem? I'm pretty new into this business and have heard several stories of first double registering your signals before acting on them. However, I never heard the whole story. Maybe it's also because the edge of the signals is not perfectly straight? Somebody else told me to use a double flip flop but when and how? Anyone out there who could clarify some things? Thx, JerreArticle: 43498
> I'm looking for a dual processor system for a new employee. > The systems we have in house right now are Dual P3's > (800-1200 MHz) with 1-2GB memory and ultraSCSI RAID. Looking > for similar horsepower but with more recent technology. > What are people buyng today as far as serious workstations > for synthesis, simulation and PAR? > Ray, I've had no problems so far with a dual Athlon 2GHz with a 1Gb of RAM - running quartus 2, ActiveHDL, Leonardo with Apex 20KE 600 devices. Also has a normal IDE hard disk system (with RAID set to mirror for backup) which is not noticibly slower than my previous much more expensive fast SCSI system. The dual system typically benchmarks at ~95% of a single Athlon 2GHz for single tasks, but shines when more tasks are going on. Multithreaded benchmarks show a 30-50% improvement over single processor in these situations. Its quite a cheap alternative to dual Pentium 4 systems probably setting you back less than $2k with a 21 inch monitor. Would recommend A Matrox dual head video card as although their games ability is terrible, the 2D performance is excellent and crisp. Also supports dual monitor very well if that's of interest. 18 inch TFT flat panel displays are also now affordable, though I think 1280x1024 is pushing it for simulation work. 1600x1200 is more usable IMO If you go for a flat panel though, get a video card with digital video output rather than VGA as the difference in clarity is well worth it. Paul BaxterArticle: 43499
Phil, Glass is half empty (test escapes happen), glass is half full (but we are forcing them to zero with improved test programs). Point of view. QED. The real point is more one of AQL (acceptable quality level) rather than one of perfection. The Quality folks always talk about zero defects, but that isn't what anyone really wants: they want an AQL at an AP (acceptable price). Each industry segment has their own AQL requirement, and each has their own AP they are willing to pay. Milspec parts from the HiRel group here are a lot of fun to examine in this regard. Getting parts qualified for space, or aircraft, or ground based systems are all different. Things get really expensive. FPGAs are a unique problem: they wake up and ask "who I am going to be today?" Thus the test program has to somehow test for every possible application (impossible) or test for every possible functional and AC combination of elements (hard, but not impossible). Thank goodness they are SRAM based. My only point was that we have improved (we have to), and test escapes are much less frequent, even though the complexity and number of devices has grown to over 500 million transistors on a die. Austin Phil Hays wrote: > Austin, > > > I have also stated that over time, we get better in our test coverage as we > > hear from everyone who finds an occasional test escape, and fix the program. > > > How we actually accomplish what you state is impossible, is proprietary and > > confidential (or already covered by patents, or in patents pending), > > Touchy on Monday morning, eh? > > I said "A complete test isn't practical." > > If Xilinx was doing a complete test, there would be no occasional test > escapes, correct? > > We agree that there are test escapes. > > So Xilinx isn't doing a complete test. QED. > > As a mostly happy Xilinx customer, for my current application I'd rather > reduce my odds of finding an occasional test escape. I know that this > isn't free, and I know that my current application isn't anything close > to the average. > > -- > Phil Hays
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