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Well, this seems to be the Spartan-II XC2S50 or the XCV250E. They have 1728 look-up tables and flip-flops plus 64K bits of BlockRAM. You can do a lot of state machines, counters, code converters, instrumentation, industrial control, etc. How's about 40 individual 32-bit 100-MHz counters, plus read-out through an asynchronous FIFO that is 32 bits wide and 256 deep, plus additional controls and other good things. Floating point is not the only, nor the most meaningful application... Peter Alfke ============================= Tyler Reed wrote: > I think you'd be hard-pressed to fit even a couple of floating-point > multipliers in 20k gates, so doing actual computing is out. You may be able > to build some simple logic circuits. > > Tyler Reed > > "Roger King" <roger@king.com> wrote in message > news:iqvN8.251995$ah_.246227@news01.bloor.is.net.cable.rogers.com... > > Ok, let me give you a better statistic, 384 CLBs? 384 sounds like a really > > low number, it looks like I can only develop extremely simple projects. > > > > > > > > "Roger King" <roger@king.com> wrote in message > > news:CUmN8.248826$ah_.140060@news01.bloor.is.net.cable.rogers.com... > > > Is 20,000 gates enough for creating a nice project? What are some > projects > > > one can create by using 20,000 gates? I am trying to decide if 20,000 > > gates > > > fpga board would be sufficient for a hobbyist that wants to use it for > > about > > > 2 years. > > > > > > I have another question. How many megs of RAM will I be able to develop > > > using 20,000 gates fpga? I mean if I want to use the fpga as a ram. > > > > > > > > > > > > > > > >Article: 44151
I just discovered the original 29 manual instantiations is also now broken. It's 7.1 that's messing with me now! 7.0.3 didn't optimize my 29 elements into a short chain like 7.1 does. When you're broadsiding chip inputs into a fast AND, short chains don't work! John_H wrote: > I'm having MUXCY trimming problems *right now*. I tried to take my 29 MUXCY > instantiations and convert them into an array of instances. Yuck! The physical > implementation of my chain became toast once Synplify started "optimizing" the pass > elements out of the chain (I have several in the middle). > > The inclusion of oh-so-many LUT1_2 elements is getting at my nerves as well: I > tried a MUXCY primitive redefinition (I called it MUXCYdammit) with syn_hier="hard" > like I did earlier with an FDRE but if you push down into the instance in > HDL_Analyst, there's a pass-LUT on the sel input. Once again Synplify knows > better. Oy. > > The apps engineers are looking at my chain, but I imagine it's back to the 29 > individual instances. I hope those aren't broken! > > - John_H > > Rick Filipkiewicz wrote: > > > O.k. I think I've found it. I removed the RLOCs on the MUXCYs just leaving them > > on the LUTs themselves and MAP survived so I could see the results. Basically > > the RPM is implementing a function: > > > > ((addr[8:0] & mask[8:0]) != 0) > > > > 2 bits at a time via the carry chain. In the situation I have there are some > > builds with only small, 256MB, memory space where the top 3 bits of the mask > > function are ifdef'ed to 0 so. Since its all instantiated Synplify doesn't (this > > time) try and do any optimisation and leaves the full 5 element chain in place > > for both builds. > > > > MAP is much cleverer and realises that in the small build the top 2 LUT outputs > > are always 1 => carry chain pass through => ``Hey I can optimise/trim those 2 > > LUTs'' and move the output down 2 steps. > > > > For some reason this causes something to go horribly wrong in the pack phase of > > MAP. I'd guess that with RLOCs on the top 2 MUXCYs they were not being trimmed > > along with their associated LUTs - or some such.Article: 44152
Georg, talk to Roger Gook at Celoxica (used to be ESL). They have some interesting co-design/ co-processing solution for SOPC. Noel Georg Heinrich <Georg.Heinrich@eas.iis.fhg.de> wrote in message news:<3CF234DF.D6E45A07@eas.iis.fhg.de>... > Hi Folks, > I am just wrtiting my thesis concerning HW-SW-Codesign and related stuff and need some > expieriences about the SOPC Builder from Altera and the target architectures Excalibur > (NIOS & ARM). > > If anybody uses the SPW-development-System from Cadence or the Innoveda > System-Level-Design-Tools : > > Any Hints & Storys appreciated > > Best regards from Dresden > > GeorgArticle: 44153
Hi folks,
In a tricky little design I'm doing I use an edge triggered RAM which I
read on the rising clock edge and write on the falling clock edge, so
that I can get my data through quickly (one item per clock tick).
This results in the following structure for the RAM's write enable
signal:
we_RAM <= (not clk) when w_en ='1'
else '0';
where w_en is an input port that is high when we should be writing
data.
I am, in effect, gating the clock signal, and I know that this is not
something to be done lightly. I am also creating a locally inverted
clock signal, are there issues there as well?
Anyway my question is will the synthesis tools (XST targetting Virtex in
this case) figure out what I'm intending and do it in a sound way, or is
there maybe a better coding style to achieve what I want? we_RAM does
not propagate past the RAM it is attached to, so I'm not too worried
about it being a low skew clock line or anything like that.
I could change the else clause to be "else 'Z'", which (I assume) would
create an inverting tristate buffer on the clock line, but I'm not sure
how a "Z" on the write_enable port would cause the RAM to behave.
Any comments?
Thanks,
John
--
Dr John Williams, Postdoctoral Research Fellow
High Performance Computing Group, CRC for Satellite Systems
Queensland University of Technology, Brisbane, Australia
Phone : (+61 7) 3864 2427 Fax : (+61 7) 3864 1517
Web : http://www.crcss.bee.qut.edu.au/comp.html
Article: 44154hellom i have F4.2i installed in my machine. want to install the last patch available on xilinx site. although i have choosen F4.2i and not ISE4.2i the patch available looks the same for the both. i have launched the installation, the GUI shows just ISE want to be sure first before carrying on the installation is the Patch2 the same for both? thanks --HristoArticle: 44155
I haven't tried it in 7.1 yet, I was just going on what Synplicity told me when I filed
a bug report. Do us all a favor and file it as a bug report too. I don't think putting
the syn_hier="hard" is going to fix it either, plus it commits the cardinal sin of
messing with the tool libraries. The reason I don't think it will fix it is that
Synplicity apparently does an optimize phase after synthesizing to primitives. It
should be sufficient to have the thing black boxed, but it is not.
Fortunately, there is a work-around: Instantiate the FDRE using the unisim library
element with the library declaration syn_translate off'd and the FDRE tagged with the
syn_black_box attribute. That much you are probably already doing. Now, put a syn_keep
on the signal going into any two of the inputs (D, R or CE). That syn_keep seems to
stick through the optimize phase and prevents the optimizer going in and doing the
"wait, I recognize tht FDRE and I can do it better than you" optimization with
relatively little pain.
John_H wrote:
> I was hoping you were right and it got fixed in 7.1. It didn't. I just got the new
> Synplify version running and the same FDRE primitive I instantiated a week ago - the
> one that got optimized on me prompting my creation of an FDREdammit primitive with
> syn_hier="hard" - still gets optimized for me if I use the FDRE. I'm considering
> adding a syn_hier="hard" to Synplify's Xilinx primitive files.
>
> Ray Andraka wrote:
>
> > You can always instantiate the FDRE or FDSE. Then again, you may still need
> > syn_keeps on any logic you put in front of them. Synplicity has recently (v7.03)
> > ripped up instantiated components and 'optimized' them on me. Apparently there is
> > an optimize phase after synthesis to primitives and at that point it can't tell
> > the difference between an inferred and an instantiated primitive. I think this
> > one got fixed in 7.1, but it also isn't the first time I've seen Synplicity
> > ripping up stuff that I instantiated. I think it needs an internal
> > syn_the_user_instantiated_this_primitive_so_I_better_leave_it_alone flag on
> > instantiated primitives (it should be easy to identify anything that is
> > black-boxed when parsing the code in the first pass, especially if there is a
> > syn_black_box atribute on the component.
> >
> > John_H wrote:
> >
> > > I like the directive thought...
> > >
> > > /* synthesis syn_for_all_that_is_holy_please_oh_please_use_an_FDSE */;
> > >
> > > Rick Filipkiewicz wrote:
> > >
> > > > What we need is a directive like ``syn_carry_chain'' or, to make quite sure,
> > > >
> > > > ``syn_this_is_a_carry_chain_so_just_do_it_and_dont_ask_questions''.
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44156Walter Banks <walter@bytecraft.com> wrote in news:3D078061.9BDE9DE@bytecraft.com: >Get a copy of "Software cost estimation with COCOMO II" by >Barry Boehm et al. > I too recommend that book. I found it a while ago at http://micro.filetap.com/Article: 44157
Jim Granville <jim.granville@designtools.co.nz> wrote in message news:<3D06C5D6.57A@designtools.co.nz>... > Peter Brenner wrote: > > > > Does anyone know of a programmable logic device or FPGA that can > > operate to the folowing specifications: > > > > >311 MHz operating speed > > Industrial temperatures (-40 to 85 degrees Celcius) > > Low Power (< 1 Watt) > > Small footprint > > 2 global clocks (minimum) > > Immediate Availability > > > > one-time programmable devices are okay, although would prefer not to > > use one. > > This is too vague for usefull replies..... > > One designers small is anothers large. > What package type/dimensions ? Is BGA ok ? > How many IO / registers/ ram ? > is the 311MHz for a Serial Capture, or floating point maths ? > How many nodes need to clock at 300+MHz > > There are data sheets claiming > 300MHz for CPLD, and FPGA's can get to > that locally. > > -jg BGA is fine. We have room for a 3mm * 3mm device, although we only need substantially less resources than typically contained in such a device. We're looking at needing only 6 flip flops. Certainly a 32-macrocell device is sufficient. the 311 MHz is for Serial encoding and decoding. The encoders and decoders are simple, but all flip-flops would need to clock at this rate. There are two clocks, both at 311 MHz, one input and one output at 155 MHz (Mbps), and one input and one output at 311 MHz (Mbps). I'm aware of some CPLDs that will claim > 300MHz, but I haven't as yet seen any low power devices that operate at Industrial temperatures.Article: 44158
> What package type/dimensions ? Is BGA ok ? Correction to : BGA is fine. We have room for a 3mm * 3mm device, although we only need substantially less resources than typically contained in such a device. - sorry, meant to be: 30mm * 30mmArticle: 44159
First, you might get a copy of Marv Frerking's Digital SIgnal Processing
in COmmunications Systems text. It is very well written, and if you are
into digital radio, is worth more than you pay for it. The ARRL Radio
Amateur's handbook is also a useful reference.
The resolution of converters is more or less inversely proportional to the
max sample frequency. You can get 8 bit converters at 1GHz or more. 12
bits seems to top out at a just a bit over 100MHz (the AD9432 is a 105 MHz
12 bit converter). If you want more bits, you get lower sampling rates.
With a limited number of bits in RF capable converters, you wind up with a
very limited (wrt the entire spectrum) dynamic range. For a practical
radio, you'll need a fairly narrow filter to block out strong signals near
the desired signal. 12 bits isn't much to quantize the entier RF
spectrum. If you have an analog front end, you can do this by mixing to
an IF where you can filter the signal with a high Q analog filter before
digitizing it, which is what you are doing.
We've got a demo application in process that puts a direct conversion
digital HAM radio in a SpartanII-100. The entire radio consists of an
antenna tuner/preamp, a burr-brown ADC demo board, and insight SpartanII
demo board with a pair of RC filters and a phone jack added to it, and a
pair of PC speakers. The spartan has in it all the tuning, filtering
decimation, demodulation and a PWM output. It will do AM, SSB, DSB, AM
stereo and CW demodulation, with plans for FM later. It makes for a
pretty cool demo, although it is not all that practical because of the
limited dynamic range of the 12 bit ADC. I am hoping to get it in a state
suitable for showing for the MAPLD conference in Laurel MD in September.
FM needs a complex baseband in order to recover the phase. In a digital
radio, you can mix your real-only digitized IF with a complex sinusoid and
then decimate it to make your filtering a whole heck of a lot easier. One
of the advantages of digital IQ separation is that you don't have the
phase and matching sensitivities you have with an analog IQ stage. With a
10 KHz BW, you can decimate to a couple times that (pick a sample rate
that makes your filter easier). Once it is filtered, then you need to
recover phase from that complex baseband signal. Phase recovery can be
done by a number of methods, a conceptually simple one being to use a
CORDIC rotator to pull out phase and magnitude.
jaideep wrote:
> Hi Newsgroup,
>
> In continuation to my earlier post with the same subject, I would
> appreciate very much, if someone can provide me with the following
> answer: what is highest frequency analog signal that I can sample with
> the currently available data converters. I am considering 2 sampling
> rates; one Nyquist and the other 4x upsampling.
>
> Thanks to Noddy for providing the information. I forgot to mention
> that the IF signal (10.7 MHz +/- 125 KHz) contains FM data around
> another subcarrier located 70KHz from the center of 10.7 MHz. The FM
> data BW is 10 KHz around this subcarrier. Therefore I guess we need to
> have a very sharp BPF centered at 70 KHz with a BW of 10KHz.Invite any
> suggestion/discussion on this subject and also as how to implement
> this in FPGA.
>
> Thanks in advance.
>
> Jaideep Bose
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44160
The Hilbert transform will leave you a hole at DC if you are doing single conversion,
and can make for a complicated filter. FOr digital IQ separation, you are better off
using a complex mixer and then low pass filtering the I and Q outputs.
The FPGA can actually be worth it if you manage to do the design in a lower cost
FPGA. We've got a demo we are putting together that puts a direct conversion Ham
radio in a spartanII-100 on an insight eval board. A decent part of that design is
working at sample rates that couldn't be touched by a DSP. If you instead did the
digital starting at an IF, then the digital portion would easily fit in a portion of
an XC2S50 leaving room for additional stuff. If you can put your processing into
one of the cheap parts, it becomes very competitive with a DSP processor. Going the
other way (ie modulating) is easier, and can be done in a pretty small portion of the
FPGA. THe FPGA solution also has the potential for using considerably less power
than a DSP (see my ee-times article on power in the links section of my website).
Austin Lesea wrote:
> John,
>
> You need to get the I and Q signals to do a digital FM demod using the Hilbert
> transform.
>
> You can look for references by searching on "digital FM demodulation." Or you
> can read up on it in the ARRL Handbook.
>
> A number of high end ham transceivers use DSP to perform all signal processing
> (USB, LSB, AM, FM, CW, speech processing, variable bandwidth filters) at the IF
> frequency right down to the audio. Some even use DSP to go the other way, and go
> from USB, LSB, AM, FM, CW all the way back to IF with filters, compression, etc.
>
> The IF in this case is shifted down to where a DSP chip can handle it. The rates
> are not high enough to warrant using a FPGA.
>
> Austin
>
> John_H wrote:
>
> > www.analog.com is where I'd go as well.
> >
> > Since the application is FM, the (up to) 200kHz bandwidths wouldn't
> > quite be compatible with a 455kHz filter. The 10.7MHz filters are
> > available specifically for FM.
> >
> > The 90 degree transform is interesting - do you mean quadrature
> > sampling? By sampling the signals at points 90 degrees out of phase,
> > two independent signals can be extracted from a quadrature modulated
> > signal without additional processing. Does the FM encode anything in
> > quadrature? It's been too long since I've played with it.
> >
> > Analog devices also has nice resolution in the dual-channel devices but
> > it sounds like quadrature is overkill.
> >
> > Sampling the 10.7MHz at an odd multiple of 10.7MHz will eliminate the
> > problem of catching the "peak" of the signal. Consider sampling a
> > 10.7MHz sine wave at 21.4MHz... there's a chance (without some form of
> > phase lock) that the sampling will occur at the zero crossings instead
> > of the peaks. Since "40MHz" is a popular A/D speed, perhaps sampling at
> > 32.1 MHz will give you the data you need to avoid quadrature processing
> > or frequency control in the analog realm.
> >
> > Have fun!
> >
> > Bevan Weiss wrote:
> > >
> > > Analog Devices have some pretty nice high speed ADC's.
> > > AD6645 : 14bits @ 105MSPS
> > > AD9430 : 12bits @ 200MSPS
> > > AD9410 : 10bits @ 210MSPS
> > > AD9054 : 8bits @ 200MSPS
> > >
> > > So it becomes a bit of a tradeoff between speed and resolution. And then
> > > there's cost...
> > > And power dissipation...
> > >
> > > You've also got to remember that any mixing(intentional or not) that you do
> > > will create intermodulation products, some of these will most likely fall
> > > within the bandwidth of any basic (non-crystal/ceramic-resonator) filter.
> > >
> > > You could always use a 455kHz IF. Btw, why did you choose the 10.7MHz IF??
> > >
> > > With a 455kHz IF you could probably then just follow it up with a low
> > > pass/bandpass filter that would create a narrow enough signal to feed into
> > > your ADC's. Then do most of the more specific filtering in the FPGA
> > > hardware (if you've got the room).
> > > As for the actual FPGA implementation, you could use something like a
> > > 90degree transform and then the CORDIC algorithm on both the phase and
> > > quadrature signals. This will get you the magnitude, and the angle. Over
> > > time that's also the frequency.
> > >
> > > "jaideep" <jaideep@sasken.com> wrote in message
> > > news:c4312ee4.0206120057.65e089f@posting.google.com...
> > > > Hi Newsgroup,
> > > >
> > > > In continuation to my earlier post with the same subject, I would
> > > > appreciate very much, if someone can provide me with the following
> > > > answer: what is highest frequency analog signal that I can sample with
> > > > the currently available data converters. I am considering 2 sampling
> > > > rates; one Nyquist and the other 4x upsampling.
> > > >
> > > > Thanks to Noddy for providing the information. I forgot to mention
> > > > that the IF signal (10.7 MHz +/- 125 KHz) contains FM data around
> > > > another subcarrier located 70KHz from the center of 10.7 MHz. The FM
> > > > data BW is 10 KHz around this subcarrier. Therefore I guess we need to
> > > > have a very sharp BPF centered at 70 KHz with a BW of 10KHz.Invite any
> > > > suggestion/discussion on this subject and also as how to implement
> > > > this in FPGA.
> > > >
> > > > Thanks in advance.
> > > >
> > > > Jaideep Bose
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44161
Arctan can be calculated in hardware with CORDIC, then the phase is jsut the
difference between samples. You can get a fairly crude phase recovery by
multiplying a sample by the complex conjugate of a sample in the prevous symbol
time, or by using the derivatives: phase ~= (IQ'-QI')/(I^2 + Q^2). If you
limit the vector to the unit circle before differentiating, then the mag squared
term is 1. If you want top notch FM detection, then you'll probably want to go
with a phase lock loop type detector.
Kevin Neilson wrote:
> What do you do with the output of the Hilbert transform?
>
> The way I've seen it done is to find the derivative (just the delta between
> samples) of arctan(I/Q) and make the demodulated output proportional to
> that. Calculating arctan requires some sort of Taylor polynomial calculator
> though unless you have a big LUT.
>
> -Kevin
>
> "Austin Lesea" <austin.lesea@xilinx.com> wrote in message
> news:3D075DE6.F274C3B1@xilinx.com...
> > John,
> >
> > You need to get the I and Q signals to do a digital FM demod using the
> Hilbert
> > transform.
> >
> > You can look for references by searching on "digital FM demodulation." Or
> you
> > can read up on it in the ARRL Handbook.
> >
> > A number of high end ham transceivers use DSP to perform all signal
> processing
> > (USB, LSB, AM, FM, CW, speech processing, variable bandwidth filters) at
> the IF
> > frequency right down to the audio. Some even use DSP to go the other way,
> and go
> > from USB, LSB, AM, FM, CW all the way back to IF with filters,
> compression, etc.
> >
> > The IF in this case is shifted down to where a DSP chip can handle it.
> The rates
> > are not high enough to warrant using a FPGA.
> >
> > Austin
> >
> > John_H wrote:
> >
> > > www.analog.com is where I'd go as well.
> > >
> > > Since the application is FM, the (up to) 200kHz bandwidths wouldn't
> > > quite be compatible with a 455kHz filter. The 10.7MHz filters are
> > > available specifically for FM.
> > >
> > > The 90 degree transform is interesting - do you mean quadrature
> > > sampling? By sampling the signals at points 90 degrees out of phase,
> > > two independent signals can be extracted from a quadrature modulated
> > > signal without additional processing. Does the FM encode anything in
> > > quadrature? It's been too long since I've played with it.
> > >
> > > Analog devices also has nice resolution in the dual-channel devices but
> > > it sounds like quadrature is overkill.
> > >
> > > Sampling the 10.7MHz at an odd multiple of 10.7MHz will eliminate the
> > > problem of catching the "peak" of the signal. Consider sampling a
> > > 10.7MHz sine wave at 21.4MHz... there's a chance (without some form of
> > > phase lock) that the sampling will occur at the zero crossings instead
> > > of the peaks. Since "40MHz" is a popular A/D speed, perhaps sampling at
> > > 32.1 MHz will give you the data you need to avoid quadrature processing
> > > or frequency control in the analog realm.
> > >
> > > Have fun!
> > >
> > > Bevan Weiss wrote:
> > > >
> > > > Analog Devices have some pretty nice high speed ADC's.
> > > > AD6645 : 14bits @ 105MSPS
> > > > AD9430 : 12bits @ 200MSPS
> > > > AD9410 : 10bits @ 210MSPS
> > > > AD9054 : 8bits @ 200MSPS
> > > >
> > > > So it becomes a bit of a tradeoff between speed and resolution. And
> then
> > > > there's cost...
> > > > And power dissipation...
> > > >
> > > > You've also got to remember that any mixing(intentional or not) that
> you do
> > > > will create intermodulation products, some of these will most likely
> fall
> > > > within the bandwidth of any basic (non-crystal/ceramic-resonator)
> filter.
> > > >
> > > > You could always use a 455kHz IF. Btw, why did you choose the 10.7MHz
> IF??
> > > >
> > > > With a 455kHz IF you could probably then just follow it up with a low
> > > > pass/bandpass filter that would create a narrow enough signal to feed
> into
> > > > your ADC's. Then do most of the more specific filtering in the FPGA
> > > > hardware (if you've got the room).
> > > > As for the actual FPGA implementation, you could use something like a
> > > > 90degree transform and then the CORDIC algorithm on both the phase and
> > > > quadrature signals. This will get you the magnitude, and the angle.
> Over
> > > > time that's also the frequency.
> > > >
> > > > "jaideep" <jaideep@sasken.com> wrote in message
> > > > news:c4312ee4.0206120057.65e089f@posting.google.com...
> > > > > Hi Newsgroup,
> > > > >
> > > > > In continuation to my earlier post with the same subject, I would
> > > > > appreciate very much, if someone can provide me with the following
> > > > > answer: what is highest frequency analog signal that I can sample
> with
> > > > > the currently available data converters. I am considering 2 sampling
> > > > > rates; one Nyquist and the other 4x upsampling.
> > > > >
> > > > > Thanks to Noddy for providing the information. I forgot to mention
> > > > > that the IF signal (10.7 MHz +/- 125 KHz) contains FM data around
> > > > > another subcarrier located 70KHz from the center of 10.7 MHz. The FM
> > > > > data BW is 10 KHz around this subcarrier. Therefore I guess we need
> to
> > > > > have a very sharp BPF centered at 70 KHz with a BW of 10KHz.Invite
> any
> > > > > suggestion/discussion on this subject and also as how to implement
> > > > > this in FPGA.
> > > > >
> > > > > Thanks in advance.
> > > > >
> > > > > Jaideep Bose
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44162Peter Brenner wrote: <snip > BGA is fine. We have room for a 3mm * 3mm device, although we only > need substantially less resources than typically contained in such a > device. > > - sorry, meant to be: 30mm * 30mm just as well :) > > We're looking at needing only 6 flip flops. Certainly a 32-macrocell > device is sufficient. > > the 311 MHz is for Serial encoding and decoding. The encoders and > decoders are simple, but all flip-flops would need to clock at this > rate. > > There are two clocks, both at 311 MHz, one input and one output at 155 > MHz (Mbps), and one input and one output at 311 MHz (Mbps). > > I'm aware of some CPLDs that will claim > 300MHz, but I haven't as yet > seen any low power devices that operate at Industrial temperatures. Industrial grade devices are more sparse, but Atmel offer low power + industrial. ( but not to 300MHz.. ) Closest would be (on paper) Lattice LC4032C-25T48C and LC4032C-5T48I You would need to check the temp/speed effects, but self heating should be low <100mW at 300MHz. It's die temp that's the key, and thermal management can help the industrial margins. -jgArticle: 44163
You can do quite a bit with 20K gates if you are clever about it. First caveat,
how fast do you want to process the data? If it is real fast, then you'll need
more gates to do it. Still 20K gates is a respectable size for many things.
For example, a number of years ago I replaced a rack of 17 DSP cards in a radar
processor (doing some filtering and a doppler pulse pair, and floating point
accumulation) in 3 4013's, or roughly 40K gate capacity, and that was two
channels worth.
You can do floating point, even full ieee floating point in a 20K gate device,
but if you do it in full parallel arithmetic you will take up most of the logic
doing it. However, there is seldom a compelling need to do full floating point
in an FPGA. In most cases you can get by fine with fixed point, and when you
can't you can separate the exponent off and work several operations on the
mantissa as fixed point thereby avoiding a lot of the normalizing/denormalizing
overhead of floating point. You also don't always need to use 24e8
formats...that is way overkill unless you are doing general purpose processors.
At reasonable data rates, there is also the possibility of using bit serial
arithmetic. In that case, you can do an amazing amount of computation in an
itty bitty space. Early scientific calculators used bit serial arithmetic and
CORDIC operations to fit lots of function into very little logic. I'd bet one
of those calculators would fit within a fraction of one of those 20K gate
devices.
My point, is there is an awful lot of processing you can do in those 20K
marketing gates, if you know how to approach the problem. I can remember not
long ago when a 4025 (25K gates) was a huge device, and yes, we were doing lots
of processing in those parts (see my MAPLD paper on a real time radar
environment simulator, available on the publications page of my website).
Tyler Reed wrote:
> I think you'd be hard-pressed to fit even a couple of floating-point
> multipliers in 20k gates, so doing actual computing is out. You may be able
> to build some simple logic circuits.
>
> Tyler Reed
>
> "Roger King" <roger@king.com> wrote in message
> news:iqvN8.251995$ah_.246227@news01.bloor.is.net.cable.rogers.com...
> > Ok, let me give you a better statistic, 384 CLBs? 384 sounds like a really
> > low number, it looks like I can only develop extremely simple projects.
> >
> >
> >
> > "Roger King" <roger@king.com> wrote in message
> > news:CUmN8.248826$ah_.140060@news01.bloor.is.net.cable.rogers.com...
> > > Is 20,000 gates enough for creating a nice project? What are some
> projects
> > > one can create by using 20,000 gates? I am trying to decide if 20,000
> > gates
> > > fpga board would be sufficient for a hobbyist that wants to use it for
> > about
> > > 2 years.
> > >
> > > I have another question. How many megs of RAM will I be able to develop
> > > using 20,000 gates fpga? I mean if I want to use the fpga as a ram.
> > >
> > >
> > >
> > >
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44164
In article <3322b9fc.0205220129.d05d487@posting.google.com>,
ziakjan@host.sk (Jan Ziak) wrote:
> OK. An example. Suppose that I have a simulation with agents in it
> (agent-based simulation). The agents have relatively simple logic.
> Agent's algorithm complexity is not a problem here, but the problem
> here is the huge number of interactions between those agents. I
> suppose that you know what a multi-agent simulation is so I do not
> feel the need to write more about it.
>
> The number of agents is several thousands or more. The problem
> nowadays is that such simulations take a really long time to simulate.
> But the problem is inherently parallel - the algorithms of agents are
> executing in parallel from the point of view of an individual agent
> (you can think of such an agent as a human for example, the population
> of agents are people). The common solution nowadays is that we
> simulate that paralelism on sequential processors (like x86 or G4) and
> the result of course is that we have only several thousands of cycles
> per agent per second. This makes the simulation so slow. We cannot
> raise the number of agents to say 100000 because the simulation will
> simply "stop".
Are you attempting to solve a single particular problem or solve a
general class of problems ? If the latter, you have to think in terms
of local and global resources, which are limited at every level of
hardware packaging.
Any FPGA will allow a so-called "random logic" problem to be solved
with high efficiency. Most of the available gates in the device will
get used. Datapath problems, on the other hand, consume global
resources as wide busses are propagated across the chip. How well
you problem fits at the device level depends on how much data you are
trying to pass per clock cycle, between your functional units.
You could, for example, pass data via serial interfaces, to ease
the global routing resource limits. The tradeoff would be
an increase in communications latency.
Memory in programmable devices can be partitioned into independent
blocks with some granularity (i.e. M blocks of independent memory of
dimension P x Q). The memory could be used as program stores, for
example, but may be too small to contain a sufficiently complicated
algorithm.
At the board level, the chips are limited by the number of I/O's at
their edge. You could connect the chips in some regular pattern, but
the I/O on each chip would be a bottleneck for data trying to reach
a "far" agent.
At the backplane level, where the boards are connected together, there
is a more severe limit to the bandwidth available.
FInally, you connected the backplanes together into a rack of equipment.
There isn't enough "regularity" in any hardware, to allow totally
unconstrained design. the software you write, to fit your agents
into hardware, has to solve the exact same problem that the FPGA
design software is solving for the people in this group. The state of
the software, after years of development, is that it still takes
multiple passes at a design, to get the operating speed of the FPGA
into a reasonable range. There are many tricky pragmas to be embedded
in the source code, to get the desired effect. Seldom can a problem
be stated and solved in an FPGA, without much human intervention.
On the other hand, if you are willing to accept a design that runs
at, say 10% of the limit of the silicon, then the process could be
automated.
Now for some specifics. If you don't want to build hardware, you
could purchase a Quickturn box (www.quickturn.com) for a couple million
dollars. This contains hundreds of FPGAs connected in a regular
pattern. At my former employer, we used these boxes to test custom
chip designs, before the masks are generated. The quickturn box can even
be connected to other hardware (i.e. a fat cable and a PCI connector
allow connection to an IBM PC, for chip designs that have PCI
interfaces). These boxes are occasionally available used, as big
companies upgrade their hardware.
At the other extreme, many universities have access to local silicon
foundaries. Graduate students construct designs which are run through
the foundary using either separate wafers provided just for them,
or filling spaces on the wafer that aren't being used. If your ideas
have enough merit to convince people who have access to such facilities,
you could construct a device with just the right mix of local and
global resources. However, the nature of hardware prevents the regularity
of this structure from extending past the bounds of a single chip.
HTH,
Paul (a board designer, not a FPGA designer)
Article: 44165Are you reading and writing the same location? Virtex-II does that for free, with one clock edge ( read the old, then write the new data value, if you wish) Peter Alfke, Xilinx Applications John Williams wrote: > Hi folks, > > In a tricky little design I'm doing I use an edge triggered RAM which I > read on the rising clock edge and write on the falling clock edge, so > that I can get my data through quickly (one item per clock tick). > > This results in the following structure for the RAM's write enable > signal: > > we_RAM <= (not clk) when w_en ='1' > else '0'; > > where w_en is an input port that is high when we should be writing > data. > I am, in effect, gating the clock signal, and I know that this is not > something to be done lightly. I am also creating a locally inverted > clock signal, are there issues there as well? > > Anyway my question is will the synthesis tools (XST targetting Virtex in > this case) figure out what I'm intending and do it in a sound way, or is > there maybe a better coding style to achieve what I want? we_RAM does > not propagate past the RAM it is attached to, so I'm not too worried > about it being a low skew clock line or anything like that. > > I could change the else clause to be "else 'Z'", which (I assume) would > create an inverting tristate buffer on the clock line, but I'm not sure > how a "Z" on the write_enable port would cause the RAM to behave. > > Any comments? > > Thanks, > > John > > -- > Dr John Williams, Postdoctoral Research Fellow > High Performance Computing Group, CRC for Satellite Systems > Queensland University of Technology, Brisbane, Australia > Phone : (+61 7) 3864 2427 Fax : (+61 7) 3864 1517 > Web : http://www.crcss.bee.qut.edu.au/comp.htmlArticle: 44166
Peter Alfke wrote: > > Are you reading and writing the same location? > Virtex-II does that for free, with one clock edge ( read the old, then > write the new data value, if you wish) Yes, I am doing that, (read, update, write) however for now I am constrained to target a Virtex. Out of interest though, what is the VHDL template to do this dual read/write on a single clock edge? Regards, JohnArticle: 44167
"Ulf Samuelsson" <ulf@atmel.REMOVE.com> wrote in message news:<x0GN8.2791$t4.5860@nntpserver.swip.net>... > > > > In continuation to my earlier post with the same subject, I would > > appreciate very much, if someone can provide me with the following > > answer: what is highest frequency analog signal that I can sample with > > the currently available data converters. I am considering 2 sampling > > rates; one Nyquist and the other 4x upsampling. > > > You can get into the 1-2 GigaSample but I am sure that the design can be > complex. Hi ALL the Newsgroup Experts, I am overwhelmed with all the expert opinions that I received from all of you.Thanks specially to Ray Andraka for making his comments on FPGA implementation look so simple. Now I have my hands full. Here is a rider to the system that I have discussed: There is a doppler frequency offset of +/- 125 KHz at the RF carrier down to my second IF carrier at 10.7 MHz. The first goal of this receiver would be then to track the carrier to the center frequency and lock it to the receiver's local oscillators.Can a novel digital NCO design alongwith a PLL do this tracking at a much faster rate than its analog counterpart i.e. sweep the LO at a rate of 32 KHz/s to lock the carrier. This would take about 8 secs to sweep the full range of +/- 125 KHz! Also, what concerns me is that the FM data sits at 70 KHz from the second IF carrier and within the doppler range, SO THE BIG QUESTION IS WHETHER AT ALL THIS APPROACH WILL WORK OR NOT? I guess we can always wait till the carrier is locked(i.e doppler is compensated) and then do the FM demod to recover the data as suggested by many of you. Thanks in advance to all who wish to contribute to this ongoing discussion. Jaideep BoseArticle: 44168
John_H wrote:
>
>I tried a MUXCY primitive redefinition (I called it MUXCYdammit) with
>syn_hier="hard" like I did earlier with an FDRE but if you push down
>into the instance in HDL_Analyst, there's a pass-LUT on the sel input.
>
By "redefinition", do you mean:
A) put a MUXCYdammit wrapper with syn_hier="hard" around a MUXCY
or,
B) black box something called MUXCYdammit and edit the EDIF
post-synthesis to fix up the primitive names
I think "B" is fairly bulletproof, but you need a search-and-replace
to fix up the EDIF names, and a wrappered simulation library to let you
sim the primitives that have the tiny brown paper bags over their heads.
Brian
John_H <johnhandwork@mail.com> wrote in message news:<3D07B0CB.F77B1634@mail.com>...
> I'm having MUXCY trimming problems *right now*. I tried to take my 29 MUXCY
> instantiations and convert them into an array of instances. Yuck! The physical
> implementation of my chain became toast once Synplify started "optimizing" the pass
> elements out of the chain (I have several in the middle).
>
> The inclusion of oh-so-many LUT1_2 elements is getting at my nerves as well: I
> tried a MUXCY primitive redefinition (I called it MUXCYdammit) with syn_hier="hard"
> like I did earlier with an FDRE but if you push down into the instance in
> HDL_Analyst, there's a pass-LUT on the sel input. Once again Synplify knows
> better. Oy.
>
> The apps engineers are looking at my chain, but I imagine it's back to the 29
> individual instances. I hope those aren't broken!
>
> - John_H
>
>
Article: 44169
I haven't had too much trouble with the MUXCY's if I put syn_keeps on the LUT output
driving the select.
Brian Davis wrote:
> John_H wrote:
> >
> >I tried a MUXCY primitive redefinition (I called it MUXCYdammit) with
> >syn_hier="hard" like I did earlier with an FDRE but if you push down
> >into the instance in HDL_Analyst, there's a pass-LUT on the sel input.
> >
>
> By "redefinition", do you mean:
>
> A) put a MUXCYdammit wrapper with syn_hier="hard" around a MUXCY
>
> or,
>
> B) black box something called MUXCYdammit and edit the EDIF
> post-synthesis to fix up the primitive names
>
> I think "B" is fairly bulletproof, but you need a search-and-replace
> to fix up the EDIF names, and a wrappered simulation library to let you
> sim the primitives that have the tiny brown paper bags over their heads.
>
> Brian
>
> John_H <johnhandwork@mail.com> wrote in message news:<3D07B0CB.F77B1634@mail.com>...
> > I'm having MUXCY trimming problems *right now*. I tried to take my 29 MUXCY
> > instantiations and convert them into an array of instances. Yuck! The physical
> > implementation of my chain became toast once Synplify started "optimizing" the pass
> > elements out of the chain (I have several in the middle).
> >
> > The inclusion of oh-so-many LUT1_2 elements is getting at my nerves as well: I
> > tried a MUXCY primitive redefinition (I called it MUXCYdammit) with syn_hier="hard"
> > like I did earlier with an FDRE but if you push down into the instance in
> > HDL_Analyst, there's a pass-LUT on the sel input. Once again Synplify knows
> > better. Oy.
> >
> > The apps engineers are looking at my chain, but I imagine it's back to the 29
> > individual instances. I hope those aren't broken!
> >
> > - John_H
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44170
Hi all,
I am a newbie to digital computing, and for my project I had to program a
CPLD XC9536 or XC9572.
Resource I have:
Xilinx Webpack 4.2 (newest frok xilinx.com)
Xilinx Programming Cable IV
a break out board for PLCC44
a self-made 5 V regulator (I measured the output of my voltage supply, it's
4.98 V)
I kept getting errors like
"
ERROR:iMPACT:634 - Boundary-scan chain test failed at bit position '1' .
A problem may exist in the hardware configuration.
Check that the cable, scan chain, and power connections are intact,
that the specified scan chain configuration matches the actual hardware,
and
that the power supply is adequate and delivering the correct voltage."
=>
I have connected the JTAG pins, applied 4.98 V to VCCINT(21,41) and
VCCIO(32), and connect GND (10,23,31) to GND
and still I get this error, my status LED on my Paragram cable IV is shown
GREEN
really need help...
John
Article: 44171With the direct conversion radio you have designed... What kind of problems did you run into with DC offsets? Any problems with the DC causing swamping of the ADC range? I'm currently trying to implement one as a project for polytech. I haven't reached hardware yet, as I'm a little worried that all I'll end up with is a maxed out ADC. The current design has got a DDS as the LO, using quadrature outputs into two active mixers, to produce a baseband signal. +30dB LNA from analog devices as the frontend, with a 120MHz low pass filter just before it, to reduce the bandwidth a little... Further amplification after mixing, just before the ADC's to optimize the ADC's resolution. No point having a 16bit ADC and only really using 8bit of it... Any possible problems that I should be warned about?? "Ray Andraka" <ray@andraka.com> wrote in message news:3D07E8CC.C67268F0@andraka.com... > First, you might get a copy of Marv Frerking's Digital SIgnal Processing > in COmmunications Systems text. It is very well written, and if you are > into digital radio, is worth more than you pay for it. The ARRL Radio > Amateur's handbook is also a useful reference. > > The resolution of converters is more or less inversely proportional to the > max sample frequency. You can get 8 bit converters at 1GHz or more. 12 > bits seems to top out at a just a bit over 100MHz (the AD9432 is a 105 MHz > 12 bit converter). If you want more bits, you get lower sampling rates. > > With a limited number of bits in RF capable converters, you wind up with a > very limited (wrt the entire spectrum) dynamic range. For a practical > radio, you'll need a fairly narrow filter to block out strong signals near > the desired signal. 12 bits isn't much to quantize the entier RF > spectrum. If you have an analog front end, you can do this by mixing to > an IF where you can filter the signal with a high Q analog filter before > digitizing it, which is what you are doing. > > We've got a demo application in process that puts a direct conversion > digital HAM radio in a SpartanII-100. The entire radio consists of an > antenna tuner/preamp, a burr-brown ADC demo board, and insight SpartanII > demo board with a pair of RC filters and a phone jack added to it, and a > pair of PC speakers. The spartan has in it all the tuning, filtering > decimation, demodulation and a PWM output. It will do AM, SSB, DSB, AM > stereo and CW demodulation, with plans for FM later. It makes for a > pretty cool demo, although it is not all that practical because of the > limited dynamic range of the 12 bit ADC. I am hoping to get it in a state > suitable for showing for the MAPLD conference in Laurel MD in September. > > FM needs a complex baseband in order to recover the phase. In a digital > radio, you can mix your real-only digitized IF with a complex sinusoid and > then decimate it to make your filtering a whole heck of a lot easier. One > of the advantages of digital IQ separation is that you don't have the > phase and matching sensitivities you have with an analog IQ stage. With a > 10 KHz BW, you can decimate to a couple times that (pick a sample rate > that makes your filter easier). Once it is filtered, then you need to > recover phase from that complex baseband signal. Phase recovery can be > done by a number of methods, a conceptually simple one being to use a > CORDIC rotator to pull out phase and magnitude. > > jaideep wrote: > > > Hi Newsgroup, > > > > In continuation to my earlier post with the same subject, I would > > appreciate very much, if someone can provide me with the following > > answer: what is highest frequency analog signal that I can sample with > > the currently available data converters. I am considering 2 sampling > > rates; one Nyquist and the other 4x upsampling. > > > > Thanks to Noddy for providing the information. I forgot to mention > > that the IF signal (10.7 MHz +/- 125 KHz) contains FM data around > > another subcarrier located 70KHz from the center of 10.7 MHz. The FM > > data BW is 10 KHz around this subcarrier. Therefore I guess we need to > > have a very sharp BPF centered at 70 KHz with a BW of 10KHz.Invite any > > suggestion/discussion on this subject and also as how to implement > > this in FPGA. > > > > Thanks in advance. > > > > Jaideep Bose > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 44172
This is definately an easier way to go, and happens to be the same method I am using for radio astronomical applications. Although, I use an analogue complex mixer to mix down from IF. This eases up on power usage and timing issues considerably. Try use the AD6121 which has a nice 92 dB gain control. This should be easier than sampling at IF and then mixing down to get I/Q signals. adrian > The Hilbert transform will leave you a hole at DC if you are doing single conversion, > and can make for a complicated filter. FOr digital IQ separation, you are better off > using a complex mixer and then low pass filtering the I and Q outputs.Article: 44173
Hi all, in my design a EP20K200CQ240C7 gets his configuration from 2 EPC2. After configuration the APEX runs for ~500 ms then configuration restarts ~200 ms and so on. An endless loop ....... What may be wrong ? Thanks in advance MichaelArticle: 44174
> It makes for a > pretty cool demo, although it is not all that practical because of the > limited dynamic range of the 12 bit ADC. I am hoping to get it in a state > suitable for showing for the MAPLD conference in Laurel MD in September. What's to stop you from oversampling? Will increase your dynamic range by sqrt(N). adrian
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