Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
John, while there are many reasons to avoid tri-state multiplexors including their inability to schedule 100% b/w, that should not be an excuse for the tools to produce the wrong results. They have their place, and the tools should follow the language correctly. Synplify 7.03, and 7.1 beta with the default settings do not produce a tri-state bus where one is explicitly expressed. That is wrong and needs to be fixed. I would still like any advocate of the push-through convolution to explain how it is in either VHDL or Verilog that storage( the enable state register(s)) may occur without a signal or reg to hold the stored result. This seems to fly in the face of the LRM for both languages. I would also like to know if any of these advocates also believe that since 'Z' propagates through all memories, whether that means that the synthesizer should build a 'Z' state memory array in parallel to each data memory array if the data memory happens to have a tri-state bus at its input. This whole notion of propagating 'Z's through storage to match the simulation just seems an incredibly bizarre distortion. Regards, "John_H" <johnhandwork@mail.com> wrote in message news:3CA88F9A.C0968EFE@mail.com... > I didn't respond initially because of one underlying issue. Tristate multiplexers > are a design element best left in the past. The efficiencies aren't high in current > silicon with respect to performance and are only available (as far as I know) in one > brand of devices. If it weren't for legacy issues, I'd almost expect the feature > would've been dropped a generation or two ago. > > There are so many different approaches to multiplexing that - in my opinion - the > tools should concentrate on generic logic implementation issues. Non-generic items > that are used most frequently might benefit from optimization; tristate > multiplexing is just used less and less these days. > > > Aki Niimura wrote: > > > I still would like to have more responses from FPGA/ASIC designers. > > With few more responses, I will wrap up this petition and present to Synplicity. > > (However, developers in Synplicity are already following this petition.) > > > > The more I hear others' opinions, the more I feel that this is something > > Verilog standard didn't do a good job. I can find both "for" and "against" > > reasons in the standard. >Article: 41551
"D.A.Kopf" <dak@dakx.com> wrote in message news:<3CA8B732.ABB32B6B@dakx.com>... > > Not sure why you want a single algorithm for all these data types; I'd think > multiple algorithms sharing common routines and having the smallest footprint > would be the engineering choice. But http://dakx.com describes a lossless > method suitable for low-complexity FPGAs. It's not great for text, maybe > compression 80-90% of original without using a character remapping table, but > competitive for audio or video. This is exactly what I am trying to do.... find multiple algorithms sharing common routines and load the FPGA with appropriate bitstream stored in a Flash device (SystemACE?) or external memory + cpld based on data type. In other words, I am trying to design a Re-configurable compressor in a FPGA which is re-configured with compression algorithm based on data type (audio/video/text etc). Generally what kind of compression algorithms are used in Networks like IPSec, VPN etc. I think there should be somekind of data compression before network transmission. This is more like a research project to learn more about data compression and re-configurable computing. Thanks everyone for your valuable suggestions.Any further comments/suggestions would be greatly appreciated.Article: 41552
>IBM has a hardware compression chip with a patented algorithm. See: I believe that IBM end-of-lifed that chip last year. Don't know if it is possible to get your hands on any more parts. -- | | Mark Nelson - markn@ieee.org - http://www.dogma.net/markn | Dr. Dobb's Compression Resource - http://www.ddj.com/topics/compression | The Data Compression Library - http://www.dogma.net/DataCompression | Preview the New Library - http://datacompression.dogma.net | "glen herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:a8ajop$hk0@gap.cco.caltech.edu... lucky_hero@yahoo.com (VP) writes: >I am trying to find best general purpose data (text, audio, video and >other types) compression algorithm suitable for FPGA implementation. >On doing some research LZW compression and variations of LZ (LZ-77, >LZS etc) compression seems to be a good fit. Can someone point me to >other hardware based loss less data compression algorithms? Did anyone >implement data compressors in FPGAs? Any pointers/references would be >greatly appreciated. IBM has a hardware compression chip with a patented algorithm. See: http://www.google.com/search?q=cache:NMXQVGVNNR0C:www.ibm.com/chips/techlib/ techlib.nsf/techdocs/852569B20050FF778525697500612122+aldc+ibm&hl=en The most appropriate algorithm depends on how you need to use it? It may be that compression can be slow and decompression fast, or the other way around. That and cost constraints should help determine the best algorithms. -- glenArticle: 41554
In article <3CA8CA64.2FBBBBCE@algor.co.uk>, rick@algor.co.uk says... > > > "Keith R. Williams" wrote: > > Xilinx chose the right processor. ;-) > > > > > > Nah! It should have been one of the MIPS cores. Other people have other points of view. ;-) > > - Speaking as someone for whom the bigger the MIPS world, the bigger my earnings. Yep! My thoughts exactly! ;-) I may be looking to leverage some knowledge someday. Nice going Xilinx! ---- KeithArticle: 41555
In article <3CA8D347.47F2ED0E@mail.com>, johnhandwork@mail.com says... > CAM based LZ would be spectacular. I haven't seen that the Xilinx CAM > implementations allowed the width and breadth needed for a decent LZW > implementation (20 bits tag, 12 bits data, 4k elements per channel). Oh, to > have an embedded CAM with a worthwhile size! The IBM LZ (ALDC) chips started with a 512 byte CAM directory. Seems like that should be no problem for Virtex2. Even double or 4X seems like it shouldn't be a problem, depending on your budget. Though with LZ chips at dollar-store prices, I wouldn't suggest a real product using even middle-of-the-road V2's. ---- Keith ======================= > > "Keith R. Williams" wrote: > > > In article <3CA88D75.1468E42C@mail.com>, johnhandwork@mail.com says... > > > Performance LZW compression is a bear. The algorithm isn't friendly to > > > single channels at top performance and under most circumstances requires > > > an external SRAM (about 60 FPGA pins). It's achievable but not a project > > > for the feint of heart. > > > > What about a CAM based LZ? Xilinx has datasheets describing how to > > make a CAM out of BlockRAMs. The CAM sizes seem reasonable for LZ (512 > > to 1024 entries give reasonable compression) in the moderate sized > > Virtex-2. Unless the chip has a lot more to do than LZ, the cost is > > going to be outrageous though. > > > > ---- > > Keith > >Article: 41556
That is what I was inferring. By separating the design you can keep working
parts of the design untouched, and your synthesis run time is considerably
reduced. You lose the optimization across the boundaries, but then a good
partition shouldn't be affected anyhow.
Kevin Brace wrote:
> Although I am not sure if it will help, but what I will suggest
> is to create two separate project files for X and Y.
> Synthesize Y by itself, likely without I/O pads being inserted.
> Then, create a blackbox for Y in X, and synthesize X without Y.
> XST's user manual talks about how to declare a blackbox for a module.
> Copy Y's netlist (If you are using XST, which I will assume, a .ngc
> file.) to X's project directory, and run NGDBUILD.
> NGDBUILD should automatically find Y's netlist, and will attach it to X.
> You can put X and Y in the same directory to save time. (That way, you
> won't have to copy Y's netlist each time you make modifications to Y.)
> Now that X and Y are separated, you should be able to floorplan X and Y,
> and even if you make modifications to Y, X's floorplan information won't
> change. (In theory.)
> Regarding the Floorplanner, I find UCF flow easier to deal with than the
> regular flow.
> Speaking of my wish list for ISE WebPACK, I will like to see FPGA Editor
> being added to the future versions of ISE WebPACK.
> I know most people won't use such a tool, and if that's the case, that's
> fine with me, but I will probably use it to see how LUTs are being
> routed in my design.
>
> Kevin Brace (In general, don't respond to me directly, and respond
> within the newsgroup.)
>
> Spaced Cowboy wrote:
> >
> > I've been playing with the Webpack floorplanner this weekend, and have
> > created a few "planned" designs from modules within my verilog source. The
> > question is how to use those nice layouts within the encompassing module:
> > say for example I have module X that contains an instance of module Y. I've
> > floorplanned Y, how do I get X to use the floorplanned design for Y when
> > laying out X ?
> >
> > Any hints gratefully received.
> >
> > Simon
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 41557When I Try to install Service Pack1 on my machine(P3+Win98 OR P4+Win2000),I get a error Message: "Quartus II 2.0 Full Version is not install on this machine.The Service Pack set will exit now." But I had installed Full Version QuartusII 2.0 on my machine. Why?Article: 41558
this might not help since the saving of one square root is offset by the increase of multiplier data size. -- Best Regards, ----------------------------------------------------------------- Xu Qijun Engineer OKI Techno Centre (S) Pte Ltd Tel: 770-7049 Fax: 779-1621 Email: qijun@okigrp.com.sg "John_H" <johnhandwork@mail.com> wrote in message news:3CA4E0FC.C8BB4C6D@mail.com... > Minor help: > A little algebra can help with the size: make the denominator sqrt( > (a1^2+a2^2)*(b1^2+b2^2) ), reducing the resource count by one 32 bit square > root block. > > If you only need 8 bits output, you can provide an answer with slightly > greater error (1.5 LSbits instead of 0.51 LSbits) by limiting the size of the > intermediate results in a structured error analysis. > > Perhaps someone has a squaring method that takes up fewer resources than a > generic multiplier? > > Is the clock rate 200MHz or 20MHz? Are you using Virtex-II which has (did > you know?) built-in multipliers available? > > Engineers calculate a value to 9 digits, use a micrometer measure, mark with > chalk, and cut with an axe. > > > Max Edmand wrote: > > > Hello all, > > > > I'm trying to design a block to perform correlation > > on two vectors: A and B. (A and B each have two elements: > > A=(a1, a2) and B=(b1, b2) > > The correlation between A and B shoul be calculated like > > this: > > > > corr = [(a1 * b1) + (a2 * b2)] / [sqrt(a1^2 + a2 ^2) * sqrt(b1^2 + b2^2)] > > > > all a1,a2,b1,b2 are 16 bit wide and the result width needs to be 8 bits. > > in the first look one can say it needs: > > 16 x 16 bit miltiplier x6 > > 32 x 32 bit multiplier x1 > > 32 bit square root block x2 > > 32/32 bit divider x1 > > 32 bit adder x3 > > > > I built a block like that with 16x16 bit multipliers from > > Xilinx CoreGenerator but by far it exceeds the logic resources > > that I have available for this block. ( because I need so many > > of these blocks so the size of each block needs to be around > > 1000 - 1500 LUTs !) > > > > So, any idea or trick for an efficient implementation? > > I could not find a correlation Core in Xilinx's CoreGen IPs. > > > > The latency is not important but it needs to produce 1 sample/clk. > > > > Thanks, > > -Max Edmand >Article: 41559
Hello, I am evaluating FPGAs for my next project. Does anyone have a list of FPGAs, preferably from altera or Xilinx, and their pricing information and gate count info as well. Thank, JZArticle: 41560
Don't use "gate count" as a measure. For comparable architectures (most Xilinx and Altera FPGAs) use the flip-flop or LUT count ( usually the same number for both), and then consider the other good things, like Clock Enable, BlockRAM, multipliers, clock management, I/O versatility, clock distribution, etc. You should not compare Fords, BMWs and Ferraris on the basis of dollars per kg, neither should you compare different architectures on the basis of pennies per kilogate. It is more complicated than that. Peter Alfke ================================ j zhang wrote: > Hello, > > I am evaluating FPGAs for my next project. Does anyone have > a list of FPGAs, preferably from altera or Xilinx, and their pricing > information and gate count info as well. > > Thank, > > JZArticle: 41561
If you'd left out the "Webpack", this would all be really easy. The Altera tools can do this with the LogicLock feature, even exporting floorplanned modules to be used in other designs and in other devices. Practically unlimited parent-child-grandchild-etc relationships are supported. If you're not committed to Xilinx devices, you might want to take a look at Altera's solution. -Pete- Spaced Cowboy <cowboy@gornall.net> wrote in message news:271q8.13332$Jw2.66771@NewsReader... > I've been playing with the Webpack floorplanner this weekend, and have > created a few "planned" designs from modules within my verilog source. The > question is how to use those nice layouts within the encompassing module: > say for example I have module X that contains an instance of module Y. I've > floorplanned Y, how do I get X to use the floorplanned design for Y when > laying out X ? > > Any hints gratefully received. > > Simon > > >Article: 41562
Hello, I need information on how to choose the termination supply voltage (VTTX and VTRX) of the Virtex II Pro RocketI/O Tranceivers. Can I use the same regulator as for the auxilliary voltage (VAUXTX, VAUXRX) or is the termination supply depending on the desired signal standard...? Thanks, AndreasArticle: 41563
I'm looking for an introduction to floorplanning for FPGA designs. Can anyone suggest a good reference? I'm designing for a ALtera apex 20ke leonardo spectrum and quartus II ver 1.0 for UNIX Thanks!Article: 41564
Try the Mentor website under LeoSpec. I know they do some App. notes for Xilinx floorplanning in conjunction with LeoSpec. They'll almost certainly do some Altera stuff as well. Niv. sadik <sadik@controlnet.co.in> wrote in message news:b8c17961.0204020350.5f3d1f77@posting.google.com... > I'm looking for an introduction to floorplanning for FPGA > designs. Can anyone suggest a good reference? I'm designing for a > ALtera apex 20ke leonardo spectrum and quartus II ver 1.0 for UNIX > Thanks!Article: 41565
Hi, In creating a Macro from the current sheet in the Schematic Editor, the pins dont seem to be connecting properly, giving me undefined signals at the Macro level. The functionality of the original schematic remains correct, so I am assuming I am missing something simple during conversion to Macro. If anyone could help I would be most grateful. Thanks in advance, Andy.Article: 41566
In comp.arch.fpga sweir <weirsp@yahoo.com> wrote: > like any advocate of the Z push-through to explain how it is that in either > VHDL or Verilog we can have store a result without first declaring a Verilog > reg, or VHDL signal to hold that result? Nowhere in any of the code > examples I have seen is there a declaration of that stored result that > Synplify dutifully produces. Do these advocates recognize that their > position dictates a discrete 'Z' state register for every address location > in a memory array where the data input is a tri-state bus? Synthesis adds and removes registers all over the place though. Duplicated registers for fan-out control, removed registers for area optimisation, extra registers for state machine encoding, etc. The synthesis result should behave as described by the code, but it is rarely a direct mapping. (I'm not saying that I think Z push-through is correct, only that I think this is a weak argument.) I find the idea of Z push-through a bit silly. VHDL is a hardware description language; you use it to describe hardware. Now Synplify is changing the behaviour of the hardware to match the behaviour of the language. The roles seem a bit reversed here. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 41567
Hey Jeanan, you sound like the first person I have come across who is attepting to actually use System C in a design. What is the design and what is your route to silicon? What I don't get is your beef about the Handel-C language. You can get a copy of the Handel-C language reference manual from the Celoxica website. It's more comprehensive than the stuff I see from System C and a lot easier to use. I don't know where your interpretation of the 'industry standard' is coming from - not from designers. Noel go_stock_boy@yahoo.com (Jeanan Del) wrote in message news:<5e59ca1f.0203261002.5fb42c34@posting.google.com>... > When is Celoxica going to kill of this useless proprietary Handel-C > language in favor of moving to the industry standard SystemC ?? I've > done a couple of experiments with DK1 3.0 and the language is painful > to use, doesn't leverage C++ and once I do soemthing in Handel-C, I > can't use with any other design or verification tools, like I can with > SystemC. There's a germ of value in Celoxica stuff but not while it > is encumbered by a dead-end proprietary language. > > When are these guys going to get real ??Article: 41568
"Peter Alfke" <palfke@earthlink.net> wrote > IMHO, both PowerPC and ARM are too complex to be implemented as soft macros. Implementations of *integer subset*s of MIPS, ARM, and PowerPC architectures are not too complex to be implemented as soft cores. One can produce an integer MIPS-I soft core as "small" as MicroBlaze; and I have done a spreadhseet analysis/design study for an FPGA-optimized PowerPC Book I soft core that cost between 1200 and 2000 LUTs (1.3-2.2x the size of MicroBlaze), depending upon performance tradeoffs and whether or not you trap and emulate certain rare and expensive instructions. The only thing holding back fast (100 MHz) relatively compact (800-2000 LUTs) FPGA-optimized soft core implementations of subsetted commercial RISC instruction set architectures is the intellectual property landscape. I am surprised that certain processor IP companies, that lack a hard core programmable logic platform, and may therefore be losing certain design wins to ARM and PPC, have not yet launched soft FPGA-optimized processor core products. Perhaps they too think it infeasible or impractical. (My company would be pleased to demonstrate otherwise.) I predict that sooner-or-later all processor IP licensors will come to the realization that programmable logic has become the air that a great many of their designers breathe, and that eventually all processor IP licensors will offer or endorse FPGA-optimized soft processor core implementations of their ISAs. To not do so would be to surrender a quickly growing market segment to their competitors. I put that date around 2005. There is no defense against the ATTACK OF THE KILLER FPGAS! I also feel that binary translation (static or dynamic) will become important and then commonplace, both as a way to run legacy ISAs on streamlined FPGA-optimized cores, and as a way to run full ISAs on subsetted ISA implementations. Jan Gray, Gray Research LLC FPGA CPU News: www.fpgacpu.orgArticle: 41569
You should also not rely on the numbers contained in the data sheets for LUTs and/or FF. You need to count them as YOU see them not the manufacturers. Often the count IOB FFs and add LUTs for "arechitecture" reasons. Also, I find IO count as important as LUT count. I have an Excel spread sheet with some SpartanII, Virtex and Virtex II info. But it would be hard to use since the data was only written for me to sort through. The prices are a combination of web pricing which is always a little higher and quotes with no distinction. But if you would like it, I will be happy to send it to you. Email me to the address shown below. Rick Peter Alfke wrote: > > Don't use "gate count" as a measure. > For comparable architectures (most Xilinx and Altera FPGAs) use the > flip-flop or LUT count ( usually the same number for both), and then > consider the other good things, like Clock Enable, BlockRAM, > multipliers, clock management, I/O versatility, clock distribution, > etc. > > You should not compare Fords, BMWs and Ferraris on the basis of dollars > per kg, neither should you compare different architectures on the basis > of pennies per kilogate. > It is more complicated than that. > > Peter Alfke > ================================ > j zhang wrote: > > > Hello, > > > > I am evaluating FPGAs for my next project. Does anyone have > > a list of FPGAs, preferably from altera or Xilinx, and their pricing > > information and gate count info as well. > > > > Thank, > > > > JZ -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 41570
Hello, Can anybody tell me how to synchronize two asynchronous inputs? one method is pulse streching but in this the input should not change for some fixed time interval. But if the input is continuously changing at faster speed the input data will be lost.And we don't want that. Is there any other method by which we can hold the input data? Thanks and regards, AmitArticle: 41571
Have you tried PSoC? Most of these have a hybrid DSP/CPU core with
programmable logic in them which will allow you to implement your core logic
then the difficult part in DSP/CPU with plenty of RAM on-chip to boot.
Granted, these do not offer the programmable muscle of top-of-the-range
FPGA's but in most cases they are an ideal solution.
Regards,
Jose.
On Mon, 1 Apr 2002 16:59:09 +0100, VP wrote
(in message <529a044.0204010759.47985ae0@posting.google.com>):
> Hi all,
>
> I am trying to find best general purpose data (text, audio, video and
> other types) compression algorithm suitable for FPGA implementation.
> On doing some research LZW compression and variations of LZ (LZ-77,
> LZS etc) compression seems to be a good fit. Can someone point me to
> other hardware based loss less data compression algorithms? Did anyone
> implement data compressors in FPGAs? Any pointers/references would be
> greatly appreciated.
>
>
> Thanks
--
Looks like we're in for a bad spell of wether.
==============================================================
Posted with Hogwasher. Mac first, Mac only:
http://www.asar.com/cgi-bin/product.pl?58/hogwasher.html
==============================================================
Article: 41572"Amit Deshpande" <amitvlsi@hotmail.com> schrieb im Newsbeitrag news:325691ba.0204020647.6be7f0ec@posting.google.com... > Hello, > > Can anybody tell me how to synchronize two asynchronous inputs? It depends . . . > one method is pulse streching but in this the input should not change > for some fixed time interval. A common method is oversampling. For this you need a fast clock, at least so fast to give you two samples for the shortest pulse width (e.g. 1us minimum pulse width -> 2 Mhz). But when doing so, a effect called metastability can (and WILL!!) hit you. Do a websearch on this. The solution is to use a synchronizer which is nothing else than a one or two stage shift register after your sampling flipflop. > But if the input is continuously changing at faster speed the input > data will be lost.And we don't want that. If you want to capture short pulses with a slow clock, use a flipflop where its input is connected to HIGH and the clock is connectet to your fast pulse input. When there is a rising or falling edge, the flipflop will load a HIGH. You can sample this with your low frequency clock and after detection you can reset the flipflop asynchronous. -- MfG FalkArticle: 41573
It seems to me that personal attacks of all kinds are getting to be the norm in engineering discussions. No doubt we live in a mean spirited age. The world of professional sports is where we seem to learn protocol and etiquette, and rules for sportsmanship and fair play are sadly lacking. Exhibitionism, tantrums, and trash talk, are the new standards. It's okay to be competitive, but the kind of snide bickering and angry retorts plastered all over the discussion groups is really the equivalent of Mike Tyson biting off his opponent's ear. Competition is a good thing. It drives innovation and keeps us sharp. But competition should be constructive in nature rather than vindictive. Despite the evidence to the contrary there's a persistent fallacy that engineers think logically and are thus immune to emotional outbursts. Nothing could be further from the truth. We may get paid for the products of our cerebrums, but ultimately our motivations stem from our limbic systems. And in that context we have evolved no further than the guests on the Jerry Springer show. There are a lot of fear based corporate cultures out there and most of us know of at least one or two suicides among our ranks. It doesn't have to be that way. Notions of proper form, of gentlemanly conduct, are not merely the antiquated decor from a Victorian drawing room. They are essential to free and open discussion and to the exchange of ideas.Article: 41574
"Mark Nelson" <markn@ieee.org> writes: >>IBM has a hardware compression chip with a patented algorithm. See: >I believe that IBM end-of-lifed that chip last year. Don't know if it is >possible to get your hands on any more parts. That may be true. Though the reference was more to show the possibilities than to suggest actually buying one. The problem then is not to design so close as to infringe the patent. One project that I almost worked on needed a hardware decompression, but could have used a software compressor. The compression algorithm could use a large table to minimize the table size for decompression, and also simplify the decompression memory access. My favorite asymmetric compression system is the ICT algorithm used by JPL for Galileo. It runs on an RCA CPD1602, which has no multiply instruction, but decompression is done on earth, with a much larger computer. ICT is similar to a DCT algorithm, with the coefficients selected to minimize the number of '1' bits. -- glen
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z