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> Yes, but for ISE users moldelsim it's completely free of charge... How?? I have ISE, but on installation of ModelSim, I have to obtain a licence or installed with starter licence. Can I obtain a licence using the same registration code I used for installation of ISE? adrianArticle: 48951
I know this topic has come up before in this newsgroup, but can't seem to find it. I am busy designing a complex polyphase filterbank, N=8, together with FFT etc. etc. and some other post filter processing. I am going to make all post filter functions multiplexed. In order to do this, I am going to need an 8 phase clock. Now, running at 32 MHz, will I get away with using my clock to drive a 3bit counter and decoder, and using the outputs of the decode as my phased clocks? Is there a better way which won't lead to any clocking issues? thanks adrianArticle: 48952
how to decide on a chip ? "Brian Guralnick" <innerdimension@videotron.ca> wrote in message news:<80yt9.23295$Td.418509@wagner.videotron.net>... > If you want speed, go for the Altera Mercury, or Xilinx's latest stuff. > > ____________ > Brian Guralnick > innerdimension@hotmail.com > (514) 624-4003 > > > "M Pedley" <Pedley@talk21.com> wrote in message news:b34821cd.0210230245.3e5080db@posting.google.com... > > Thanks, > > > > The Altera Stratix does look quite good. I was possibly being a bit > > ambitious with my original spec as Xilinx only claim 800Mbps outputs > > when using their own fixed netlist cores. As long as it can run at > > 311MHz, 622Mbps Output Data Rate then that should be fine. > > > > Cost is not really an issue (as far as i know), i am under the > > impression that these FPGAs cost upto a few thousand dollars??, we are > > looking for the highest spec FPGA that best suits our requirements > > (High Speed Data comms with strict jitter tolerances). It is going to > > be used for simulating an ASIC without the time and money involved in > > immediately producing a test chip (around $1million!). > > > > MattArticle: 48953
Dear all, If you have any experience with design with virtex FPGAs, please read my mail. The power on of a virtex require a certain power-on ramp of the power supplies. Can you tell me how you did this? For my power regulation i'm thinking to use the low drop regulators of TI; UC385-1 and UC385-3. If you have any experience with VIRTEX's please send me a your experiences so i can reply on them if they are useful for me. Best regards, Nico FleurinckArticle: 48954
Article: 48955
Just download Quartus2 and MaxPlus2. Their download is free for the limited versions. You need to apply for a key that is valid for 3 month, then get the next. Rene Soul in Seoul wrote: > Besides that, does Altera offer any free software like Xilinx's WebPack? > I heard that Altera FPGA chips and demo boards are cheaper than it's > competitors, is it so? > >Article: 48956
On 27 Oct 2002 21:52:01 -0800, zhouchang2001cn@yahoo.com.cn (Zhou Chang) wrote: >A few mouth ago ,I've estimated the Fmax of a nomal design on Xilinx or Altera >chip . The result said Xilinx is a little fast Than Altear . > > Tsu ( ns ) Tco ( ns ) Tlut ( ns ) Fmax >Spartent II -5 0.7 1.3 0.7 96 M >Virtex E -6 0.63 1.0 0.47 137M >Virtex II -4 0.37 0.57 0.44 160M I distinctly recall achieving 350MHz in a real (albeit small) design in a Virtex II -5, all in behavioural VHDL, without hand placement. (A -5 isn't *that* much faster than a -4.) >Virtex II Pro -50.29 0.40 0.37 193M >APEX E -3 # 0.23 0.32 1.01 79M >APEX II -9## 0.33 0.23 0.7 112M >Stratix -7 0.011 0.202 0.527 153M Regards, Allan. > > > > > >"Brian Guralnick" <innerdimension@videotron.ca> wrote in message news:<L3yt9.23302$Td.417972@wagner.videotron.net>... >> However, for the 400Kbit internal ram, the Altera Stratix is probably the best & fastest solution. To get anything else cost worthy >> with over 400Kbit, you will need to connect to ZBTRam. >> >> ____________ >> Brian Guralnick >> innerdimension@hotmail.com >> (514) 624-4003 >> >> >> "M Pedley" <Pedley@talk21.com> wrote in message news:b34821cd.0210230245.3e5080db@posting.google.com... >> > Thanks, >> > >> > The Altera Stratix does look quite good. I was possibly being a bit >> > ambitious with my original spec as Xilinx only claim 800Mbps outputs >> > when using their own fixed netlist cores. As long as it can run at >> > 311MHz, 622Mbps Output Data Rate then that should be fine. >> > >> > Cost is not really an issue (as far as i know), i am under the >> > impression that these FPGAs cost upto a few thousand dollars??, we are >> > looking for the highest spec FPGA that best suits our requirements >> > (High Speed Data comms with strict jitter tolerances). It is going to >> > be used for simulating an ASIC without the time and money involved in >> > immediately producing a test chip (around $1million!). >> > >> > MattArticle: 48957
I have a signal which is passing from one clock domain to another. One clock is generated from the other using a DCM. Unfortunately MAP is smart enough to try and propagate the timing constraint on the source clock through to the other clock. I need to add a TIG to the relevant nets to stop this happening. The most sensible place for this would be in the VHDL source as I instantiate this particular component a number of times. I have tried the following but get an internal error in pack... am I doing something wrong, or is this a bug? (using 5.1sp2): signal foo : std_ulogic; attribute tig: string; attribute tig of foo : signal is ""; TIA, SimonArticle: 48958
Rene Tschaggelar napisal(a): >Just download Quartus2 and MaxPlus2. >Their download is free for the limited versions. >You need to apply for a key that is valid for 3 month, >then get the next. The key is valid 6 months. -- Pozdrowienia, Marcin E. Hamerla "If we can put a man on the moon, we can build a computer made entirely of recycled paper"Article: 48959
Thanks for the reply... I am working with a design that was done for an XC4062XL (I know, I know prehistoric but no option to upgrade). This chip has 8 BUFGs available that can be used for clocks or other signals according to the library guide. Two of the BUFGs were being used for clocks. I instantiated a BUFG primitive to get their GlobalReset signal off of the logic routing resources but with this change... the design seems dead.Article: 48960
"Zinnias" <revankar@cranessoftware.com> wrote in message news:8d0c938.0210280025.5a00b1@posting.google.com...
> how to decide on a chip ?
>
Altera's Mercury specializes in multiple PLLs and many 1.25GHz LVDS channels & dedicated 9 bit HW DSP blocks. It's very easy to
get high density complex designs to run above 270MHz on this chip.
Apparently, the new Altera Cyclone chips will run the same design easily at 240 MHz, but, these ICs are the cheapest in price by
far. Less than 1/5 the price of Xilinx component. The smallest one has only 1 PLL & the large ones have 2. It can only run it's
IO to 350Mhz LVDS. Altera also really fixed up it's boot prom interface which now uses 1 SO-8 chip where you design may now use
free room in the boot prom as general flash ram. This means if your design uses 2 megabits in the 4 megabit boot prom, you also
have 2 megabits spare flash ram without any other external components.
Question for Xilinx users: What's with all this talk of manual logic cell placement of designs. I have yet to do this once with
Altera's Quartus. It seems it always does a really good job at laying out the logic for best IO performance.
____________
Brian Guralnick
innerdimension@hotmail.com
(514) 624-4003
"Srinivas" <revankar@cranessoftware.com> wrote in message news:8d0c938.0210280025.5a00b1@posting.google.com...
> how to decide on a chip ?
>
> "Brian Guralnick" <innerdimension@videotron.ca> wrote in message news:<80yt9.23295$Td.418509@wagner.videotron.net>...
> > If you want speed, go for the Altera Mercury, or Xilinx's latest stuff.
> >
> > ____________
> > Brian Guralnick
> > innerdimension@hotmail.com
> > (514) 624-4003
> >
> >
> > "M Pedley" <Pedley@talk21.com> wrote in message news:b34821cd.0210230245.3e5080db@posting.google.com...
> > > Thanks,
> > >
> > > The Altera Stratix does look quite good. I was possibly being a bit
> > > ambitious with my original spec as Xilinx only claim 800Mbps outputs
> > > when using their own fixed netlist cores. As long as it can run at
> > > 311MHz, 622Mbps Output Data Rate then that should be fine.
> > >
> > > Cost is not really an issue (as far as i know), i am under the
> > > impression that these FPGAs cost upto a few thousand dollars??, we are
> > > looking for the highest spec FPGA that best suits our requirements
> > > (High Speed Data comms with strict jitter tolerances). It is going to
> > > be used for simulating an ASIC without the time and money involved in
> > > immediately producing a test chip (around $1million!).
> > >
> > > Matt
Article: 48961I recently bought a Spartan II 2S200 PCI card. The application we want to use it for, will be designed under linux and so will have to work under linux. I'm having difficulties to get the card running. I found sourecode for this driver, but it's for windows only, so a lot of header files can't be used properly. Can somebody help me to find a working linux driver for this card (or for a similar card, which i can change untill it works for me)? kind regards, Michael Van Oostende Suminvent - BelgiumArticle: 48962
FPGAs are basically like a custom logic chip that you get to define the logic.
An FPGA design is a digital logic design, which could be a microprocessor or
could be something much more application specific. Since it is digital hardware
design, it carries with it the need to possess certain hardware design skills in
order to do reliable design on it. Our current recommendation is that if your
application can be handled by a single DSP microprocessor, you should do it
there rather than in the FPGA. The talent needed for software DSP design is
easier to find and is cheaper. The FPGA becomes favorable when the required
data rates become hard to achieve in microprocessor based systems. See my
sidebar in the article by Brian Dipert in the Oct 3 issue of EDN (there is a
link to the article on my website).
Klemen wrote:
> Hi!
>
> I'm new to FPGA and i'd like to know for what kind of an aplication they are
> better suited than dsp or microcontroller. Is it more easy to design with uc
> an dsp or with FPGA?
>
> thanks
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48963
Use phased clock enables instead. Ie, the 32 MHz clock goes to everything, then
the divided clock enable controls the flip-flops on each phase. You can
substantially reduced the size of your filter bank by going to a digit-serial
architecture using distributed arithmetic since you have 8 clocks per sample to
work with.
Noddy wrote:
> I know this topic has come up before in this newsgroup, but can't seem to
> find it.
>
> I am busy designing a complex polyphase filterbank, N=8, together with FFT
> etc. etc. and some other post filter processing. I am going to make all post
> filter functions multiplexed. In order to do this, I am going to need an 8
> phase clock.
>
> Now, running at 32 MHz, will I get away with using my clock to drive a 3bit
> counter and decoder, and using the outputs of the decode as my phased
> clocks? Is there a better way which won't lead to any clocking issues?
>
> thanks
>
> adrian
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 48964On Mon, 28 Oct 2002 10:09:23 -0000, "Simon" <null@null.null> wrote: >I have a signal which is passing from one clock domain to another. One clock >is generated from the other using a DCM. Unfortunately MAP is smart enough >to try and propagate the timing constraint on the source clock through to >the other clock. > >I need to add a TIG to the relevant nets to stop this happening. The most >sensible place for this would be in the VHDL source as I instantiate this >particular component a number of times. > >I have tried the following but get an internal error in pack... am I doing >something wrong, or is this a bug? (using 5.1sp2): > >signal foo : std_ulogic; >attribute tig: string; >attribute tig of foo : signal is ""; It doesn't like the zero length string "". Try "true" or "1". Regards, Allan.Article: 48965
i download Xilinx ISE WebPACK version about 5.1i from the web,but it can not run on my computer,the operate system is windows 98.i don't know why?Article: 48966
On Mon, 28 Oct 2002 06:37:23 -0500, "Brian Guralnick" <innerdimension@videotron.ca> wrote: >"Zinnias" <revankar@cranessoftware.com> wrote in message news:8d0c938.0210280025.5a00b1@posting.google.com... >> how to decide on a chip ? >> > Altera's Mercury specializes in multiple PLLs and many 1.25GHz LVDS channels & dedicated 9 bit HW DSP blocks. It's very easy to >get high density complex designs to run above 270MHz on this chip. > > Apparently, the new Altera Cyclone chips will run the same design easily at 240 MHz, but, these ICs are the cheapest in price by >far. Less than 1/5 the price of Xilinx component. The smallest one has only 1 PLL & the large ones have 2. It can only run it's >IO to 350Mhz LVDS. Altera also really fixed up it's boot prom interface which now uses 1 SO-8 chip where you design may now use >free room in the boot prom as general flash ram. This means if your design uses 2 megabits in the 4 megabit boot prom, you also >have 2 megabits spare flash ram without any other external components. > > >Question for Xilinx users: What's with all this talk of manual logic cell placement of designs. I have yet to do this once with >Altera's Quartus. It seems it always does a really good job at laying out the logic for best IO performance. I rarely do it. But if you are pushing the limits of the device, it helps. Sometimes it is essential, particularly for designs above 200MHz or so (but that depends on the skill of the designer, the "skill" of the tools, and the particular part used.) I mentioned a 350MHz design in another post in this thread. It was done without placement, but I think that is atypical at that frequency. Block rams should often be hand placed, even in low frequency designs. There are relatively few block rams in a chip (and they're widely spaced across the die), so it's easy for the automatic placement algorithm to come up with something that is wildly "suboptimal". This doesn't seem to happen so badly with FF or LUTs (although I have seen several examples where 1 FF in a vector was placed on the wrong side of the chip, causing timing failures). The placer operation can be inferred from stopping the design flow and looking at the results in fpga editor. It starts by plonking everything down in the lower left corner of the die (or area group), then tentatively moving stuff about. If the placer score improves with the move, it saves the move. This can lead to the problem of "painting itself into a corner" in which a FF is in the wrong area, but it can't get to the right one because there is a big chunk of unrelated logic in the way. In my opinion (which probably isn't worth much, since I don't write placers, I write VHDL), there are two faults: 1. There is no feedback from PAR to MAP. When a design is close to full, MAP will map unrelated logic into the same slices, without any attention being given to the floorplan. This can make the design impossible to route. Changing the cost table won't help, because the damage is done before PAR. I usually fix this problem by changing the source so that MAP has to do something different. Another fix is massive redesign to avoid making the chip so full. 2. There is no feedback from routing to placement (within PAR). If a particular signal won't route to speed because of poor placement, there is nothing that the router can do. I sometimes fix this problem by either hard placement (LOC) in the UCF or relative placement (RLOC) in the source code. Changing the placer cost table can also work. I understand that adding feedback between these passes in the design flow would increase the complexity so much that it would probably make the tools so bug ridden that they would be useless. So for the "few" designs (~100% of mine!) that show up these flaws in the tools, we must work around them. But I don't think that most users are affected that much. YMMV. Placement can also speed up PAR runtime. You can give the tools a design with the hard bits already worked out, so they don't waste any time working on those bits. I hope this doesn't sound too pessimistic. I (and many other designers) frequently use the tools quite successfully without too much manual guidance. Regards, Allan. >____________ >Brian Guralnick >innerdimension@hotmail.com >(514) 624-4003 > > >"Srinivas" <revankar@cranessoftware.com> wrote in message news:8d0c938.0210280025.5a00b1@posting.google.com... >> how to decide on a chip ? >> >> "Brian Guralnick" <innerdimension@videotron.ca> wrote in message news:<80yt9.23295$Td.418509@wagner.videotron.net>... >> > If you want speed, go for the Altera Mercury, or Xilinx's latest stuff. >> > >> > ____________ >> > Brian Guralnick >> > innerdimension@hotmail.com >> > (514) 624-4003 >> > >> > >> > "M Pedley" <Pedley@talk21.com> wrote in message news:b34821cd.0210230245.3e5080db@posting.google.com... >> > > Thanks, >> > > >> > > The Altera Stratix does look quite good. I was possibly being a bit >> > > ambitious with my original spec as Xilinx only claim 800Mbps outputs >> > > when using their own fixed netlist cores. As long as it can run at >> > > 311MHz, 622Mbps Output Data Rate then that should be fine. >> > > >> > > Cost is not really an issue (as far as i know), i am under the >> > > impression that these FPGAs cost upto a few thousand dollars??, we are >> > > looking for the highest spec FPGA that best suits our requirements >> > > (High Speed Data comms with strict jitter tolerances). It is going to >> > > be used for simulating an ASIC without the time and money involved in >> > > immediately producing a test chip (around $1million!). >> > > >> > > Matt > >Article: 48967
> Use phased clock enables instead. Ie, the 32 MHz clock goes to everything, then > the divided clock enable controls the flip-flops on each phase. You can > substantially reduced the size of your filter bank by going to a digit-serial > architecture using distributed arithmetic since you have 8 clocks per sample to > work with. Thanks for the advice... I do have one question though regarding the clock enables (I may be mixing up something, though). Consider a sub-filter in the polyphase filterbank. What you are saying, I think, is that I should send the 32MHz clock signal to the sub-filter clock input, and then use a phased clock at the enable? How do I make sure that the filter is enabled before the clock edge arrives since the 32 MHz clock will be driving both the sub-filter, and the 3bit decoder (which forms the phased signal)? Unless I use a negative edge triggered clock input on the sub-filter? Thanks adrianArticle: 48968
> It doesn't like the zero length string "". Try "true" or "1". I don't believe it's that... just tried it anyway (I think old versions of XST needed "yes" as the string, but that may just be folklore): ERROR:TSDatabase:40 - One or more TIG directives were specified for a specification with TSid "true", which does not exist. btw, with: attribute tig of foo : signal is ""; the error I am getting is: INTERNAL_ERROR:Pack:pksbatsdesign.c:575:1.14 - global TIG has no NC_SIGNAL reference SimonArticle: 48969
Hi, Please take into consideration the latest speed grades for Stratix the -5 and you will see some blazing fast preformance. (Just to compare Xilinx and Altera on there respectivly fastes FPGA's to be fair). Fredrik zhouchang2001cn@yahoo.com.cn (Zhou Chang) wrote in message news:<2ccc49b.0210272152.4a6e4206@posting.google.com>... > A few mouth ago ,I've estimated the Fmax of a nomal design on Xilinx or Altera > chip . The result said Xilinx is a little fast Than Altear . > > Tsu ( ns ) Tco ( ns ) Tlut ( ns ) Fmax > Spartent II -5 0.7 1.3 0.7 96 M > Virtex E -6 0.63 1.0 0.47 137M > Virtex II -4 0.37 0.57 0.44 160M > Virtex II Pro -50.29 0.40 0.37 193M > APEX E -3 # 0.23 0.32 1.01 79M > APEX II -9## 0.33 0.23 0.7 112M > Stratix -7 0.011 0.202 0.527 153M > > > > > > "Brian Guralnick" <innerdimension@videotron.ca> wrote in message news:<L3yt9.23302$Td.417972@wagner.videotron.net>... > > However, for the 400Kbit internal ram, the Altera Stratix is probably the best & fastest solution. To get anything else cost worthy > > with over 400Kbit, you will need to connect to ZBTRam. > > > > ____________ > > Brian Guralnick > > innerdimension@hotmail.com > > (514) 624-4003 > > > > > > "M Pedley" <Pedley@talk21.com> wrote in message news:b34821cd.0210230245.3e5080db@posting.google.com... > > > Thanks, > > > > > > The Altera Stratix does look quite good. I was possibly being a bit > > > ambitious with my original spec as Xilinx only claim 800Mbps outputs > > > when using their own fixed netlist cores. As long as it can run at > > > 311MHz, 622Mbps Output Data Rate then that should be fine. > > > > > > Cost is not really an issue (as far as i know), i am under the > > > impression that these FPGAs cost upto a few thousand dollars??, we are > > > looking for the highest spec FPGA that best suits our requirements > > > (High Speed Data comms with strict jitter tolerances). It is going to > > > be used for simulating an ASIC without the time and money involved in > > > immediately producing a test chip (around $1million!). > > > > > > MattArticle: 48970
Hi, There is a learning curve but it is no big think to get used to Alteras software. There is indeed a free version of QuartusII avalible called QuartusII Web Edition, this software supports all familys but not all densities. Full information is avalible on Alteras Web. Cheers Fredrik "Soul in Seoul" <Far@East.Design> wrote in message news:<3dbcedf0$1@news.starhub.net.sg>... > Besides that, does Altera offer any free software like Xilinx's WebPack? > I heard that Altera FPGA chips and demo boards are cheaper than it's > competitors, is it so? > > > > > Friends may come and go, but enemies accumulate. > "Soul in Seoul" <Far@East.Design> wrote in message > news:3dbced5e@news.starhub.net.sg... > > Hi, > > > > I am an intermediate with Xilinx softwares like ISE 4.2 and ISE Webpack. I > > did a few designs also. > > I want to know whether it will take a lot of learning to get used to > Altera > > softwares? > > > > Will it be like a computer amateur to switch from Macintosh to Windows? > > > > > > > >Article: 48971
Petter, Tom, Thank you both for these suggestions. The higher-end devices that I know will handle these devices tend to be $750 and up, while they are good value for what all they do, that's more than I'm comfortable spending at this time. Both the Roman-Jones programmer and the parallel cable solutions both look to be just right for what I'm seeking. (I already have the Parallel Cable) One question, Petter, I use the parallel cable all the time for JTAG download to my test FPGA, and also for ChipScope... but I don't know how to go about using it to program the SPROM. Is there an AppNote or something that explains how to do this... or where should I start my learning ? Will I also need to write some software ? Thanks, -rajeev- Petter Gustad <newsmailcomp3@gustad.com> wrote in message news:<873cqub5m8.fsf@filestore.home.gustad.com>... <...> > The parallel cable is of course cheaper than the MultiLinx (USB, and > serial). If you don't have ISP support you can wire up a DIP socket > and make your own programmer. > > PetterArticle: 48972
SH7
Let me try updating ModelSim as you suggest. I did notice lots of
X's...
I found out my outputs are not "stuck" at their first computed
values from the test bench. They are stuck at the initial register
values specified in the project. I can make all those permanent "zeros"
at the outputs into "ones" (that never change ...).
Thanks,
Bill
Spam Hater wrote:
>
> Bill,
>
> Did you install the ModelSim library updates? The ones that come in a
> zip file so there's no way to back them out?
>
> If so, that's your problem. I had to re-install ModelSim to get rid
> of them to fix the same problem.
>
> Dig into the waveform of the post-fit cpld, and you will see way too
> many X's on the signals.
>
> SH7
>
> On Sun, 27 Oct 2002 15:07:59 GMT, Bill Turnip <BTurnip@wellspring.org>
> wrote:
>
> >Hello group:
> > I'll try to keep this short. I have a simple asynchronous Verilog
> >module that takes 3 inputs to produce a few simple outputs.
> >Behavorially, the module works fine. I pumped the design through
> >WebPACK and targeted an FPGA as well as a CPLD. Behavorially, the
> >post-PAR and post-fit models simulate and match the behavorial model
> >(now with various delays, of course). To switch back and forth between
> >FPGA <> CPLD I simply changed the "properties" of the project, and
> >re-synthesized, etc. The verilog code for the module being implemented
> >as well as the testbench were the same for both the FPGA and CPLD
> >cases. I let the Xilinx IDE handle all the background stuff for the
> >ModelSim simulations of the post-PAR, post-Fit models.
> > So, I then made the design synchronous - added a clock as well as a
> >reset and made small modifications to the testbench - and repeated the
> >exercise above. The FPGA implementation works fine, with the behavorial
> >functionality matching the post-PAR (and post-map, post-translate, etc.)
> >functionality, now with delays of course. However, the post-fit CPLD
> >implementation does not work functionally at all! Again, I am using the
> >same testbench and verilog code for the two synchronous
> >implementations. It seems the post-Fit CPLD design is "stuck." The
> >outputs are correct for the first set of inputs passed to it from the
> >testbench, but after this they never change, as if time is not passing.
> >But the same exact code works for the FPGA! I'm new to this area, but
> >it doesn't seem to make sense. Do I need to do something special for
> >the clock or reset in the post-Fit code for the CPLD that is transparent
> >for the FPGA? I expected the CPLD implementation to be easier and less
> >complicated.
> > Thanks for any insight to this very interesting issue.
> >- BT
Article: 48973Hi all, I`m using Foundation 4.1i and during implemenation (for any device type) I`m getting the following error: ERROR:Map:40 - Problem encountered invoking program "m1map". m1map: Invalid argument. I`ve ensured my path variables are set correctly but this doesnt seem to solve the problem. Any help much appreciated. Cheers, Andy.Article: 48974
On Mon, 28 Oct 2002 14:22:35 -0000, "Simon" <null@null.null> wrote: >> It doesn't like the zero length string "". Try "true" or "1". > >I don't believe it's that... just tried it anyway (I think old versions of >XST needed "yes" as the string, but that may just be folklore): > >ERROR:TSDatabase:40 - One or more TIG directives were specified for a > specification with TSid "true", which does not exist. > > >btw, with: >attribute tig of foo : signal is ""; > >the error I am getting is: >INTERNAL_ERROR:Pack:pksbatsdesign.c:575:1.14 - global TIG has no NC_SIGNAL > >reference I just looked at the manual. It said to use: attribute tig of signal_name : signal is "value"; where "value" can be: - Empty (global TIG that blocks all paths) - A single TSid to block - A comma separated list of TSids to block It would seem that "" matches the first of these. However, that doesn't mean that it will work with the particular synthesiser that you are using. I guess you need to try giving it a valid TSid next. Regards, Allan.
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