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Not reliably. The HC7404 works because it is used as an amplifier, which can
be done with a simple inverter. An FPGA has too many gain stages between the
pins to be abused as an amplifier in an oscillator circuit. While it may work
on the bench, it will not reliably start and maintain the fundamental
frequency with variations in temp, process, and voltage. Why not use an
integrated xtal oscillator instead of a simple crystal? The costs are nearly
the same.
Dan wrote:
> Hello,
>
> My design has a common low cost crystal oscillator. It uses two inverters
> HC7404 and a few caps & two res.
>
> Can the inverter chip be replace by the FPGA. Can I simply put the crystal
> across two IO pins ( I am using a Spartan IIE ) and configurae them as an
> inverter ( while keeping the caps and the res(s) ) ?
>
> Sincerely
> Dan
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47251Hi, i want to take a look at the fpga systems to learn something more about. So I want to buy a development package but they are all so expensive. Isnīt there any cheap development package where i donīt to spent so much money or maybe a computer simulation of such an fpga chip? Thanks FrankArticle: 47252
In article <3d8bddff$0$18874$afc38c87@news.optusnet.com.au>,
hamish@cloud.net.au writes:
|> "Giuseppe?" <gziggio.pleasedontsendmeanything@tin.it> wrote:
|> > The only doubt that I have is that I use the Suse Linux and Xilinx required
|> > Red Hat.
|>
|> I don't see anything about Red Hat-specific about the installation
|> process; you just run the installer under Wine. It should work in SuSE,
|> Debian, etc just fine.
|>
|> Having said that, I tried it under Debian and didn't get too far. The
|> installer got to the part where it would copy the files, then sat at 0%
|> forever. The progress bar kept changing colour but never increased
|> beyond 0%.
That is maybe related to the (sorry Xilinx) crappy installer which runs under
Java. I always had problems with it (even under Solaris). I have made my own
installation script by directly calling the installer-class, much faster than
the GUI: http://wwwbode.cs.tum.edu/~acher/xilinx/
I will never understand why an installation needs Java, since a simple .tar.gz
(like in the early days of Xact) is much faster and user friendly than the
current colorful, Valium-installation.
--
Georg Acher, acher@in.tum.de
http://wwwbode.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 47253Georg Acher <acher@in.tum.de> wrote: : I will never understand why an installation needs Java, since a simple : .tar.gz : (like in the early days of Xact) is much faster and user friendly than the : current colorful, Valium-installation. The java parts of webpack aren't the biggest things since sliced bread neither... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 47254
Frank Adalater <localfun66@hotmail.com> wrote: : Hi, : i want to take a look at the fpga systems to learn something more about. So : I want to buy a development package but they are all so expensive. Isnīt : there any cheap development package where i donīt to spent so much money or : maybe a computer simulation of such an fpga chip? Xilinx Webpack is available for free, and some chips from families webpack can programm begin to show up at the catalogue distributors ( e.g. Spartan II at www.schukat.de) Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 47255
Thanks for the practical advice Ray. DanArticle: 47256
Altera provides a free version of the Quartus II Web Edition software which supports both FPGA's and CPLD devices. The software is available for download from: http://www.altera.com/products/software/pld/products/quartus2/sof-quarwebmai n.html Information about Development boards is available at: http://www.altera.com/products/devkits/kit-dev_platforms_partner.html http://www.altera.com/products/devkits/kit-dev_platforms.html Please be sure to match the development kit with the devices supported in the Quartus II Web Edition Software. - DS "Frank Adalater" <localfun66@hotmail.com> wrote in message news:ami2co$5pb3f$1@ID-34826.news.dfncis.de... > Hi, > > i want to take a look at the fpga systems to learn something more about. So > I want to buy a development package but they are all so expensive. Isnīt > there any cheap development package where i donīt to spent so much money or > maybe a computer simulation of such an fpga chip? > > > > Thanks Frank > >Article: 47257
Ray Andraka wrote: > Not reliably. The HC7404 works because it is used as an amplifier, which can > be done with a simple inverter. An FPGA has too many gain stages between the > pins to be abused as an amplifier in an oscillator circuit. While it may work > on the bench, it will not reliably start and maintain the fundamental > frequency with variations in temp, process, and voltage. Why not use an > integrated xtal oscillator instead of a simple crystal? The costs are nearly > the same. Amen. Could not be said better... XC3000 has a dedicated single-stage amplifier between XTAL1 and XTAL2 pins. But no other FPGA family has repeated that dubious feature. Peter AlfkeArticle: 47258
You can try Xilinx ISE WebPACK and ModelSim XE-Starter for free
from Xilinx.
http://www.insight-electronics.com/cgi-bin/bvutf8/memec/scripts/local/mc_loc_b.jsp?Div=INSIGHT&Reg=AMERICAS&Country=UNITED_STATES&Lang=EN&EDOID=168749&Manu=XILINX
Insight Electronics has several Spartan-II-based low cost (below $300)
development kits.
http://www.insight-electronics.com/cgi-bin/bvutf8/memec/scripts/local/mc_loc_a6.jsp?catPath=/INSIGHT/AMERICAS/UNITED_STATES/MANUFACTURERS/XILINX/EVALUATION_KITS&Manu=XILINX&Div=INSIGHT&Reg=AMERICAS&Country=UNITED_STATES&Lang=EN&isDetailPage=true
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Frank Adalater wrote:
>
> Hi,
>
> i want to take a look at the fpga systems to learn something more about. So
> I want to buy a development package but they are all so expensive. Isnīt
> there any cheap development package where i donīt to spent so much money or
> maybe a computer simulation of such an fpga chip?
>
> Thanks Frank
Article: 47259I haven't purchased an FPGA yet, but there are many low cost development boards based on the Spartan II/Spartan IIE that I've found. I don't own or have experience with any of them though. www.digilentinc.com - has a Spartan IIE board for around $100.00 www.xess.org - A variety of boards at different prices. www.insightelectronics.com - The only low priced PCI board I've found -- around $250. Spartan II part. www.nuhorizons.com - As near as I can tell, they are selling the same board as digilent. www.burched.com.au - $179 US for their Spartan IIE, 300k gate FPGA board. Lots of add-ons available. http://www.altera.com/education/univ/unv-kits.html - If you're enrolled in a unviersity, you may qualify for Altera's university program. The only low priced altera board i've found so far. "Frank Adalater" <localfun66@hotmail.com> wrote in message news:ami2co$5pb3f$1@ID-34826.news.dfncis.de... > Hi, > > i want to take a look at the fpga systems to learn something more about. So > I want to buy a development package but they are all so expensive. Isnīt > there any cheap development package where i donīt to spent so much money or > maybe a computer simulation of such an fpga chip? > > > > Thanks Frank > >Article: 47260
"Ray Andraka" <ray@andraka.com> wrote in message
news:3D8C5646.E15B5035@andraka.com...
> Looks like part of the performance problem in v4.2 is a
> reappearance of the so called RPM zippering problem. That
> is, if you have flip-flops placed with RLOCs, then use
> synthesized LUTs you would expect the placer to place the
> LUTs in the slices with the flip-flops. It does not, so in
> a design where you've placed the flip-flops in a dense
> pattern, you'd espect good performance. Instead,the placer
> is putting the LUTs outside of that dense pattern, killing
> the density and performance. (this was a problem with early
> versions of the M1 floorplanner that finally was fixed in
> the 3.1 tools). Has anyone else seen this?
Yes, I've seen this. In some cases you can work around this problem by going
to the extra trouble of explicitly technology mapping your logic into LUTs
which you add to the RPM.
[[[But, in some cases, (like FFs following RAMs in a slice), I have seen the
mapper refuse apparently legal packings of location constrained
primitives -- even packings it assigns on its own accord if the RLOCs are
removed. (Seeing this makes me wonder if there isn't a phase-ordering
problem in the software.) So then you remove the RLOCs on the FFs and pray
the mapper puts the unconstrained FFs into the same slices as the
now-constrained LUTs. It's like pushing on a rope!]]]
Since I was astonished that the tools did not appear to merge RPM FFs and
non-RPM LUTs, I did some experiments. These demonstrated that MAP/PAR
*will* merge non-RPM LUTs and RPM FFs, under duress, e.g. when the device is
almost full and the pack will otherwise fail. So I attribute this problem to
some placer code which (suboptimally) penalizes/scores merging non-RPM LUTs
and RPM FFs, even in areas where there is little congestion.
Here "suboptimally" ::= wasting slices and interconnect ("but who cares if
there are slices to spare?") and worse, increasing delays and wasting
power through unnecessary use of non-local interconnect.
If anything, the presence of a placement-constrained FF should subtly
influence placement scores such that, all things being equal, the LUT that
drives the FF is "attracted" to the same slice as the FF.
Of course, what may seem like poor results (or bugs) to expert users may in
fact simply reflect algorithms that have been tuned for push button
synthesis users, or to reduce PAR time, despite effort level "5" --perhaps
revealing a paucity of RPM examples in the tuning (or regression) test
suites.
This is not encouraging:
"5.1i Virtex-II MAP - Designs with very large RPM macros may experience long
MAP run times":
http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=
1&getPagePath=15096
but note that 5.1i SP1 is now "out".
I have yet to receive 5.1i. Xilinx reports it was shipped to me on 9/4, so
it shouldn't be long now...
Jan Gray, Gray Research LLC
Article: 47261
As far as I am concerned, mapping the LUTs into slices with placed FF's is low
hanging fruit. There is no excuse for not doing this simple step (and checking
to see that it works). This had been a problem with the original floorplanners
in M1, and it finally got fixed in 3.1. Now it is broke again. I am aware that
I can instantiate the LUTs so as to place them too. Really don't want to do
that though. The flip-flops are in one of our library elements (d_register)
which gives us a placed register with parameterization to control the placement
pattern (row first, or column first arrays with independent row and column
pitches, settings for virtex, virtexII or no placement, etc). The logic
function that goes before is a one-line concurrent statement that is simple to
read...changing that to placed luts obfuscates the code, and requires a fair
amount of effort to match the FF placement patterns. I'll try putting an area
constraint on the LUTs to force them into the same slices as the registers.
Worse yet, it busts up the coregen macros like that too...at least the async
fifo. In that case one is forced to either accept the speed/power/density
penalties (I can't) or write their own. This is precisely why we use our own
multiplier macros now. I fear what else they might have broken in 5.1i in the
name of the mythical push-the-big-green-button beast. One of the features I am
not looking forward to in 5.1 is the reported slowdown with big RPMs. There is
one in this particular design with over 35,000 flip-flops in it.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 47262Georg Acher wrote: > In article <3d8bddff$0$18874$afc38c87@news.optusnet.com.au>, > hamish@cloud.net.au writes: > |> Having said that, I tried it under Debian and didn't get too far. The > |> installer got to the part where it would copy the files, then sat at 0% > |> forever. The progress bar kept changing colour but never increased > |> beyond 0%. > > I will never understand why an installation needs Java, since a simple .tar.gz > (like in the early days of Xact) is much faster and user friendly than the > current colorful, Valium-installation. I too detest the flashy installer. RPMS are so much easier and to the point, even a simple zip of the xilinx directory (and a teensy setup to set a few pertinent registry/environment variables) should work as well as anything els. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." abuse@xo.com uce@ftc.govArticle: 47263
Giuseppeģ wrote: >>If you want a stable work environment, start getting used to the >>idea of moving to Linux. >>-- >>Steve Williams "The woods are lovely, dark and deep. > > > This is exactly what I think to do. > The only doubt that I have is that I use the Suse Linux and Xilinx required > Red Hat. > > I don't know the technical question that induced Xilinx to drop NT but they > are very strange. > By now I have to put 2 OS on my desktop because old uP emulator doesn't work > on W2000 and the up to date of the software is not possible and convenient. Hmm. I'm not having much luck with Linux, either. I've got a fresh install of Redhat 7.3, and tried with both the bundled wine, and the cvs version, and both crash when trying to run the installer 'Setup.exe' :-( This is using the no-genuine-windows-dll's option. Anyone who's got it working care to post some configurations ? Cheers, SimonArticle: 47264
I would like to use a push-button switch (either normally open or normally closed) to drive a logic one (3V) or logic zero to a Xilinx CoolRunner XPLA3 CPLD. The input current should be no more than a few uA. Can anyone suggest a circuit for this using my switch, 3V supply, and hopefully just a small amount of resistors (and caps, if necessary)?Article: 47265
Try Palmchip. They do SoC, but will also just sell the cores. Then you can just hardcode and use squencer to bypass the usual embedded processor. "frank" <maddog@etang.com> wrote in message news:2b32768a.0209201200.70d86885@posting.google.com... > Hi, > I want make a hard disk drive from SDRAMs,which use IDE interface to > connect to pc.and have a battery to keep the data when power off. > is there any logic core for FPGA-IDE interfaceing?? > any one have try that before?? > please give me some suggestion, thank a lot!!!Article: 47266
I can't find it on Xilinx Web site .Article: 47267
John wrote:
>
> I would like to use a push-button switch (either normally open or
> normally closed) to drive a logic one (3V) or logic zero to a Xilinx
> CoolRunner XPLA3 CPLD. The input current should be no more than a few
> uA. Can anyone suggest a circuit for this using my switch, 3V supply,
> and hopefully just a small amount of resistors (and caps, if
> necessary)?
See also other postings on this
The smallest/simplest switch connection is using a SPCO
Vcc -----\
o--------- PIN
GND -----
This works best with a pin-keeper, and draws no current in either
state.
It also has bounce-removal.
Some CPLDs have symmetric pinkeepers built in, on the others,
you can drive the OP-IP to create a pinkeeper.
For SPNO (tact ) type switches, you need a pullup (10-100K),
and then Icc is drawn when pressed, and you also have
bounce to handle.
If you want a 'clean edges' signal, then use a TinyLogic HC1G14 and
a pullup, plus series RC to filter the bounce.
- jg
Article: 47268Normally open w/ 10K pullup, other side of switch to ground, is the most common, I think. Invert the input at top level. You will want to provide logic to reduce metastability and debounce using your clock signal. You can use a simple up/down counter to do both. Experiment with the count. Then you don't need any RC and schmitt trigger to do the debouncing externally. "John" <jjjkkl@hotmail.com> wrote in message news:4a50e479.0209211542.118aab7a@posting.google.com... > I would like to use a push-button switch (either normally open or > normally closed) to drive a logic one (3V) or logic zero to a Xilinx > CoolRunner XPLA3 CPLD. The input current should be no more than a few > uA. Can anyone suggest a circuit for this using my switch, 3V supply, > and hopefully just a small amount of resistors (and caps, if > necessary)?Article: 47269
I've just spent the last week in hell, baffled as to why my FPGA design was not working. Was I really THAT bad of a VHDL coder? To make a long and painful story short, it wasn't my fault. And it wasn't Synplicity's fault (sorry about that call to tech support). It is Xilinx's fault. I don't mean to bash Xilinx, as their products are great, but they blew this one. The problem: When using JTAG to configure a Spartan II FPGA (and perhaps Virtex too), the first configuration after power up will work, but subsequent ones will not. Worse, the re-configurations may APPEAR to work, because something did get downloaded, and the Impact programmer chirps "PROGRAM SUCCEEDED". But after 3 days of dissecting your code and backing all the way out to a trivial case (e.g. hard set a few output pins to 01010101 or some such), you'll find as I did that the part just did not get reprogrammed correctly. The problem is that the FPGA needs to have its configuration memory cleared before starting a new download, and the JTAG configuration inexplicably neglects to do this. Whether this is an oversight in the Impact downloader and can be fixed in a subsequent release (I'm using 4.2wP3.x), or whether it is an oversight in the chip design, I don't know. What you have to do is this: before reprogramming the FPGA via JTAG, you must pull the PROGRAM_BAR pin low (that clears the memory), and then bring it back high (if you leave it low, Impact will give you an error, saying the boundary-scan chain test failed). That you can't just use the JTAG pins to reprogram the part, and have to do this little dance with the PROGRAM pin is a flat out bug in my opinion. It should be fixed, or this workaround printed in 24-point red letters in the user's manual. I sincerely hope this posting helps some future poor sap(s) from wasting as much time as I did. -tdArticle: 47270
Simon Gornall wrote: > Duane Clark wrote: > >> Simon Gornall wrote: >> >>> Up until now I've been using the Webpack software available free from >>> Xilinx. I'm actually pretty happy with it - the sole problem is that >>> I have to reboot into Windows to run it ... this is a major reason >>> for me choosing to "do something else" :-) >>> >>> I noticed that ISE 5.1 is available under linux (hurrah!) at last, >>> and was wondering: >> >> >> >> As mentioned above (in "ISE 5.1 Linux?", ISE 5.1 needs Wine to run. >> WebPack will actually install and run under a current CVS version of >> Wine too. I run it and the similar ISE program manager. They both >> actually work pretty good. > > > Hmm. My "mileage varies". I get a crash either when running > 'wine WebPACK_42wp30_fpga_installer.exe', or when unpacking that with > unzip, and running 'wine Setup.exe'. Notepad seems to work fine, so I > suppose it's just not working with the fpga stuff :-( I get a few > dialogue boxes on the screem, then it tells me: > > fixme:seh:check_resource_write Broken app is writing to the resource > data, enabling work-around > > .. and the InstallShield dialgoue box complains about a missing engine. > > It's possible this is the OS - I'm running Mandrake 8.2 at home, but > I'll give it a go on the Redhat 7.3 in the office tomorrow. Well, I installed a clean redhat 7.3, downloaded the Redhat Network fixes, and compiled the latest CVS of wine. All seemed to go well. The bad news is that the installer won't. It crashes as it tries to open the splashscreen on install. I tried backing-out the CVS version of wine, and re-installing the Redhat-bundled one, and this had the same problem :-( I tried enabling the opengl extension in the CVS version, in case that would help (!) but still no joy. The CVS version of wine I'm using claims to be: [simon@atlantis ~/webpack]$ wine --version Wine 20020904 If anyone's got it running for webpack, I'd be glad to hear your version number and OS... Cheers, SimonArticle: 47271
Sure not your fault, I experienced also that after configuring an XC2S200 needs to be powered down, before loading a new configuration. When not doing so the behaviour seems unpredictable. "Tony Dean" <td@emu.com> wrote in message news:33aa9b10.0209212030.73e929f4@posting.google.com... > I've just spent the last week in hell, baffled as to why my FPGA > design was not working. Was I really THAT bad of a VHDL coder? > > To make a long and painful story short, it wasn't my fault. And it > wasn't Synplicity's fault (sorry about that call to tech support). It > is Xilinx's fault. I don't mean to bash Xilinx, as their products are > great, but they blew this one. > > The problem: > When using JTAG to configure a Spartan II FPGA (and perhaps Virtex > too), the first configuration after power up will work, but subsequent > ones will not. > > Worse, the re-configurations may APPEAR to work, because something did > get downloaded, and the Impact programmer chirps "PROGRAM SUCCEEDED". > But after 3 days of dissecting your code and backing all the way out > to a trivial case (e.g. hard set a few output pins to 01010101 or some > such), you'll find as I did that the part just did not get > reprogrammed correctly. > > The problem is that the FPGA needs to have its configuration memory > cleared before starting a new download, and the JTAG configuration > inexplicably neglects to do this. Whether this is an oversight in the > Impact downloader and can be fixed in a subsequent release (I'm using > 4.2wP3.x), or whether it is an oversight in the chip design, I don't > know. > > What you have to do is this: before reprogramming the FPGA via JTAG, > you must pull the PROGRAM_BAR pin low (that clears the memory), and > then bring it back high (if you leave it low, Impact will give you an > error, saying the boundary-scan chain test failed). > > That you can't just use the JTAG pins to reprogram the part, and have > to do this little dance with the PROGRAM pin is a flat out bug in my > opinion. It should be fixed, or this workaround printed in 24-point > red letters in the user's manual. > > I sincerely hope this posting helps some future poor sap(s) from > wasting as much time as I did. > > -tdArticle: 47272
Maybe slightly off topic, but sombody here know where to get Xilinx FPGA in europe in small quantities for a reasonable price ? Marcel "Frank Adalater" <localfun66@hotmail.com> wrote in message news:ami2co$5pb3f$1@ID-34826.news.dfncis.de... > Hi, > > i want to take a look at the fpga systems to learn something more about. So > I want to buy a development package but they are all so expensive. Isnīt > there any cheap development package where i donīt to spent so much money or > maybe a computer simulation of such an fpga chip? > > > > Thanks Frank > >Article: 47273
Ray Andraka wrote: > Not reliably. The HC7404 works because it is used as an amplifier, which can > be done with a simple inverter. An FPGA has too many gain stages between the > pins to be abused as an amplifier in an oscillator circuit. While it may work > on the bench, it will not reliably start and maintain the fundamental > frequency with variations in temp, process, and voltage. Why not use an > integrated xtal oscillator instead of a simple crystal? The costs are nearly > the same. > Do you happen to know if there's a 32.??Khz xtal osc. that uses sufficiently little power that it can run off a 3V coin cell ? or with some power-down mode ? The reason I ask is that I'd dearly like to replace the PIIX4 southbridge + CombiIO functions in an FPGA/CPLD and about the only thing that's hard is the real time clock. I've already got a CPLD on board so it could be replaced by a CoolRunner (II ?) to take the RTC function. Maybe this is just to perfectionist & I'll just bite the bullet and find a stand-alone PC-compatible RTC.Article: 47274
Rick Filipkiewicz wrote: > > Ray Andraka wrote: > > > Not reliably. The HC7404 works because it is used as an amplifier, which can > > be done with a simple inverter. An FPGA has too many gain stages between the > > pins to be abused as an amplifier in an oscillator circuit. While it may work > > on the bench, it will not reliably start and maintain the fundamental > > frequency with variations in temp, process, and voltage. Why not use an > > integrated xtal oscillator instead of a simple crystal? The costs are nearly > > the same. > > > > Do you happen to know if there's a 32.??Khz xtal osc. that uses sufficiently > little power that it can run off a 3V coin cell ? or with some power-down mode ? > The reason I ask is that I'd dearly like to replace the PIIX4 southbridge + > CombiIO functions in an FPGA/CPLD and about the only thing that's hard is the real > time clock. I've already got a CPLD on board so it could be replaced by a > CoolRunner (II ?) to take the RTC function. > > Maybe this is just to perfectionist & I'll just bite the bullet and find a > stand-alone PC-compatible RTC. If you want to run of a coin cell, what's going to keep track of the time ? You could look at : Dallas DS32KHz - Not cheap, but high precision, and with battery pin. Intersil used to make a programmable OSC chip Or, make your own using HEF4069, or HEF4007 and a 32Khz xtal. Philips PCF8563 - docs suggest it defaults to 32KHz CLKOUT, so should power up without i2c BUS activity ? You could put a Read-Time state engine into the FPGA, and then the PCF8563.RTC can keep track of time, with << 1 uA Icc when in OFF mode. Seems the OSC is less of a problem, than the question of who's in charge of the time. -jg
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