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"spyng" <ospyng@yahoo.com> schrieb im Newsbeitrag news:b34a8c79.0206240917.7140fb66@posting.google.com... > hi, > any one know is it possible to control the skew betwen different > signal on Virtex2. for i.e, between i_data[0], i_data[1] > ....i_data[7]. > > from what I understand NET "i_data[*]" MAXSKEW = 4 ns, will only > constraint the skew of the individual signal. You can define timing groups. But dont ask me about the details, havnt does this yet. > the problem I have is that my external data(5 bit) and clock is not > align properly (don't ask me why, I have try that), so we are trying > to sample the input data with 8 different phase of the internal clock > and then determind which phase is the best to use. Hmm, what is the data frequency? The clock is comming (missaligned ) into the FPGA? -- MfG FalkArticle: 44601
"Ken Mac" <aeu96186@yahoo.co.uk> schrieb im Newsbeitrag news:af7c2v$a5k$1@dennis.cc.strath.ac.uk... > So, the questions: > > It is my intention to pass data between two clock domains: CLK and CLKDIV - > can I use the VHDL below to synthesise CLKDIV and use this as the source > clock for the CLKDIV domain? > > Will this avoid metastability issues? I would suggest to use a clock enable for your lower speed logic. This will keep the whole thing on one clock doamin. No problem. > PS - I know I could use an asynchronous FIFO to cross the domain but I want > the smallest solution possible in terms of slices and want to avoid state > machines... You get what you pay for. Crossing clock domains isnt just done with a bunch of wires (in most cases) -- MfG FalkArticle: 44602
I don't believe anyone has support for this in any of the place and route tools. Please let me know if you do. If the tools would support minimum and maximum delays you could accomplish this. Unfortunately in the past I have had to result to hard routing in the parts to ensure that all of the data bus uses identical paths throughout the chip. Of course it is best if you can use the IOB latch and not worry about this. But several designs I have completed were in Orca 2T parts which did not have latches in the IOB. Bryan "spyng" <ospyng@yahoo.com> wrote in message news:b34a8c79.0206240917.7140fb66@posting.google.com... > hi, > any one know is it possible to control the skew betwen different > signal on Virtex2. for i.e, between i_data[0], i_data[1] > ....i_data[7]. > > from what I understand NET "i_data[*]" MAXSKEW = 4 ns, will only > constraint the skew of the individual signal. > > the problem I have is that my external data(5 bit) and clock is not > align properly (don't ask me why, I have try that), so we are trying > to sample the input data with 8 different phase of the internal clock > and then determind which phase is the best to use. > > so there will be 8 set of input data sample register and they can not > be in the IOB. But we will have to make sure that all the 5 bit input > data have the same delay to all the 8 set of data sample reg. > > Xilinx actually have a app note on this (xapp 255), but I am not > convince that they are able to control the skew between different > signal. correct me if I am wrong. > > any help? > thanks > pyngArticle: 44603
I am looking at buying a new PC and it is hard to find units that come with anything other than XP. The Xilinx web site does not say their tools run under XP. But has anyone tried it? Any word on how well it works? Any word on when Xilinx will be supporting XP? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44604
If you need a symmetric clock internally (which unless you are using both edges
of the clock, you don't), the DLL can be set up for a 50% duty cycle without
having to double the clock, in fact that is the default.
If you use the period constraint on the clock input and use the CLKDLL's the
timing constraint gets recreated on the individual clocks with the appropriate
period constraints.
cfk wrote:
> I have a design where I am bringing in a 66 Mhz oscillator and dividing by
> two to get 33 Mhz for my PCI interface. The reason I am doing this is that I
> was taught that clock symmetry is better when the oscillator is brought into
> the logic and divided by two. But what I seem to see, is that this concept
> confuses timing user constraints and the ISE tools. It seems that the tools
> now consider the net where CLK/2 is sourced to not be a global net and
> further, the options of making timing constraints are non-existent from the
> windows gui editor. I suppose that I can define a TNM_NET, but perhaps the
> proper thing is to use a 33Mhz oscillator instead and give up on my
> conception that oscillator/2 is the way to go for an FPGA design. I woud
> appreciate any comments on this.
>
> Charles
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44605Vincent, Verify UART communications in the other direction. Can you display STDOUT via the HyperTerminal? The "Hello World" example would test communication in this direction. Verify that your board clock frequency is the same as what is set in the MHS file. Make sure the SD and EN UART signals are driven properly in the MHS file. Verify your UCF pin settings. Matt Vincent JADOT wrote: > Hi, > > I m a beginer on xilinx fpga, i used to work with altera fpga. I'm > trying to compare, both embedded processor solution for a typical > application, for choosing the best one (speed of calculations). > So, i try to run the Xilinx's microblaze examples on the memec spartan2 > demo board. > When i try the interrupt_controller examples, i can't send data (number) > with the windows "hyper terminal" ( i configure all my com port: > 19200bps,8bits,no parity,1 stop bit,noflow control). > There'snt number echoes on screen. The program run, but i can change the > frequency of LED rotation. > Thanks.Article: 44606
Hi, If you use the Megawizard functions to generate your RAM/ROM in Quartus II, then the tool maps the RAM/ROM into embedded memory blocks. I do that and hence that was not the reason for Leo reporting lower LCs. I guess Leo is just a more efficient synthesizer than Quartus. Thanks, Prashant "Endric Schubert" <endric_@_bridges2silicon.com> wrote in message news:<0pPQ8.6786$cD4.361980989@newssvr21.news.prodigy.com>... > One of the reasons Leo may have reported much less LE is the fact that LEO > can extract RAM and ROM and implement it in embedded memory blocks. I don't > know whether Quartus can do that. > > Regarding newer versions of Leo: I use 2002a_49. It has some quirks fixed so > it is worth a try... > > Endric > -- > Bridges2Silicon, Inc. > Endric Schubert, PhD > 471 E. Evelyn Ave. > Sunnyvale, CA 94086 > www.bridges2silicon.com > > > "Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message > news:3d006605$0$236$cc9e4d1f@news.dial.pipex.com... > > > Since LS-Altera is free (Albeit the GUI is buggy.) even for QII Web > > > Edition users (Although I rather get a free crippled ModelSim instead.), > > > there really is no reason to use Quartus II native synthesis tool at all > > > other than maybe some beginners may appreciate it because they won't > > > have to import an EDIF netlist from LS-Altera. > > > > I echo the sentiment NOT to use quartus for synthesis, just place and > route > > with the edif output from leonardo. > > If you use the buggy (but useable) gui you can even do the quartus place > and > > route from within Leo. > > > > I would however use Q2 to generate PAR constraints as you can get more > > detailed than using Leo alone. > > > > I'm still using Leo 2001_1d, anyone any comments on the newest release? > > > > > > > >Article: 44607
John_H,
I believe that you are correct in that after the gbuf, secondary
routing resources are being used. I did a test case, and the node
directly after the gbuf was H_GENOUT in a VirtexE. The node after the
gbuf was V_GLOBAL in a Virtex2, but soon after, it hit a switchbox to
be re-routed.
I am sorry for creating the confusion, and I thank the group for
informing me otherwise. I really did not do the proper amount of
homework before I posted.
For those who are interested, below is my quick and dirty test case.
Newman
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library unisim;
use unisim.vcomponents.all;
use IEEE.Vital_Timing.all;
-- pragma translate_on
entity gbuftest is
port (
CLK : in std_logic; -- system clock
RESET : in std_logic; -- synchronous reset
TESTOUT : out std_logic); -- test output
end gbuftest;
architecture rtl of gbuftest is
component BUFG
-- synopsys translate_off
generic(
TimingChecksOn : boolean := DefaultTimingChecksOn;
InstancePath : string := "*";
Xon : boolean := DefaultXon;
MsgOn : boolean := DefaultMsgOn;
tpd_I_O : VitalDelayType01 := (0.100 ns, 0.100 ns);
tipd_I : VitalDelayType01 := (0.000 ns, 0.000 ns)
);
-- synopsys translate_on
port(
O : out std_ulogic;
I : in std_ulogic
);
end component;
signal ireset_s : std_logic;
signal iresetout_s : std_logic;
signal itestout_s : std_logic;
begin -- rtl
-- Misc assignments
TESTOUT <= itestout_s;
SYNC_PROC1: process (CLK, ireset_s)
begin -- process SYNC_PROC
if ireset_s = '1' then -- asynchronous reset (active
hi)
itestout_s <= '0';
elsif CLK'event and CLK = '1' then -- rising clock edge
itestout_s <= not itestout_s;
end if;
end process SYNC_PROC1;
SYNC_PROC2: process (CLK)
begin
if CLK'event and CLK = '1' then
iresetout_s <= RESET;
end if;
end process SYNC_PROC2;
reset_gbuf : BUFG
port map (
O => ireset_s,
I => iresetout_s);
end rtl;
John_H <johnhandwork@mail.com> wrote in message news:<3D16825F.BA4705EB@mail.com>...
> I thought gbufs only - repeat ONLY - went to clocks or immediately to
> secondary routing. Has this changed since Virtex such that a global
> signal is available for more than just clocks? A clock enable or
> synchronous reset would be too nice.
>
> I've done my share of poking down into the VirtexE and Virtex-II with
> the FPGA editor program and didn't see any new global resource
> connectivity (other than clocks) but I wasn't looking hard at the time.
>
Article: 44608Ken, I did not review your code too much, but my personal opinion is that it is easier to implement a derived clock transfer via clock enables, rather than generating another clock domain. If you do it by deriving another clock domain, keep the interface simple and localized. You have to understand the transfer boundary very well. NewmanArticle: 44609
rickman <spamgoeshere4@yahoo.com> writes: > Neil Franklin wrote: > > > > Tests run by my office mate, just before I moved to this office im Mai > > (so I do not know the details, just the result: sci/eng get Athlons). > > But if we don't have any info on how the tests were done, then we don't > know under what conditions the results will change. Both Athlons and > P4s have been changing over the last year. I only know the tests were done fairly recently (stongly assume this year). I will be seeing this colleague again on Thursday and can ask him then. > I also do not understand exactly how the CPU heats up as you do > "computation". Have they changed the OS so that the CPU stops when you > don't give it something to do? That is standard in PCs since about 10 years in anything which is not DOS-based Windows (which ignores this hardware feature). My 5 year old AMD K6-2/350 running Linux has an pronounced increase in ventilator (thermaly controlled) noise as soon as I compile something, within split seconds. > Does the clock slow down when running > the IDLE task? Slow or even switch off until next interrupt occurs. > > > > >don't doubt, but I can't belive they would design a desktop that won't > > > > >crunch at top clock all day. > > > > The largest part of Intels users will be running Office, that does not > > crunch numbers for long times. > > But even if 1% of the machines are running workhorse code, it would be > immediately recognized if they were slower than other machines with much > lower clock ratings. That is aparently exactly the observation made. > lower clock ratings. In my last position we had a bank of servers to > crunch FPGA work and we would have known there was a problem. We had > one P4 which was used by the group designing in the largest FPGAs we > were using. We did not see a problem and this 1 GHz machine ran faster > than the 750 MHz P3s. a) perhaps they were sufficiently cooled, being server machines b) perhaps the problem only starts above 1GHz. > I can't belive Intel is making a chip or that > DELL, etc are making machines that slow down running "normal" FPGA > apps. 99% of their customers could not care. And cost saving ist cost saving. Lower price or can be spent on 0.1GHz more, which markets itsself better. That counts in todays PC marketplace. The victory of crapitalism. > > > > The P4 has a clock throttling thermal diode. In case of overheat, it > > > > cuts the clock in half. Early systems had poorly implemented cooling, > > > > so you could trigger it during normal use on the early desktops. > > > > And first generation P4s get/got awfully hot. Them GHz come with lots > > of current usage. > > We are no longer buying first gen P4s. They are up to 2.5 GHz or so and > have reduced geometries with lower power demands. Reduced geometry and increased clock. And power goes up linear with clocking. > I will check with > some former coworkers and see if they have a newer, faster P4 server > now. I will check on Thursday. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - Make your code truely free: put it into the public domainArticle: 44610
Falk, Thanks for the reply. > > Will this avoid metastability issues? > > I would suggest to use a clock enable for your lower speed logic. This will > keep the whole thing on one clock doamin. No problem. Sounds good - how do I ensure the clock enables are used on the device from my VHDL? I get the feeling I am a small snippet of code away from making the leap! Thanks for your time, Ken --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.368 / Virus Database: 204 - Release Date: 29/05/2002Article: 44611
rickman wrote:
>
>
> Netscape already has that capability. But the fact is that under
> Windows the process is far from perfect. The last copy of web pack I
> downloaded took me days due to the overnight download stopping before it
> was done so that even if I did not have to start over, it spent many
> hours a night doing nothing. Then I was within 2KBytes of being
> complete and it locked. When I attempted to restart, it claimed that
> there was no file in the first place.
>
Use a download utility like Gozilla or Download Accelerator to
download something like ISE WebPACK.
It takes me about 14 hours to download ISE WebPACK with a 56K modem . .
.
The data rate I get is about 4KB/s.
> I don't care where the fault is, I don't care if there is "better"
> software. It is not a difficult thing to produce a CD. There really is
> no good reason that Xilinx can't do that for the Webpack software and
> service packs. So charge $10 like Netscape does. A CD in quantity 1000
> costs about $2 to make with covers. Please keep the $8.
>
I don't know if it is still continuing, but a few months ago, I
ordered a WebPACK CD from Insight Electronics free of charge.
http://208.129.228.206/solutions/kits/xilinx/webpack/
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 44612Ken, I looked at your code a little bit more. I typically do not use variables in synthesizable code, but you are using a combinatorial process to generate what I suspect is your derived clock, and a suspect that it will be glitchy. Newman > library IEEE; > use IEEE.std_logic_1164.all; > > entity eMetastabilityTesting is > port ( > CLK : in STD_LOGIC; > CLKDIV : out std_logic > ); > end eMetastabilityTesting; > > > architecture aMetastabilityTesting of eMetastabilityTesting is > > constant DIV : integer := 5; > signal cnt : integer range 0 to DIV := 0; > > begin > > process(clk) > begin > if rising_edge(clk) then > if cnt <= (DIV-1) then > cnt <= cnt + 1; > else > cnt <= 1; > end if; > end if; > end process; > > process(cnt) > variable tmp : std_logic; > > begin > if cnt <= (DIV-1) then > tmp := '0'; > else > tmp := '1'; > end if; > > clkdiv <= tmp; > end process; > > > end architecture; > > > // END VHDL codeArticle: 44613
> ------------------------------------------------------------------- > > Eleventh ACM International Symposium on > Field-Programmable Gate Arrays > > Monterey, California > > February 23-25 2003 > > Submissions due: September 27, 2002 > web site: http://fpga2003.ece.ubc.ca > > The ACM/SIGDA International Symposium on Field-Programmable Gate > Arrays is the premier conference for presentation of advances > in all areas related to FPGA technology. For FPGA 2003, we > are soliciting submissions describing novel research and > developments in the following (and related) areas of interest: > > - FPGA Architecture: Combined FPGA fabric with system blocks > (memory, processors, etc.), Logic block & routing architectures, > I/O structures and circuits, new commercial architectures, > Field-Programmable Interconnect Chips and Devices (FPIC/FPID). > > - CAD for FPGAs: Placement, routing, logic optimization, technology > mapping, system-level partitioning, logic generators, testing > and verification, CAD for FPGA-based accelerators, CAD for > incremental FPGA design. > > - Applications: Innovative use of FPGAs, exploitation of FPGA > features, novel circuits, high-performance and low-power/ > mission-critical applications, DSP techniques, uses of > reconfiguration, FPGA-based cores. > > - FPGA-based and FPGA-like computing engines: Compiled accelerators, > reconfigurable computing, adaptive computing devices, systems > and software. > > - Rapid-prototyping: Fast prototyping for system-level design, > Multi-Chip Modules (MCMs), logic emulation. > > Authors are invited to submit English language PDF of their paper > (12 pages maximum) and panel proposals by September 27, 2002 by > E-mail to fpga2003@ecs.umass.edu. Notification of acceptance > will be sent by November 22, 2002. The authors of accepted > papers will be required to submit the final camera-ready copy > by December 6, 2002. A proceedings of the accepted papers will > be published by ACM, and included in the Annual ACM/SIGDA CD-ROM > Compendium publication. > > Address questions to: > > Russ Tessier, Program Chair, FPGA 2003 > University of Massachusetts > 309G Knowles Engineering Building > Amherst, MA 01003 > phone: (413) 545-0160 > fax: (413) 545-1993 > fpga2003@ecs.umass.edu > > The committee consists of: > > General Chair: Steve Trimberger, Xilinx > Program Chair: Russ Tessier, U. Mass.-Amherst > Publicity Chair: Steve Wilton, U. British Columbia > Finance Chair: Martine Schlag, UCSC > Panel Chair: Herman Schmit, CMU > > Program Committee: > > Ray Andraka, Andraka Consulting > Michael Butts, Cadence > Vaughn Betz, Altera > Jason Cong, UCLA > Andre DeHon, Caltech > Eugene Ding, Mentor Graphics > Scott Hauck, U. Washington > Rajeev Jayaraman, Xilinx > Sinan Kaptanoglu, Altera > Tom Kean, Algotronix > Arun Kundu, Actel > Miriam Leeser, Northeastern U. > Wayne Luk, Imperial College > Margaret Marek-Sadowska, UCSB > Majid Sarrafzadeh, UCLA > Martine Schlag, UCSC > Herman Schmit, CMU > Russ Tessier, U. Mass.-Amherst > Steve Trimberger, Xilinx > Qiang Wang, Lattice Semiconductor > Steve Wilton, U. British Columbia > Martin Wong, U. Texas > Zeljko Zilic, McGill U. > > > Sponsored by ACM SIGDA, with support from industry. > > Please visit the web site < http://fpga2003.ece.ubc.ca > for > more information. > > -----------------------------------------------------------Article: 44614
Kevin Brace wrote: > > Rick Filipkiewicz wrote: > > > > > > But I still don't understand why Xilinx can't send a few 100 WebPACK CDs to each of the > > distis ? or at least allow anyone with a fast net connection and a CD-R/W the right to > > make & ship copies for a media charge + postage ? > > I don't know if it is still continuing, but a few months ago, I > ordered a WebPACK CD from Insight Electronics free of charge. > > http://208.129.228.206/solutions/kits/xilinx/webpack/ > > Kevin Brace (In general, don't respond to me directly, and respond > within the newsgroup.) Thanks Kevin, the web page is still good so I have made my request. He's hoping it works!!! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44615
rickman wrote:
>
> >
> > I don't know if it is still continuing, but a few months ago, I
> > ordered a WebPACK CD from Insight Electronics free of charge.
> >
> > http://208.129.228.206/solutions/kits/xilinx/webpack/
>
> Thanks Kevin, the web page is still good so I have made my request.
> He's hoping it works!!!
>
Hopefully you will get the CD (Actually a CD-R.).
I believe the CD is sent through USPS.
Let news:comp.arch.fpga know when you actually get the CD.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 44616That document is available at IEEE.ORG: E.B. Hogenauer, "An Economical Class of Digital Filters for Decimation and Interpolation," IEEE Trans. Acoust., Speech, Signal Process., ASSP-29, 155–162, April, 1981. This article may also be of interest: http://www.chipcenter.com/networking/technote015-2.html Tom "Jerzy Gbur" <furia@wp.pl> wrote in message news:<3d16f50d@news.vogel.pl>... > Hallo All! > I'm looking for recipe how to truncating or rounding stages in CIC filter. > Every documents says that clue is in E. B. Hogenauer article: "An ecomical > class of digital filters for decimationand interpolation". > But I can't find this document at all. > Can You help me? > > Best regards > furiaArticle: 44617
I could make it with 16MHz and times 4, but 8X is problematic, -- Best Regards, ----------------------------------------------------------------- Xu Qijun Engineer OKI Techno Centre (S) Pte Ltd Tel: 6770-7081 Fax: 6779-2382 Email: qijun677@oki.com "XU QIJUN" <qijun677@oki.com> wrote in message news:3d12919d$1@news.starhub.net.sg... > Hi, > > I am using a Spartan-II 100K to do some experiments on clock multiplication. > I successfully made a X2 and X4, then problem occurs when I coded one extra > DLL to make it 8. Following is the bug, > Whats your comments? > > ERROR:Place:1726 - Could not find an automatic placement for the following > components: > CLKIN of type GCLK IOB is placed at P77. > dll2x of type DLL is unplaced. > clk2xg of type GCLK BUFFER is unplaced. > dll4x of type DLL is unplaced. > clk4xg of type GCLK BUFFER is unplaced. > dll8x of type DLL is unplaced. > clk8xg of type GCLK BUFFER is unplaced. > lckpad of type GCLK BUFFER is unplaced. > ERROR:Place:1727 - Xilinx requires using locate constraints to preplace such > connected GCLK/GCLKIO/DLL components. > Total REAL time to Placer completion: 2 secs > Total CPU time to Placer completion: 1 secs > > ----------------------------------------------------------------- > > Following are the codes: > > module dll_standard (CLKIN, CLK2X, CLK4X, CLK8X, LOCKED); > input CLKIN; > output CLK2X, CLK4X, CLK8X, LOCKED; > > wire RESET; > wire CLKIN_w, RESET_w, CLK2X_dll, CLK4X_dll, LOCKED2X, LOCKED4X; > wire LOCKED2X_delay, RESET4X; > wire LOCKED4X_delay, RESET8X; > wire logic1; > assign RESET = 1'b0; > > assign logic1 = 1'b1; > > assign CLKIN_w = CLKIN; > assign RESET = RESET_w; > > CLKDLL dll2x (.CLKIN(CLKIN_w), .CLKFB(CLK2X), .RST(RESET_w), > .CLK0(), .CLK90(), .CLK180(), .CLK270(), > .CLK2X(CLK2X_dll), .CLKDV(), .LOCKED(LOCKED2X)); > BUFG clk2xg (.I(CLK2X_dll), .O(CLK2X)); > SRL16 rstsrl (.D(LOCKED2X), .CLK(CLK2X), .Q(LOCKED2X_delay), > .A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1)); > assign RESET4X = !LOCKED2X_delay; > > CLKDLL dll4x (.CLKIN(CLK2X), .CLKFB(CLK4X), .RST(RESET4X), > .CLK0(), .CLK90(), .CLK180(), .CLK270(), > .CLK2X(CLK4X_dll), .CLKDV(), .LOCKED(LOCKED4X)); > BUFG clk4xg (.I(CLK4X_dll), .O(CLK4X)); > SRL16 rstsr2 (.D(LOCKED4X), .CLK(CLK4X), .Q(LOCKED4X_delay), > .A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1)); > assign RESET8X = !LOCKED4X_delay; > // assign CLK4X_B = ~ CLK4X; > > CLKDLL dll8x (.CLKIN(CLK4X), .CLKFB(CLK8X), .RST(RESET8X), > .CLK0(), .CLK90(), .CLK180(), .CLK270(), > .CLK2X(CLK8X_dll), .CLKDV(), .LOCKED(LOCKED_dll)); > BUFG clk8xg (.I(CLK8X_dll), .O(CLK8X)); > > BUFG lckpad (.I(LOCKED_dll), .O(LOCKED)); > > endmodule > > >Article: 44618
Hi everyone i am using an APEX20k400e, and my design use lots of ESB memory in it, the design function correctly when power up, but if I run for a very long time(about 5 min), it will behavir in an error way, if I reset, the design still in error if I power down and then up immediatly, the design still in error, I think it is because the device is too hot, I touch the device with my finger, it is very very very hot, so if any one have any sugession?Article: 44619
Thanks ! "jerry1111" <jerry1111@wp.pl> wrote in message news:af7doh$hh8$1@news.tpi.pl... > > But I can't find the driver. > > > > I try to use the setup application under the directory "drivers" in the path > > where I installed MaxPlus+II > > but it looked useless. > > > > any other ideas? or Maxplus just doesn't support WinXP? > > AFAIR you should manually install ByteBlaster driver for NT > selecting it as 'sound card' or joystick. Description > is available on www.altera.com > > jerry > >Article: 44620
I know Xilinx says that they don't yet support XP, but I've been using it and have had no problems (other than those I would normally have). On the contrary, I'm much happier, because instead of rebooting ~6 times per day on ME I'm rebooting once every six days. -Kevin "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3D1770B5.11971E9E@yahoo.com... > I am looking at buying a new PC and it is hard to find units that come > with anything other than XP. The Xilinx web site does not say their > tools run under XP. But has anyone tried it? Any word on how well it > works? > > Any word on when Xilinx will be supporting XP? > > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44621
Hi I am new to CPLD. I only worked on Xilinx FPGA before. As far as I know, by Xilinx Foundation or other software like Synplicity, we generate bit file and download to FPGA and then FPGA works. How about Lattice ispLSIv2192VE? What kind of software is used? And what kind of file is generated to download? I have two Xilinx PROM and one Virtex, and I know how to download. By PROM Format software, I transfer the bit file to mcs file and download to FPGA, but how about I add one Lattice ispLSI at the end? Thanks a lot!Article: 44622
Min frequency for the DLL input is 25 MHz for reliable operation. That falls
out from the length of the delay line used in there. Additionally, Xilinx does
not recommend cascading more than 2 DLLs because each adds jitter, and more than
2 in a line can lead to problems with excessive jitter in the last one, although
if you keep your power supply clean, the input clock with low jitter and don't
switch to many single ended I/O on the same bank as the clock input, you can
probably get away with a cascade of 3.
The placer can figure out how to put the DLLs if they are connected to do a
clockx4. Anything more than that you will have to either place in the
floorplanner, in the UCF file or in the source using LOC constraints because the
placer can't figure out how to put them.
XU QIJUN wrote:
> I could make it with 16MHz and times 4, but 8X is problematic,
>
> --
> Best Regards,
> -----------------------------------------------------------------
> Xu Qijun
> Engineer
> OKI Techno Centre (S) Pte Ltd
> Tel: 6770-7081 Fax: 6779-2382
> Email: qijun677@oki.com
> "XU QIJUN" <qijun677@oki.com> wrote in message
> news:3d12919d$1@news.starhub.net.sg...
> > Hi,
> >
> > I am using a Spartan-II 100K to do some experiments on clock
> multiplication.
> > I successfully made a X2 and X4, then problem occurs when I coded one
> extra
> > DLL to make it 8. Following is the bug,
> > Whats your comments?
> >
> > ERROR:Place:1726 - Could not find an automatic placement for the following
> > components:
> > CLKIN of type GCLK IOB is placed at P77.
> > dll2x of type DLL is unplaced.
> > clk2xg of type GCLK BUFFER is unplaced.
> > dll4x of type DLL is unplaced.
> > clk4xg of type GCLK BUFFER is unplaced.
> > dll8x of type DLL is unplaced.
> > clk8xg of type GCLK BUFFER is unplaced.
> > lckpad of type GCLK BUFFER is unplaced.
> > ERROR:Place:1727 - Xilinx requires using locate constraints to preplace
> such
> > connected GCLK/GCLKIO/DLL components.
> > Total REAL time to Placer completion: 2 secs
> > Total CPU time to Placer completion: 1 secs
> >
> > -----------------------------------------------------------------
> >
> > Following are the codes:
> >
> > module dll_standard (CLKIN, CLK2X, CLK4X, CLK8X, LOCKED);
> > input CLKIN;
> > output CLK2X, CLK4X, CLK8X, LOCKED;
> >
> > wire RESET;
> > wire CLKIN_w, RESET_w, CLK2X_dll, CLK4X_dll, LOCKED2X, LOCKED4X;
> > wire LOCKED2X_delay, RESET4X;
> > wire LOCKED4X_delay, RESET8X;
> > wire logic1;
> > assign RESET = 1'b0;
> >
> > assign logic1 = 1'b1;
> >
> > assign CLKIN_w = CLKIN;
> > assign RESET = RESET_w;
> >
> > CLKDLL dll2x (.CLKIN(CLKIN_w), .CLKFB(CLK2X), .RST(RESET_w),
> > .CLK0(), .CLK90(), .CLK180(), .CLK270(),
> > .CLK2X(CLK2X_dll), .CLKDV(), .LOCKED(LOCKED2X));
> > BUFG clk2xg (.I(CLK2X_dll), .O(CLK2X));
> > SRL16 rstsrl (.D(LOCKED2X), .CLK(CLK2X), .Q(LOCKED2X_delay),
> > .A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1));
> > assign RESET4X = !LOCKED2X_delay;
> >
> > CLKDLL dll4x (.CLKIN(CLK2X), .CLKFB(CLK4X), .RST(RESET4X),
> > .CLK0(), .CLK90(), .CLK180(), .CLK270(),
> > .CLK2X(CLK4X_dll), .CLKDV(), .LOCKED(LOCKED4X));
> > BUFG clk4xg (.I(CLK4X_dll), .O(CLK4X));
> > SRL16 rstsr2 (.D(LOCKED4X), .CLK(CLK4X), .Q(LOCKED4X_delay),
> > .A3(logic1), .A2(logic1), .A1(logic1), .A0(logic1));
> > assign RESET8X = !LOCKED4X_delay;
> > // assign CLK4X_B = ~ CLK4X;
> >
> > CLKDLL dll8x (.CLKIN(CLK4X), .CLKFB(CLK8X), .RST(RESET8X),
> > .CLK0(), .CLK90(), .CLK180(), .CLK270(),
> > .CLK2X(CLK8X_dll), .CLKDV(), .LOCKED(LOCKED_dll));
> > BUFG clk8xg (.I(CLK8X_dll), .O(CLK8X));
> >
> > BUFG lckpad (.I(LOCKED_dll), .O(LOCKED));
> >
> > endmodule
> >
> >
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44623Your fingertip is a pretty good thermometer: If you can maintain contact, the package is below 60 or 65 degree C. If you pull away fast, it is above 70 degrees If it sizzles, it is above 100 degrees. Usually, the junction-to-case thermal resistance is fairly low, so the case temperture is just a little lower than the junction temperature (unless you have a big heatsink). If you can keep your fingertip on the packcage, its junction is most likely below the worst-case temperature, and the circuitry should work. Peter Alfke, FPGA Applications ============================= ssy wrote: > Hi everyone > > i am using an APEX20k400e, and my design use lots of ESB memory in it, > > the design function correctly when power up, but if I run for a very > long time(about 5 min), it will behavir in an error way, > > if I reset, the design still in error > > if I power down and then up immediatly, the design still in error, > > I think it is because the device is too hot, I touch the device with > my finger, it is very very very hot, > > so if any one have any sugession?Article: 44624
Hi, I have a design working with Xilinx Virtex FPGA Device. The design is in VHDL. I want to migrate from FPGA to ASIC. I have few questions about this. 1. The MAP report gives "Total Equivalent gate count for the design" and "Additional JTAG gate count for IOBs". Is sum of these the true indication of ASIC gates? What i mean is if i migrate to ASIC can I safely assume that i will be utilizing only these many number of gates? 2. What happens to maximum operating speed of my design? Will it remain same as given in "Post place and Route Static Timing report" ? or will it increse or decrease? 3. What happens to BlockRAMs? Will they become external to ASIC or they still work as they were inside FPGA? Could anyone please answer these questions?
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