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I thought I would try converting a design developed using free Xilinx web tools to one based on free Altera web tools (QuartusII). When I try to compile the design I get errors about unsupported features of the compiler. Is there a way around this ? Am I using the right version of the tools ? It'd be nice if I could have designs that would work with either toolset. What I've found missing so far is parameterized modules and non-constant bit selects. It's easy enough to work around these things, but it is annoying to have to. Is there an alternative ? Thanks RobArticle: 44826
XPower gives you the average power over the simulation run, not a dynamic power. I beleive what he is looking for is a time varying power plot that is a function of the activity in the design. I don't know of a tool that does that, although you might be able to use XPower in a series of simulations to
do that (very tedious though)
Martin wrote:
> Hello Arash,
>
> the tool which functionality you describe is available. It's called XPower and takes in the implemented design and if you want a *.vcs-file (I think that's the extension) with simulation data from e.g. Modelsim. With that tool you can very accurately predict how much power your design is going to use.
>
> The tool comes as part of ISE and WebPack and you'll find it in the P&R section of the 'Implement Design' Part in the Project Navigator.
>
> Martin
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44827I'm using Synopsys FPGA Express with ActiveHDL. Sysntesis fails when I try to use procedures stored in custom package that is added to project. The failure message is as follows: alu.vhd(line 6) No selected element named MY_OWN_PACKAGE is defined for this prefix. where line 6 contains: use WORK.MY_OWN_PACKAGE.all; I managed to solve the problem only when i use GUI for that and export data after. But it makes too much movements every time so i still hope for better solution. Best regards OlegArticle: 44828
We are looking for partners to help us market our MP3 ASIC core and design services. A brief introduction of our MP3 ASIC core is available at www.owlowl.com. Please email me for more information. Best regards, Zhijian Hu Zhijian.hu@owlowl.comArticle: 44829
Hi,
I've used Altera parts in the past, Flex 10KE and APEX 20KE. Altera always
recommended that MAXPLUS (or QUARTUS) be allowed to choose the pinouts
before locking the pins down for performance reasons. Does this apply to
Xilinx parts as well? Board routing would be much easier if I could assign
the device pins before routing.
TIA,
Bill
______________________________________________________________________
Posted Via Uncensored-News.Com - Still Only $9.95 - http://www.uncensored-news.com
<><><><><><><> The Worlds Uncensored News Source <><><><><><><><>
Article: 44830"Thomas" <ThoLei@gmx.net> schrieb im Newsbeitrag news:ee77a68.-1@WebX.sUN8CHnE... > Dear Community! > > In my application I need to let the FPGA communicate with the PC. (I want to write a small C++ program where you can enter some values) > The demo board I use offers an serial RS-232 port but only with TXin and RXout pins. So I suppose I must use some software handshake? > And i have to implement a serial/parallel converter within the FPGA (vhdl code?). A complete RS232 UART inluding 16 byte FIFO in both directions is ready to use available for Spartan-II devices. Have a look at the xapps from Xilinx (AFAIK 223 or so). For other families, you may try the UART from www.opencores.org If you need a intelligent salve inside the FPGA, I recommend having a look at xapp213, which delivers a 8 bit RISC processor, ready to use. -- MfG FalkArticle: 44831
As long as you design with your layout in mind - knowing that the data flow can be stretched at the input and the output - everything should be fine. I use IOB output flops for almost all my logic which needs the full period for the data from the previous pipeline stage to get from wherever in the chip it happens to be, through minimal logic (if any) and to the flop. For instance, taking a BlockRAM output in my old Spartan-II design straight to an output would be ugly for my timing; by registering the output (some combining with other results in a mux-like arrangement) after minimal or no logic, I can meet the period constraint. The tools haven't let me down wrt my locked pins in the smaller devices. I imagine you'll get good results with the larger devices as well as long as you're aware of the delays. Bill wrote: > Hi, > > I've used Altera parts in the past, Flex 10KE and APEX 20KE. Altera always > recommended that MAXPLUS (or QUARTUS) be allowed to choose the pinouts > before locking the pins down for performance reasons. Does this apply to > Xilinx parts as well? Board routing would be much easier if I could assign > the device pins before routing. > > TIA, > > Bill > > ______________________________________________________________________ > Posted Via Uncensored-News.Com - Still Only $9.95 - http://www.uncensored-news.com > <><><><><><><> The Worlds Uncensored News Source <><><><><><><><> >Article: 44832
>i am using the Synario 4.1 compiler for a target GAL chip in VHDL code. I am >facing a rather strange problem. > >Synaio does not seem to recognise the std_logic_unsigned package. it keeps >giving a 'the following variable has not been declared' compilation error. i >ran the same code in Max Plus and it works well. > >Could anyone give any suggestions on this..? do the >Synopsys libraries (of which std_logic_unsigned is a part of) need to be >imported into Synario? if so how? >any other suggestions please? You'll need to compile std_logic_unsigned package into the ieee library as one of your compilation file, prior to compiling your design. I had to do that with Synplify. Ben --------------------------------------------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------Article: 44833
Hi,
I am developping a Java program based on JBITS which can generate a
bitstream to configure the Xilinx Virtex FPGA directly. But I don't know
whether there's some kind of tools can help check whether this bitstream
can actually work on FPGA instead of burnning it.
I know there's Virtex Device Simulator can do some simulation on
bitstream, will the simulator check the bitstream and give some warning
if there're two dirvers for one line?
Thanks!
Weifeng
Article: 44834
The 10 and 20K are notoriously bad for pinlocking, partly because the IOBs are
registered in only one direction (Xilinx 4K was also problematic due to insufficient
routing). If you register your IOBs, then in most cases pin assignments are not going
to give you problems in the VirtexII parts. That said, you should have at least some
thought as to how the device is to be used, so pick your pins intelligently to make
things easier on the PAR tools. Generally speaking, data should flow across the chip
(assuming you have arithmetic in the data path) so that it is perpendicular to the
carry chains. The RAM is distributed around the chip for the larger devices, and is
along the left and right edges for the smallest ones.
Bill wrote:
> Hi,
>
> I've used Altera parts in the past, Flex 10KE and APEX 20KE. Altera always
> recommended that MAXPLUS (or QUARTUS) be allowed to choose the pinouts
> before locking the pins down for performance reasons. Does this apply to
> Xilinx parts as well? Board routing would be much easier if I could assign
> the device pins before routing.
>
> TIA,
>
> Bill
>
> ______________________________________________________________________
> Posted Via Uncensored-News.Com - Still Only $9.95 - http://www.uncensored-news.com
> <><><><><><><> The Worlds Uncensored News Source <><><><><><><><>
>
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44835Obviously, any pin-locking puts a constraint on the chip-internal routing. The Altera CPLD-like rigid routing structure is far more sensitive to this than the more ASIC-like Xilinx routing structure. If you use some common sense you should be able to lock the pins, but remember: Data likes to flow horizontally, carry is going bottom to top. So feed data from the right or left, with the LSB at the bottom, and the chip-routing will love it. Of course, if the chip is underutilized and the clock rate is low, you will be successful with even the worst pin-assignment. With the Xilinx routing structure, nothing is inherently impossible. :-) Peter Alfke, Xilinx Applications =================================== Bill wrote: > Hi, > > I've used Altera parts in the past, Flex 10KE and APEX 20KE. Altera always > recommended that MAXPLUS (or QUARTUS) be allowed to choose the pinouts > before locking the pins down for performance reasons. Does this apply to > Xilinx parts as well? Board routing would be much easier if I could assign > the device pins before routing. > > TIA, > > Bill > > ______________________________________________________________________ > Posted Via Uncensored-News.Com - Still Only $9.95 - http://www.uncensored-news.com > <><><><><><><> The Worlds Uncensored News Source <><><><><><><><> >Article: 44836
Although I am not a fan of it (I prefer ISE WebPACK's XST over LeonardoSpectrum.), you should use LeonardoSpectrum-Altera Level 1 instead of Quartus II's native synthesis tool. LeonardoSpectrum supposedly has better VHDL language support than Quartus II's native synthesis tool (I feel like the Verilog language coverage is about the same.), and also gives you much better QoR (Quality of Results). Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Rob Finch wrote: > > I thought I would try converting a design developed using free Xilinx web > tools to one based on free Altera web tools (QuartusII). When I try to > compile the design I get errors about unsupported features of the compiler. > Is there a way around this ? Am I using the right version of the tools ? > It'd be nice if I could have designs that would work with either toolset. > What I've found missing so far is parameterized modules and non-constant bit > selects. It's easy enough to work around these things, but it is annoying to > have to. Is there an alternative ? > > Thanks > RobArticle: 44837
Peter, I feel like you 56k modem's calculation is somewhat too optimistic. When I do downloads with a 56k modem, I don't get anymore than 4k bytes/s. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.)Article: 44838
...and shift register logic runs top to bottom. Peter Alfke wrote: > [snip] Data likes to flow horizontally, carry is going bottom to top. So feed data > from the > right or left, with the LSB at the bottom, and the chip-routing will love it. > [snip] > > Peter Alfke, Xilinx Applications > =================================== > [Bill got snipped, for bandwidth's sake] -- Davis Moore Software Engineer -- PLP Implementation Tools Xilinx, Inc. davism@xilinxnospam-thanks.com "I zigged when I should have zagged." - Bugs BunnyArticle: 44839
I should have learned from Bugs. The SRL data path is not routing constrained in the same fashion as the carry logic in the intra-CLB routing. The top-to-bottom flow of the SRL data path only applies within a CLB - which has little to do with optimal pin assignment. Davis Moore wrote: > ...and shift register logic runs top to bottom. > > > "I zigged when I should have zagged." - Bugs Bunny -- Davis Moore Software Engineer -- PLP Implementation Tools Xilinx, Inc. davism@xilinxnospam-thanks.comArticle: 44840
A few more caveats: Certain pins are used for configuration, and certain pins are used for boundary scan. Clocks are preferrably applied to certain pins. And on the newer devices, the different optional I/O voltages and standards should be grouped in banks = half-edges of the chip. LVDS pin-pairs must be placed properly. In other words, it pays to look at the device pin-outs ( ball-outs?) before you start the board lay-out, but that still leaves you a lot of freedom in the pin-assignment (ball-assignment?) Peter Alfke ============================== Peter Alfke wrote: > Obviously, any pin-locking puts a constraint on the chip-internal routing. > The Altera CPLD-like rigid routing structure is far more sensitive to this than the > more ASIC-like Xilinx routing structure. If you use some common sense you should be > able to lock the pins, but remember: > Data likes to flow horizontally, carry is going bottom to top. So feed data from the > right or left, with the LSB at the bottom, and the chip-routing will love it. > Of course, if the chip is underutilized and the clock rate is low, you will be > successful with even the worst pin-assignment. With the Xilinx routing structure, > nothing is inherently impossible. :-) > > Peter Alfke, Xilinx Applications > =================================== > Bill wrote: > > > Hi, > > > > I've used Altera parts in the past, Flex 10KE and APEX 20KE. Altera always > > recommended that MAXPLUS (or QUARTUS) be allowed to choose the pinouts > > before locking the pins down for performance reasons. Does this apply to > > Xilinx parts as well? Board routing would be much easier if I could assign > > the device pins before routing. > > > > TIA, > > > > Bill > > > > ______________________________________________________________________ > > Posted Via Uncensored-News.Com - Still Only $9.95 - http://www.uncensored-news.com > > <><><><><><><> The Worlds Uncensored News Source <><><><><><><><> > >Article: 44841
Ray Andraka wrote: > XPower gives you the average power over the simulation run, not a dynamic power. I beleive what he is looking for is a time varying power plot that is a function of the activity in the design. I don't know of a tool that does that, although you might be able to use XPower in a series of simulations to > do that (very tedious though) maybe manipulate the various VCD dump commands so that they create series of files at a granularity of, say, a few usec. This might also solve the Xpower very-large-VCD files problem.Article: 44842
Right, that is what I was trying to say. It does involve quite a bit more manual intervention, so I think you are better off with a big VCD file if you can handle it in the case of a fixed power number. For dynamic power, I don't think there are many options.
Rick Filipkiewicz wrote:
> Ray Andraka wrote:
>
> > XPower gives you the average power over the simulation run, not a dynamic power. I beleive what he is looking for is a time varying power plot that is a function of the activity in the design. I don't know of a tool that does that, although you might be able to use XPower in a series of simulations to
> > do that (very tedious though)
>
> maybe manipulate the various VCD dump commands so that they create series of files at a granularity of, say, a few usec. This might also solve the Xpower very-large-VCD files problem.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44843Hello, I am converting a design from gdf maxplus II format to vhdl to better control synthesis. What place and route tools target the Flex 10K30A for synthesis? I tried Quartus but it does not seem to support the Flex 10K30A. SalmanArticle: 44844
Hiya, > What I've found missing so far is parameterized modules and non-constant bit > selects. It's easy enough to work around these things, but it is annoying to > have to. Is there an alternative ? I happen to know for a fact that Altera is adding support for a lot of currently missing VHDL features in version 2.1. In the meantime I suggest that you use Leonardo Spectrum. It's a very mature tool with language coverage that will surprise you (at least it did to me). If you want to be sure that your design is supported by Quartus II 2.1, contact your local disty or Altera FAE. They should have beta copies of the full 2.1 version at the moment, as the full version is scheduled for release in the next few weeks. The free web edition should follow a few weeks after. Heard it will support one of the new Stratix devices as well. BenArticle: 44845
Hallo Holger, > I'd like to change the contents of the flex 10K internal memory EABs > (LPM_RAM). The EABs are connected with a .mif file and the > design is compiled to a .sof File. Is it possible to modify the content > of the EABs just by changing the .sof-File (without recompiling)? > Is a tool for this available? At this moment there is no official way to do this. I have heard that this is possible in the upcoming 2.1 version of Quartus, but I am not sure whether this feature is also possible in all families. Contact your local Altera FAE for more details. Best regards, BenArticle: 44846
Weifeng Xu <wxu@ecs.umass.edu> writes: > I am developping a Java program based on JBITS which can generate a > bitstream to configure the Xilinx Virtex FPGA directly. But I don't know > whether there's some kind of tools can help check whether this bitstream > can actually work on FPGA instead of burnning it. The generation process of JBits should ensure that, as long as you use the automatic routing. If you set individual PIPs, all bets are off. > I know there's Virtex Device Simulator can do some simulation on > bitstream, will the simulator check the bitstream and give some warning > if there're two dirvers for one line? Do not know that one. I would doubt it. -- Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/ Hacker, Unix Guru, El Eng HTL/BSc, Programmer, Archer, Roleplayer - Make your code truely free: put it into the public domainArticle: 44847
Does anyone know if Chameleon Systems is still in businness? I have been trying to speak to someone there with no luck for the last couple of weeks. Thanks, -ArrigoArticle: 44848
Converting between allegedly similar architectures is always sub-optimal. If you use the powerful unique features of the original architecture ( in your case the Clock Enable, distributed RAM, dual-port BlockRAM, SRL16, DCM and perhaps the DCI of the Xilinx architecture), you have to give those up, but you get no benefit from the advantages (whatever they are) of the Altera architecture. So you end up with the worst of both worlds, a bland design that is inferior to any design optimized for either of the two architectures. Synthesis can patch over some of these issues, but never give you the true optimum. Peter Alfke, obviously biased, but trying to be fair. ======================================== Rob Finch wrote: > I thought I would try converting a design developed using free Xilinx web > tools to one based on free Altera web tools (QuartusII). When I try to > compile the design I get errors about unsupported features of the compiler. > Is there a way around this ? Am I using the right version of the tools ? > It'd be nice if I could have designs that would work with either toolset. > What I've found missing so far is parameterized modules and non-constant bit > selects. It's easy enough to work around these things, but it is annoying to > have to. Is there an alternative ? > > Thanks > RobArticle: 44849
Why do such a small design in an HDL in the first place? It isn't giving you much but the process is killing you. "Sandeep Unni" <sandeepmec@hotmail.com> wrote in message news:<yjbU8.10481$DB.139224@news1.east.cox.net>... > Hi, > > i am using the Synario 4.1 compiler for a target GAL chip in VHDL code. I am > facing a rather strange problem. > > Synaio does not seem to recognise the std_logic_unsigned package. it keeps > giving a 'the following variable has not been declared' compilation error. i > ran the same code in Max Plus and it works well. > > Could anyone give any suggestions on this..? do the > Synopsys libraries (of which std_logic_unsigned is a part of) need to be > imported into Synario? if so how? > any other suggestions please? > > Many thanks in advance > > Cheers, > Sandeep
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