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Can Synplify infer case statements as ROM in blockRAM? (Tell me yes.) -KevinArticle: 43526
Never mind... I think I got the answer on this one. "Kevin Neilson" <kevin-neilson@removethistextattbi.com> wrote in message news:WHUG8.7680$352.784@sccrnsc02... > Can Synplify infer case statements as ROM in blockRAM? (Tell me yes.) > -Kevin > >Article: 43527
--------------71090DC669C5AB0BD691A742 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Kevin, Starting with Synplify 7.1 you can infer ROMs using Block SelectRAM instead of LUTs for Virtex, Virtex-E, Virtex-II, and Virtex-II Pro in the following cases: - For Virtex/Virtex-E the address line must be between 8 to 12 bits. - For Virtex-II/Pro the address line must be between 9 to 14 bits. - The address lines must be registered with a simple flip-flop (no resets or enables, etc) or the ROM output can be registered with enables or sets/resets, however, not both sets/resets and enables. The flip-flops’ sets/resets can be either synchronous or asynchronous. In the case where asynchronous sets/resets are used Synplify will create registers with the sets/resets and then either AND or OR these registers with the output of the BlockRAM. Steve Kevin Neilson wrote: > Can Synplify infer case statements as ROM in blockRAM? (Tell me yes.) > -KevinArticle: 43528
I am trying to find a free FPGA compiler/emulator. Does anyone know where I can find one. I tried to download Xnf-tools and use with diglog but I did not have much luck. Any suggestion will be highly appreciated. Thanks in advance. ArunArticle: 43529
This is a typical problem that the software cannot solve. That's why engineers get a job... Tullio K PRASAD wrote: > > hello all > i would like to know regarding this > suppose i have a synchronous design A and design B. > if i want to synchronise both the designs, > and also do so,and synthesize the whole design, > then how will the setup and hold times violations > be adjusted and the maximum clock speed will be obtained for > the fpga? will they be actually taken care of by the software..? > can any help me.please write in detail... -- ---------------------------------------------------- ----------------------------------------------------------- ---------------------------------------------------- ----------------------------------------------------------- ---------------------------------------------------- ----------------------------------------------------------- ---------------------------------------------------- -----------------------------------------------------------Article: 43530
In article <acgcie$ae9$1@slb2.atl.mindspring.net>, Jan Gray <jsgray@acm.org> wrote: >5. Another approach is to use Comeau C++, based upon Edison Design Group's >superb retargetable C++ front end. That emits C that you *might* be able to >compile with lcc. See http://www.comeaucomputing.com/. Most likely, but it would require a custom port of Comeau C++. -- Greg Comeau 4.3.0 NEWS: New Windows Backends + 'export' IN MAY! Comeau C/C++ ONLINE ==> http://www.comeaucomputing.com/tryitout World Class Compilers: Breathtaking C++, Amazing C99, Fabulous C90. Comeau C/C++ with Dinkumware's Libraries... Have you tried it?Article: 43531
Phil Hays messed up and wrote: > > Falk Brunner wrote: > > > we have a design with a XCS30XL, which is utilized to 96%. > > Bad thing is, P&R takes about 30!!! minutes on a Athlon 500. The design uses > > a lot of TBUFs and DP-RAMS. > > Are there some tricks to speed up things? Some floorplanning? Timing > > constraints? > > To find out what floorplanning might gain you, once you get a route > completed, re-route the same design with a completely locked down > floorplan. > > How to completely lock down a design: (ucf flow) > Open the graphical floorplanner, read in your design, from the > "floorplan" menu select. ^^^^^^^^^^^^^^^^^^^^^^^^^^Select What??? Should be: From the "floorplan" menu select "replace all with placement". > From the file menu select "ucf flow", then write constraints to a new > file. > With a text editor, merge the placement constraints into your ucf file. > Rerun ngdbuild, map and par. Talking to myself.. -- Phil HaysArticle: 43532
"Gr?ory HERMANT" <gregory.hermant@isis-ingenierie.com> wrote in message news:<acg6d3$u84$1@s1.read.news.oleane.net>... > Anybody know where I can get orcad symbol for virtex II XC2V-6000 FF1152 ? > > greg For an FPGA with this huge number of pins, I'd recommend: create your own symbol, showing the exact functional pinout of your design. Create the symbol as a heterogenous device (in OrCAD-speak, a device in which every part can have a different layout and pin-names). Each part of the device will have the pins related to a function (e.g. a bus or a number of related buses and pins) and every pin will have a meaningful name (the best way - use exactly the same names of you HDL/schematic chip design). You can create the OrCAD symbol even before you have a final pinout - you can always edit the device and change pin numbers. Make one part of the device all power and configuration pins - this reduces clutter in the schematic. This method appears to be a lot of work, but in my experience it doesn't take more than a few days to create the symbol. It will make debugging your card much easier. One warning: Once you've defined the number of parts in your symbols, OrCAD doesn't allow change. If you want to add or delete a part, you have to create a new symbol and then copy all parts from the old symbol. WHEN YOU DO THAT, ORCAD DOESN'T COPY PIN NUMBERS ! great usability, I'd like to meet the genius who had specified this OrCAD feature.Article: 43533
>One warning: Once you've defined the number of parts in your symbols, OrCAD >doesn't allow change. If you want to add or delete a part, you have to create >a new symbol and then copy all parts from the old symbol. WHEN YOU DO THAT, >ORCAD DOESN'T COPY PIN NUMBERS ! great usability, I'd like to meet the genius >who had specified this OrCAD feature. Is the info stored in a text file that's reasonable to read/write? If so, I'd suggest that somebody write a script that will read a file of some format that you like, check against the Xilinx pin list, and write out the OrCAD symbol file(s). If not, send a bug report. 1/2 :) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 43534
Hello all, I have read few weeks ago in xilinx site about the Chip Scope, seems like a good solution for testing a FPGA. I am thinking to purchase it but first I would like some comments about this tool from someone who have used it. Can someone help me on this? Greetings, HarrisArticle: 43535
There is some good constraint info in the following link http://www.xilinx.com/support/techtips/documents/timing/presentation/timingcsts3_1i/index.htm I have some questions. When there is a constraint like OFFSET IN 10 ns BEFORE clk Does it mean that the data WILL be available at an input pin of the FPGA 10ns before the clock edge arrives at an input pin of the FPGA? (i.e. we are informing the FPGA) and OFFSET OUT 10ns AFTER clk Does it mean that data SHOULD be valid at an output pin of the FPGA 10ns after the clock edge arrives at an input pin of the FPGA. (i.e. we are ordering the FPGA to meet some timing) Early answers will be appreciated. Thanks, Searcher of knowledge Tullio Grassi <tullio@physics.umd.edu> wrote in message news:<3CEC21A6.C96B66A5@physics.umd.edu>... > This is a typical problem that the software cannot solve. > That's why engineers get a job... > > Tullio > > K PRASAD wrote: > > > > hello all > > i would like to know regarding this > > suppose i have a synchronous design A and design B. > > if i want to synchronise both the designs, > > and also do so,and synthesize the whole design, > > then how will the setup and hold times violations > > be adjusted and the maximum clock speed will be obtained for > > the fpga? will they be actually taken care of by the software..? > > can any help me.please write in detail... > > -- > > ---------------------------------------------------- > ----------------------------------------------------------- > > > ---------------------------------------------------- > ----------------------------------------------------------- > > ---------------------------------------------------- > ----------------------------------------------------------- > > ---------------------------------------------------- > -----------------------------------------------------------Article: 43536
Austin, Rick: Thanks for the replies. Hopefully, using the full swing won't cause a problem, as the datarate will never exceed 15MHz... I think initially I will connect the differential signals into the LVDS, and route them straight out of the FPGA again, and varify with a scope / logic analyser that the io blocks in LVDS configuration, with apropriate external resistors, are 'seeing' the signals correctly. Thanks also for the comments on smd work. I think I'll put myself down for a third arm graft as soon as it's medically possible! ;-) Rumour has it that we can get a special bit for our soldering station that is a pair of tweasers, for easy removl of smd components... Cheers, Chris Saunter : The LVDS differential receivers will work with full swing signals, but they : won't meet he 420 MHz speed specification that way. Best is to use the : voltage swing it was designed for: 400 mV peak to peak. : Since Virtex II also has clamp diodes to Vcco and ground, operating it at 3.3 : V Vcco will clamp a 5V signal to a diode drop above Vcco, so some series : resistance is required, either in the driver, or physically separate. : I suggest a resistor network to do the job for you. : As for soldering SM parts, get a good magnifying glass setup, and a good : solder station, a pair of tweezers, another soldering station (so you can heat : both ends if you need ot pull one off -- this works really well, you just need : three hands .... I place the tweezers in my teeth to flip the SM part off if I : soldered the wrong one on there the first time), and some small diameter : solder. : It is just a technical skill, not unlike playing a musical instrument. : Practice...... : AustinArticle: 43537
Hi , is there a way to describe , using verilog RTL, a module that will recieve two multiple bit buses and combine them in a DDR fashion. I know that after synthesis this module will be interputed to multiple instanteations of the FDDRRSE unit. thanks, EyalArticle: 43538
Falk Brunner <Falk.Brunner@gmx.de> wrote: > we have a design with a XCS30XL, which is utilized to 96%. > Bad thing is, P&R takes about 30!!! minutes on a Athlon 500. The design uses > a lot of TBUFs and DP-RAMS. Is that a long time ?! Sorry, I'm used to doing 10 passes @ 1.5+ hours each. Or a whole weekend's worth. > Are there some tricks to speed up things? Some floorplanning? Timing > constraints? Locking your IO and your block RAMs will help significantly. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 43539
Hello, Anyone know where I can get one of these chips for cheap? Arrow.com looks like the only place to buy the -3 speed part. Thanks. SalmanArticle: 43540
Ray Andraka <ray@andraka.com> wrote: > Our current machines have the very fast SCSI drives, and if the PAR gets into > paging the performance is very much tied to the SCSI performance. I noticed > that the fast IDE drives still have the slower rotation speeds (7200 rpm vs > 15000 on my scsi drives). Is that an issue, or perhaps by using more of the > cheaper IDEs in a Raid configuration I get better overall performance at a > similar or smaller price? Better to buy more RAM and avoid swapping? Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 43541
I have an old LCA design for a 2018 (can you believe it!), which unfortunately requires some minor updating. However the 5 1/4" source floppies are no longer usable and are corrupted. I can't get the installer to install the 2018 device files. I still have the horrible dongle, but now need the program! I've so far searched in vain, and am wondering if someone out there still has a copy of this ancient application which they could send me. Any help is most appreciated! Regards, Joe.Article: 43542
Thanks for your responce. "Carl Daniel" <cpdaniel@pacbell.net> wrote in message news:<xPuC8.317$RB5.51554486@newssvr14.news.prodigy.com>... > Take your pick. There are existing PCI ethernet cards fitting both of those > descriptions. Generally, the simpler PCI cards incorporate a fairly small > amount of RAM which they manage as a circular buffer into which packets are > inserted. Appox. how much Ram. E.g. 4*(MaxFrameSize) = ~6Kbytes?? > Most of the more sophisticated cards use memory structures in > main (PCI) memory to store packets. Is this acheived using DMA. How? > Having the card write directly into > main memory can result in a more efficient system since it avoids one entire > copy of the data. I say "can be more efficient" because whether it actually > is more efficient will depend on many factors, some beyond the control of > the PCI card. > > -cd > > "Shane Mulligan" <mememeiii@hotmail.com> wrote in message > news:c25fdd8.0205090442.50ba0b4@posting.google.com... > > I need some help, I'm designing and coding a PCI Ethernet adapter using > > the verilog language. Its something I want to do as a personel project > > and its not work related so I can't get any help there. > > > > The adapter will comply with PCI rev 2.2 and 802.3 standards. I have > > looked at both specs but they as you can expect neither spec make no > > reference to interfacing to the other. > > > > I have run into a few problems. > > 1) I need to know what happens when the ethernet card receives packets > > from another ethernet station? How is the data transfered to the CPU or > > Memory? I don't know if I need both a Master and a Target PCI state > machine. > > All I know is that I think there are only two possible ways this can be > > achieved. > > > > a) See I'm trying to figure out if I need a master state machine in the > PCI > > interface to initiate the transaction i.e. it would request the bus and > > perform a merory write. > > > > or > > > > b) The ethernet adapther receives the packet and notifies the pci core. > > The PCI core then aserts its INTC to the Interupt router would then assert > > its IRQ to the CPU. The CPU then initiates and interrupt acknowlegedment > > and the interrupt router then forwards an interruot vector fot the PCI > > card. This informs the CPU of the ISR (Interupt service routine) and it > > then initiates a read to the ethernet card. In this case the adapter > > card only needs to have a target state machine. > > > > Here's were I need help. Your responce is appreciated...... > > > > Shane Mulligan.Article: 43543
Eyal, There is currently no way for the Synthesis tools (FPGA Express, LeonardoSpectrum, Synplify, XST) to infer the FDDRRSE primitives. They have to be instantiated. Steve Eyal Shachrai wrote: > Hi , > > is there a way to describe , using verilog RTL, a module that will > recieve two > multiple bit buses and combine them in a DDR fashion. I know that > after synthesis this module will be interputed to multiple > instanteations of the FDDRRSE unit. > > thanks, > EyalArticle: 43544
So, for high end audio using the heavily oversampled ADC, the conversion is apparantly Sigma Delta. Isn't this ADC architecture extremely jitter tolerant? Allan Herriman wrote: > On 21 May 2002 06:18:53 -0700, mrand@my-deja.com (Marc Randolph) > wrote: > > >allan_herriman.hates.spam@agilent.com (Allan Herriman) wrote in message news:<3ce9d59e.89244667@netnews.agilent.com>... > >> On Mon, 20 May 2002 16:42:46 +0200, "Marcel" > >> <marcelgl-hates-spam@xs4all.nl> wrote: > >> > >> >Hi, > >> > > >> >I need to generate a tunable clock in the range from 18Mhz - 30Mhz with > >> >100Hz resolution. > >> >I was considering to use an external VCO and implement a PLL in the FPGA. > >> >But I was wondering is this > >> >also can be done in another way. > >> > > >> >The main problem is that the clock is used for audio D/A, so it must be a > >> >low jitter clock. > >> > > >> >Any suggestions ? > >> > >> 1. Audio is usually only sampled at certain rates, e.g. 8.0000kHz > >> (and multiples), 11.025kHz (and multiples) and 48.000kHz (and > >> multiples.) > >> ... why do you need to use other frequencies? And why 100Hz > >> resolution on your high speed clock? > > > >Either he isn't sampling audio for human consumption, or he is making > >a typo and meant 18kHz to 30 kHz. > > > >30 MHz is WAY overkill for anything that humans could hope to hear. > >Over 500 times overkill. > > The ADC requires a clock that's many times the sampling frequency, > typically 256, 384 or 512 times as high. So 18MHz to 30MHz sounds > quite reasonable for the high speed clock, and isn't likely to be a > typo. > > Regards, > Allan.Article: 43545
Hi, I'm somewhat new to the newsgroup and this may be an old topic, but why is it that Xilinx keeps the format of its .ncd files a secret? This seems a bit strange to me since Xilinx offers a tool (XDL) which translates the NCD file to an ASCII file in XDL format, which is not proprietary (though documentation for XDL isn't easily found).Article: 43546
If you don't initialize the RAM the place&route tool will normally initialize it to zero. I always get warnings during place&route informing me that the blockRAM is being initialized to zero by default. "Noman" <noman_news@hotmail.com> wrote in message news:ee76e24.-1@WebX.sUN8CHnE... > Hi, > > I am trying to use a RAM of length 32k (32768) where each element of the RAM is 16 bits wide. I am required to have all the elements of the RAM initialized to zero before processing data elements and placing them in the RAM. > > This can be done by assigning initial values during the simulation but when synthesizing the synthesizer ignores the initial values. > > How can I initialize the RAM elements to zero so that after synthesis I get the same result as after simulation???? > > Thanks. > > NomanArticle: 43547
If Xilinx releases too much infomation, it would be easier for another company to make a gate array or clone FPGA that could use the same bit file. "Jeff" <jeff@Despammed_Domain.com> wrote in message news:b862d891.0205231110.2da2e57f@posting.google.com... > Hi, > > I'm somewhat new to the newsgroup and this may be an old topic, but > why is it that Xilinx keeps the format of its .ncd files a secret? > This seems a bit strange to me since Xilinx offers a tool (XDL) which > translates the NCD file to an ASCII file in XDL format, which is not > proprietary (though documentation for XDL isn't easily found).Article: 43548
Noman wrote: > How can I initialize the RAM elements to zero so that after synthesis I get the same result as after simulation???? A real RAM has no reset input, so if you really need to clear ram at any time, you must provide the hardware to do the write cycles. Maybe a state machine or CPU interface. -- Mike TreselerArticle: 43549
RAM internal to the FPGA or external RAM? If it is internal RAM, it initializes to zero by default on start up unless you provide other initial values (in which case you need to instantiate the RAM primitives and add both INIT
generics and INIT attributes to set alternative start up values. For external RAM, the RAM does not start up in a defined state, you have to provide a state machine to run through the RAM writing the initialization values in
your design.
Noman wrote:
> Hi,
>
> I am trying to use a RAM of length 32k (32768) where each element of the RAM is 16 bits wide. I am required to have all the elements of the RAM initialized to zero before processing data elements and placing them in the RAM.
>
> This can be done by assigning initial values during the simulation but when synthesizing the synthesizer ignores the initial values.
>
> How can I initialize the RAM elements to zero so that after synthesis I get the same result as after simulation????
>
> Thanks.
>
> Noman
--
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President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
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Compare FPGA features and resources
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